diff --git a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll --- a/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll +++ b/llvm/test/CodeGen/AMDGPU/clamp-modifier.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9 %s diff --git a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll --- a/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll +++ b/llvm/test/CodeGen/AMDGPU/divrem24-assume.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck %s define amdgpu_kernel void @divrem24_assume(i32 addrspace(1)* %arg, i32 %arg1) { ; CHECK-LABEL: @divrem24_assume( diff --git a/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll b/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll --- a/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=amdgcn -mattr=+fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s -; RUN: llc -march=amdgcn -mattr=-fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s +; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s +; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-fast-fmaf,-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FLUSH %s -; RUN: llc -march=amdgcn -mattr=+fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FASTFMA %s -; RUN: llc -march=amdgcn -mattr=-fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SLOWFMA %s +; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-FASTFMA %s +; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-fast-fmaf,+fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SLOWFMA %s ; FIXME: This should also fold when fma is actually fast if an FMA ; exists in the original program. diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll --- a/llvm/test/CodeGen/AMDGPU/frem.ll +++ b/llvm/test/CodeGen/AMDGPU/frem.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=FUNC %s diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll @@ -1,5 +1,6 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SIVI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=SIVI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s declare i64 @llvm.amdgcn.s.memtime() #0 @@ -7,10 +8,10 @@ ; GCN-DAG: s_memtime s{{\[[0-9]+:[0-9]+\]}} ; GCN-DAG: s_load_dwordx2 ; GCN: lgkmcnt -; GCN: buffer_store_dwordx2 -; GCN-NOT: lgkmcnt +; GCN: {{buffer|global}}_store_dwordx2 +; SIVI-NOT: lgkmcnt ; GCN: s_memtime s{{\[[0-9]+:[0-9]+\]}} -; GCN: buffer_store_dwordx2 +; GCN: {{buffer|global}}_store_dwordx2 define amdgpu_kernel void @test_s_memtime(i64 addrspace(1)* %out) #0 { %cycle0 = call i64 @llvm.amdgcn.s.memtime() store volatile i64 %cycle0, i64 addrspace(1)* %out diff --git a/llvm/test/CodeGen/AMDGPU/madmk.ll b/llvm/test/CodeGen/AMDGPU/madmk.ll --- a/llvm/test/CodeGen/AMDGPU/madmk.ll +++ b/llvm/test/CodeGen/AMDGPU/madmk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; FIXME: None of these trigger madmk emission anymore. It is still @@ -94,8 +94,8 @@ } ; GCN-LABEL: {{^}}v_s_madmk_f32: -; GCN: s_load_dword [[SREG:s[0-9]+]] -; GCN: buffer_load_dword [[VREG1:v[0-9]+]] +; GCN-DAG: s_load_dword [[SREG:s[0-9]+]] +; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]] ; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]] ; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]] ; GCN: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/omod.ll b/llvm/test/CodeGen/AMDGPU/omod.ll --- a/llvm/test/CodeGen/AMDGPU/omod.ll +++ b/llvm/test/CodeGen/AMDGPU/omod.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; IEEE bit enabled for compute kernel, no shouldn't use. diff --git a/llvm/test/CodeGen/AMDGPU/operand-folding.ll b/llvm/test/CodeGen/AMDGPU/operand-folding.ll --- a/llvm/test/CodeGen/AMDGPU/operand-folding.ll +++ b/llvm/test/CodeGen/AMDGPU/operand-folding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}fold_sgpr: ; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll --- a/llvm/test/CodeGen/AMDGPU/sdiv.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn | FileCheck %s -check-prefixes=FUNC,SI,GCN +; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx600 | FileCheck %s -check-prefixes=FUNC,SI,GCN ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global | FileCheck %s -check-prefixes=FUNC,SI,TONGA ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global | FileCheck %s -check-prefixes=FUNC,SI,GFX9 ; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood | FileCheck %s -check-prefixes=FUNC,EG @@ -16,50 +16,50 @@ define amdgpu_kernel void @sdiv_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; GCN-LABEL: sdiv_i32: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_mov_b32 s2, s6 +; GCN-NEXT: s_mov_b32 s3, s7 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, s10 +; GCN-NEXT: s_mov_b32 s1, s11 +; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v0 -; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v1 -; GCN-NEXT: v_xor_b32_e32 v4, v2, v3 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v3 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_hi_u32 v3, v2, v1 -; GCN-NEXT: v_mul_lo_u32 v5, v2, v1 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5 -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v3, v3, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v3, v2 -; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v2, v2, v0 -; GCN-NEXT: v_mul_lo_u32 v3, v2, v1 -; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, -1, v2 -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v3, v0 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 +; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v6 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3 +; GCN-NEXT: v_xor_b32_e32 v2, v6, v2 +; GCN-NEXT: v_mul_f32_e32 v3, 0x4f800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v1 +; GCN-NEXT: v_mul_hi_u32 v5, v3, v1 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v4 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v4, v4, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v4, v3 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v3, v3, v0 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; GCN-NEXT: v_add_i32_e32 v6, vcc, -1, v3 +; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v4, v0 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v4 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v7, v1 ; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v5, s[0:1] ; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GCN-NEXT: v_xor_b32_e32 v0, v0, v4 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; @@ -216,23 +216,23 @@ define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; GCN-LABEL: sdiv_i32_4: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_dword v0, off, s[8:11], 0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s7 +; GCN-NEXT: s_mov_b32 s6, s2 +; GCN-NEXT: s_mov_b32 s7, s3 +; GCN-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 30, v1 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 2, v0 -; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: sdiv_i32_4: @@ -310,25 +310,25 @@ define amdgpu_kernel void @slow_sdiv_i32_3435(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; GCN-LABEL: slow_sdiv_i32_3435: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_mov_b32 s10, s2 +; GCN-NEXT: s_mov_b32 s11, s3 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 +; GCN-NEXT: s_mov_b32 s8, s6 +; GCN-NEXT: s_mov_b32 s9, s7 ; GCN-NEXT: buffer_load_dword v0, off, s[8:11], 0 -; GCN-NEXT: s_mov_b32 s2, 0x98a1930b -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, 0x98a1930b +; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_mul_hi_i32 v1, v0, s2 +; GCN-NEXT: v_mul_hi_i32 v1, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 11, v0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 -; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: slow_sdiv_i32_3435: @@ -411,69 +411,69 @@ ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s10, -1 -; GCN-NEXT: s_mov_b32 s6, s10 -; GCN-NEXT: s_mov_b32 s7, s11 +; GCN-NEXT: s_mov_b32 s4, 0x4f800000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s2 -; GCN-NEXT: s_mov_b32 s5, s3 -; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 -; GCN-NEXT: s_mov_b32 s2, 0x4f800000 ; GCN-NEXT: s_mov_b32 s8, s0 ; GCN-NEXT: s_mov_b32 s9, s1 +; GCN-NEXT: s_mov_b32 s0, s2 +; GCN-NEXT: s_mov_b32 s1, s3 +; GCN-NEXT: s_mov_b32 s2, s10 +; GCN-NEXT: s_mov_b32 s3, s11 +; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v2 -; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v3 -; GCN-NEXT: v_xor_b32_e32 v8, v4, v5 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 -; GCN-NEXT: v_xor_b32_e32 v9, v6, v7 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v6, v1 +; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v0 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v7, v3 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v4 ; GCN-NEXT: v_xor_b32_e32 v2, v2, v5 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 +; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1 +; GCN-NEXT: v_xor_b32_e32 v8, v4, v5 +; GCN-NEXT: v_cvt_f32_u32_e32 v5, v2 ; GCN-NEXT: v_xor_b32_e32 v3, v3, v7 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v4 +; GCN-NEXT: v_xor_b32_e32 v9, v6, v7 +; GCN-NEXT: v_cvt_f32_u32_e32 v7, v3 ; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v5 -; GCN-NEXT: v_mul_f32_e32 v4, s2, v4 -; GCN-NEXT: v_mul_f32_e32 v5, s2, v5 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v7, v7 +; GCN-NEXT: v_mul_f32_e32 v4, s4, v5 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v6, v1 +; GCN-NEXT: v_mul_f32_e32 v5, s4, v7 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v2 ; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 ; GCN-NEXT: v_mul_lo_u32 v11, v5, v3 -; GCN-NEXT: v_sub_i32_e32 v12, vcc, 0, v7 -; GCN-NEXT: v_sub_i32_e32 v13, vcc, 0, v11 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6 +; GCN-NEXT: v_sub_i32_e32 v12, vcc, 0, v7 ; GCN-NEXT: v_cndmask_b32_e64 v6, v7, v12, s[0:1] +; GCN-NEXT: v_sub_i32_e32 v13, vcc, 0, v11 ; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v10 ; GCN-NEXT: v_cndmask_b32_e64 v7, v11, v13, s[2:3] ; GCN-NEXT: v_mul_hi_u32 v6, v6, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v7, v5 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v6, v4 ; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1] ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v5 ; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v10, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[2:3] ; GCN-NEXT: v_mul_hi_u32 v4, v4, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[2:3] ; GCN-NEXT: v_mul_hi_u32 v5, v5, v1 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v2 ; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v4 -; GCN-NEXT: v_add_i32_e32 v10, vcc, -1, v4 ; GCN-NEXT: v_mul_lo_u32 v11, v5, v3 -; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v5 -; GCN-NEXT: v_add_i32_e32 v13, vcc, -1, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, -1, v4 ; GCN-NEXT: v_subrev_i32_e32 v14, vcc, v6, v0 ; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v6 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v14, v2 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, v11, v1 +; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v5 +; GCN-NEXT: v_add_i32_e32 v13, vcc, -1, v5 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v11 -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v14, v2 ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3 ; GCN-NEXT: s_and_b64 s[2:3], s[2:3], s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v7, s[2:3] @@ -737,17 +737,17 @@ define amdgpu_kernel void @sdiv_v2i32_4(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ; GCN-LABEL: sdiv_v2i32_4: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s7 +; GCN-NEXT: s_mov_b32 s6, s2 +; GCN-NEXT: s_mov_b32 s7, s3 +; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v1 @@ -757,7 +757,7 @@ ; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v0, 2, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 2, v1 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: sdiv_v2i32_4: @@ -846,150 +846,150 @@ define amdgpu_kernel void @sdiv_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ; GCN-LABEL: sdiv_v4i32: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s19, 0xf000 -; GCN-NEXT: s_mov_b32 s18, -1 -; GCN-NEXT: s_mov_b32 s2, s18 -; GCN-NEXT: s_mov_b32 s3, s19 +; GCN-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_mov_b32 s2, s10 +; GCN-NEXT: s_mov_b32 s3, s11 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s10 -; GCN-NEXT: s_mov_b32 s1, s11 +; GCN-NEXT: s_mov_b32 s0, s14 +; GCN-NEXT: s_mov_b32 s1, s15 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 offset:16 -; GCN-NEXT: s_mov_b32 s6, 0x4f800000 +; GCN-NEXT: s_mov_b32 s14, 0x4f800000 +; GCN-NEXT: s_mov_b32 s8, s12 +; GCN-NEXT: s_mov_b32 s9, s13 ; GCN-NEXT: s_waitcnt vmcnt(1) ; GCN-NEXT: v_ashrrev_i32_e32 v8, 31, v0 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v9, 31, v4 -; GCN-NEXT: v_ashrrev_i32_e32 v10, 31, v1 -; GCN-NEXT: v_ashrrev_i32_e32 v11, 31, v5 -; GCN-NEXT: v_ashrrev_i32_e32 v12, 31, v2 -; GCN-NEXT: v_ashrrev_i32_e32 v13, 31, v6 -; GCN-NEXT: v_ashrrev_i32_e32 v14, 31, v3 -; GCN-NEXT: v_ashrrev_i32_e32 v15, 31, v7 -; GCN-NEXT: v_xor_b32_e32 v16, v8, v9 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v8, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v10, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v12, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v14, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v9, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v13, v6 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v15, v7 -; GCN-NEXT: v_xor_b32_e32 v17, v10, v11 -; GCN-NEXT: v_xor_b32_e32 v18, v12, v13 -; GCN-NEXT: v_xor_b32_e32 v19, v14, v15 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v8 ; GCN-NEXT: v_xor_b32_e32 v4, v4, v9 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v10 +; GCN-NEXT: v_xor_b32_e32 v15, v8, v9 +; GCN-NEXT: v_cvt_f32_u32_e32 v9, v4 +; GCN-NEXT: v_ashrrev_i32_e32 v11, 31, v5 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v11, v5 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v8, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v9, v9 ; GCN-NEXT: v_xor_b32_e32 v5, v5, v11 -; GCN-NEXT: v_xor_b32_e32 v2, v2, v12 -; GCN-NEXT: v_xor_b32_e32 v6, v6, v13 -; GCN-NEXT: v_xor_b32_e32 v3, v3, v14 -; GCN-NEXT: v_xor_b32_e32 v7, v7, v15 -; GCN-NEXT: v_cvt_f32_u32_e32 v8, v4 -; GCN-NEXT: v_cvt_f32_u32_e32 v9, v5 -; GCN-NEXT: v_cvt_f32_u32_e32 v10, v6 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v8 +; GCN-NEXT: v_cvt_f32_u32_e32 v8, v5 +; GCN-NEXT: v_mul_f32_e32 v9, s14, v9 +; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9 +; GCN-NEXT: v_ashrrev_i32_e32 v10, 31, v1 ; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v8 -; GCN-NEXT: v_rcp_iflag_f32_e32 v9, v9 -; GCN-NEXT: v_rcp_iflag_f32_e32 v10, v10 -; GCN-NEXT: v_mul_f32_e32 v8, s6, v8 -; GCN-NEXT: v_mul_f32_e32 v9, s6, v9 -; GCN-NEXT: v_mul_f32_e32 v10, s6, v10 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v10, v1 +; GCN-NEXT: v_xor_b32_e32 v16, v10, v11 +; GCN-NEXT: v_xor_b32_e32 v1, v1, v10 +; GCN-NEXT: v_mul_f32_e32 v8, s14, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v9, v4 +; GCN-NEXT: v_mul_lo_u32 v10, v9, v4 ; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8 -; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9 -; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v8, v4 -; GCN-NEXT: v_mul_lo_u32 v12, v8, v4 -; GCN-NEXT: v_mul_hi_u32 v13, v9, v5 -; GCN-NEXT: v_mul_lo_u32 v14, v9, v5 -; GCN-NEXT: v_sub_i32_e32 v15, vcc, 0, v12 +; GCN-NEXT: v_ashrrev_i32_e32 v12, 31, v2 +; GCN-NEXT: v_ashrrev_i32_e32 v13, 31, v6 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v12, v2 ; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v10, v6 -; GCN-NEXT: v_cndmask_b32_e64 v12, v12, v15, s[0:1] -; GCN-NEXT: v_sub_i32_e32 v15, vcc, 0, v14 -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v13 -; GCN-NEXT: v_mul_lo_u32 v13, v10, v6 -; GCN-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[2:3] -; GCN-NEXT: v_sub_i32_e32 v15, vcc, 0, v13 -; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v11 -; GCN-NEXT: v_cvt_f32_u32_e32 v11, v7 -; GCN-NEXT: v_rcp_iflag_f32_e32 v11, v11 -; GCN-NEXT: v_mul_f32_e32 v11, s6, v11 -; GCN-NEXT: v_cvt_u32_f32_e32 v11, v11 -; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v15, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v15, v11, v7 -; GCN-NEXT: v_mul_lo_u32 v20, v11, v7 -; GCN-NEXT: v_sub_i32_e32 v21, vcc, 0, v20 -; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v15 -; GCN-NEXT: v_cndmask_b32_e64 v15, v20, v21, s[6:7] -; GCN-NEXT: v_mul_hi_u32 v12, v12, v8 -; GCN-NEXT: v_add_i32_e32 v20, vcc, v12, v8 -; GCN-NEXT: v_subrev_i32_e32 v8, vcc, v12, v8 -; GCN-NEXT: v_mul_hi_u32 v12, v14, v9 -; GCN-NEXT: v_add_i32_e32 v14, vcc, v12, v9 -; GCN-NEXT: v_subrev_i32_e32 v9, vcc, v12, v9 -; GCN-NEXT: v_mul_hi_u32 v12, v13, v10 -; GCN-NEXT: v_add_i32_e32 v13, vcc, v12, v10 -; GCN-NEXT: v_subrev_i32_e32 v10, vcc, v12, v10 -; GCN-NEXT: v_mul_hi_u32 v12, v15, v11 -; GCN-NEXT: v_add_i32_e32 v15, vcc, v12, v11 -; GCN-NEXT: v_subrev_i32_e32 v11, vcc, v12, v11 -; GCN-NEXT: s_mov_b32 s16, s8 -; GCN-NEXT: s_mov_b32 s17, s9 -; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v20, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v14, s[2:3] -; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v13, s[4:5] -; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v15, s[6:7] -; GCN-NEXT: v_mul_hi_u32 v8, v8, v0 -; GCN-NEXT: v_mul_hi_u32 v9, v9, v1 -; GCN-NEXT: v_mul_hi_u32 v10, v10, v2 -; GCN-NEXT: v_mul_hi_u32 v11, v11, v3 -; GCN-NEXT: v_mul_lo_u32 v12, v8, v4 -; GCN-NEXT: v_add_i32_e32 v13, vcc, 1, v8 -; GCN-NEXT: v_add_i32_e32 v14, vcc, -1, v8 -; GCN-NEXT: v_mul_lo_u32 v15, v9, v5 -; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v12 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v12 -; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v9 +; GCN-NEXT: v_xor_b32_e32 v17, v12, v13 +; GCN-NEXT: v_xor_b32_e32 v2, v2, v12 +; GCN-NEXT: v_sub_i32_e32 v12, vcc, 0, v10 +; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v12, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v12, v8, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v13, v6 +; GCN-NEXT: v_xor_b32_e32 v6, v6, v13 +; GCN-NEXT: v_mul_lo_u32 v11, v8, v5 +; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v12 +; GCN-NEXT: v_cvt_f32_u32_e32 v12, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v10, v9 +; GCN-NEXT: v_sub_i32_e32 v13, vcc, 0, v11 +; GCN-NEXT: v_cndmask_b32_e64 v11, v11, v13, s[2:3] +; GCN-NEXT: v_rcp_iflag_f32_e32 v12, v12 +; GCN-NEXT: v_ashrrev_i32_e32 v14, 31, v7 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v14, v7 +; GCN-NEXT: v_xor_b32_e32 v7, v7, v14 +; GCN-NEXT: v_mul_f32_e32 v12, s14, v12 +; GCN-NEXT: v_cvt_u32_f32_e32 v12, v12 +; GCN-NEXT: v_mul_hi_u32 v18, v12, v6 +; GCN-NEXT: v_mul_lo_u32 v13, v12, v6 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v18 +; GCN-NEXT: v_add_i32_e32 v18, vcc, v10, v9 +; GCN-NEXT: v_subrev_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_mul_hi_u32 v10, v11, v8 +; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v18, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v9, v9, v0 +; GCN-NEXT: v_sub_i32_e32 v19, vcc, 0, v13 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v10, v8 +; GCN-NEXT: v_subrev_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_cndmask_b32_e64 v13, v13, v19, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v11, s[2:3] +; GCN-NEXT: v_mul_hi_u32 v10, v13, v12 +; GCN-NEXT: v_mul_lo_u32 v11, v9, v4 +; GCN-NEXT: v_mul_hi_u32 v8, v8, v1 +; GCN-NEXT: v_add_i32_e32 v13, vcc, v10, v12 +; GCN-NEXT: v_subrev_i32_e32 v10, vcc, v10, v12 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v0, v11 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v11 ; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v0, v4 -; GCN-NEXT: v_add_i32_e32 v0, vcc, -1, v9 -; GCN-NEXT: v_mul_lo_u32 v4, v10, v6 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v15 -; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v15 -; GCN-NEXT: v_add_i32_e32 v15, vcc, 1, v10 -; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v1, v5 -; GCN-NEXT: v_add_i32_e32 v1, vcc, -1, v10 -; GCN-NEXT: v_mul_lo_u32 v5, v11, v7 -; GCN-NEXT: v_cmp_ge_u32_e64 s[8:9], v2, v4 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, -1, v11 -; GCN-NEXT: v_cmp_ge_u32_e64 s[10:11], v3, v5 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v11 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v6 -; GCN-NEXT: v_cmp_ge_u32_e64 s[12:13], v3, v7 -; GCN-NEXT: s_and_b64 s[2:3], s[2:3], s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v2, v8, v13, s[2:3] -; GCN-NEXT: s_and_b64 s[2:3], s[6:7], s[4:5] -; GCN-NEXT: v_cndmask_b32_e64 v3, v9, v12, s[2:3] -; GCN-NEXT: s_and_b64 vcc, vcc, s[8:9] -; GCN-NEXT: v_cndmask_b32_e32 v6, v10, v15, vcc -; GCN-NEXT: s_and_b64 vcc, s[12:13], s[10:11] -; GCN-NEXT: v_cndmask_b32_e32 v5, v11, v5, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, v14, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[4:5] -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v6, s[8:9] -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v5, s[10:11] -; GCN-NEXT: v_xor_b32_e32 v2, v2, v16 -; GCN-NEXT: v_xor_b32_e32 v4, v0, v17 -; GCN-NEXT: v_xor_b32_e32 v5, v1, v18 -; GCN-NEXT: v_xor_b32_e32 v3, v3, v19 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v2, v16 -; GCN-NEXT: v_sub_i32_e32 v1, vcc, v4, v17 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, v5, v18 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v19 -; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 +; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v13, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v0, v8, v5 +; GCN-NEXT: v_mul_hi_u32 v4, v10, v2 +; GCN-NEXT: v_add_i32_e32 v12, vcc, -1, v9 +; GCN-NEXT: v_add_i32_e32 v10, vcc, -1, v8 +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v0 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v0, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v4, v6 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v9 +; GCN-NEXT: v_add_i32_e32 v0, vcc, 1, v8 +; GCN-NEXT: s_and_b64 vcc, s[2:3], s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc +; GCN-NEXT: v_sub_i32_e32 v9, vcc, v2, v5 +; GCN-NEXT: s_and_b64 vcc, s[6:7], s[4:5] +; GCN-NEXT: v_cvt_f32_u32_e32 v11, v7 +; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v0, v10, v0, s[4:5] +; GCN-NEXT: v_xor_b32_e32 v1, v1, v15 +; GCN-NEXT: v_xor_b32_e32 v8, v0, v16 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v15 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, v8, v16 +; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v11 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v9, v6 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v2, v5 +; GCN-NEXT: v_ashrrev_i32_e32 v10, 31, v3 +; GCN-NEXT: v_mul_f32_e32 v8, s14, v8 +; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v10, v3 +; GCN-NEXT: v_xor_b32_e32 v3, v3, v10 +; GCN-NEXT: v_add_i32_e32 v6, vcc, -1, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v8, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v8, v7 +; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v4 +; GCN-NEXT: v_sub_i32_e32 v11, vcc, 0, v5 +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v5, v5, v8 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v5, v8 +; GCN-NEXT: v_subrev_i32_e32 v5, vcc, v5, v8 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5] +; GCN-NEXT: v_mul_hi_u32 v5, v5, v3 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v4, v5, v7 +; GCN-NEXT: v_xor_b32_e32 v2, v2, v17 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, v2, v17 +; GCN-NEXT: v_xor_b32_e32 v6, v10, v14 +; GCN-NEXT: v_sub_i32_e32 v8, vcc, v3, v4 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v8, v7 +; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v3, v4 +; GCN-NEXT: v_add_i32_e32 v7, vcc, -1, v5 +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v5 +; GCN-NEXT: s_and_b64 vcc, s[0:1], s[2:3] +; GCN-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v7, v3, s[2:3] +; GCN-NEXT: v_xor_b32_e32 v3, v3, v6 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: sdiv_v4i32: @@ -1435,17 +1435,17 @@ define amdgpu_kernel void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ; GCN-LABEL: sdiv_v4i32_4: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s7 +; GCN-NEXT: s_mov_b32 s6, s2 +; GCN-NEXT: s_mov_b32 s7, s3 +; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v1 @@ -1463,7 +1463,7 @@ ; GCN-NEXT: v_ashrrev_i32_e32 v1, 2, v1 ; GCN-NEXT: v_ashrrev_i32_e32 v2, 2, v2 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 2, v3 -; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: sdiv_v4i32_4: @@ -1579,34 +1579,35 @@ define amdgpu_kernel void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { ; GCN-LABEL: v_sdiv_i8: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_mov_b32 s10, s2 +; GCN-NEXT: s_mov_b32 s11, s3 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 +; GCN-NEXT: s_mov_b32 s8, s6 +; GCN-NEXT: s_mov_b32 s9, s7 ; GCN-NEXT: buffer_load_sbyte v0, off, s[8:11], 0 ; GCN-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:1 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_cvt_f32_i32_e32 v3, v0 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_xor_b32_e32 v2, v0, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1 -; GCN-NEXT: v_or_b32_e32 v2, 1, v2 -; GCN-NEXT: v_mul_f32_e32 v3, v0, v3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v0, -v3, v1, v0 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, v1 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v1 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 +; GCN-NEXT: v_mul_f32_e32 v1, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mad_f32 v3, -v1, v2, v3 +; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 8 -; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: v_sdiv_i8: @@ -1723,45 +1724,43 @@ define amdgpu_kernel void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) { ; GCN-LABEL: v_sdiv_i23: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:2 -; GCN-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:6 -; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0 -; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_waitcnt vmcnt(3) -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s7 +; GCN-NEXT: s_mov_b32 s6, s2 +; GCN-NEXT: s_mov_b32 s7, s3 +; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; GCN-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:2 +; GCN-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:6 ; GCN-NEXT: s_waitcnt vmcnt(2) -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_or_b32_e32 v1, v2, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 +; GCN-NEXT: v_or_b32_e32 v2, v2, v3 +; GCN-NEXT: v_bfe_i32 v2, v2, 0, 23 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23 -; GCN-NEXT: v_bfe_i32 v1, v1, 0, 23 -; GCN-NEXT: v_xor_b32_e32 v2, v0, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v1 -; GCN-NEXT: v_or_b32_e32 v2, 1, v2 -; GCN-NEXT: v_mul_f32_e32 v3, v0, v3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v0, -v3, v1, v0 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v3 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v4 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v3, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23 -; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: v_sdiv_i23: @@ -1908,35 +1907,33 @@ define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) { ; GCN-LABEL: v_sdiv_i24: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:2 -; GCN-NEXT: buffer_load_sbyte v3, off, s[8:11], 0 offset:6 -; GCN-NEXT: buffer_load_ushort v0, off, s[8:11], 0 -; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 offset:4 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_waitcnt vmcnt(3) -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s7 +; GCN-NEXT: s_mov_b32 s6, s2 +; GCN-NEXT: s_mov_b32 s7, s3 +; GCN-NEXT: buffer_load_ushort v0, off, s[4:7], 0 +; GCN-NEXT: buffer_load_sbyte v1, off, s[4:7], 0 offset:2 +; GCN-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_load_sbyte v3, off, s[4:7], 0 offset:6 ; GCN-NEXT: s_waitcnt vmcnt(2) -; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 -; GCN-NEXT: s_waitcnt vmcnt(1) +; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GCN-NEXT: v_or_b32_e32 v0, v0, v1 ; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v3, 16, v3 ; GCN-NEXT: v_or_b32_e32 v2, v2, v3 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 ; GCN-NEXT: v_xor_b32_e32 v1, v1, v3 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 30, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v2, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v2 -; GCN-NEXT: v_mul_f32_e32 v3, v0, v3 +; GCN-NEXT: v_mul_f32_e32 v3, v0, v4 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_mad_f32 v0, -v3, v2, v0 ; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 @@ -1944,7 +1941,7 @@ ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 -; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; TONGA-LABEL: v_sdiv_i24: @@ -2097,52 +2094,52 @@ define amdgpu_kernel void @v_sdiv_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) { ; GCN-LABEL: v_sdiv_i25: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s10, s6 -; GCN-NEXT: s_mov_b32 s11, s7 +; GCN-NEXT: s_mov_b32 s2, s6 +; GCN-NEXT: s_mov_b32 s3, s7 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s8, s2 -; GCN-NEXT: s_mov_b32 s9, s3 -; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s0, s10 +; GCN-NEXT: s_mov_b32 s1, s11 +; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_bfe_i32 v2, v0, 0, 25 -; GCN-NEXT: v_bfe_i32 v3, v1, 0, 25 -; GCN-NEXT: v_bfe_i32 v0, v0, 24, 1 +; GCN-NEXT: v_bfe_i32 v2, v1, 0, 25 ; GCN-NEXT: v_bfe_i32 v1, v1, 24, 1 -; GCN-NEXT: v_xor_b32_e32 v4, v0, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v0, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v1, v3 -; GCN-NEXT: v_xor_b32_e32 v0, v2, v0 -; GCN-NEXT: v_xor_b32_e32 v1, v3, v1 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_hi_u32 v3, v2, v1 -; GCN-NEXT: v_mul_lo_u32 v5, v2, v1 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5 -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v3, v3, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v3, v2 -; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v5, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v2, v2, v0 -; GCN-NEXT: v_mul_lo_u32 v3, v2, v1 -; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, -1, v2 -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v3, v0 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 -; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v7, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v1, v2 +; GCN-NEXT: v_xor_b32_e32 v2, v2, v1 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v2 +; GCN-NEXT: v_bfe_i32 v4, v0, 0, 25 +; GCN-NEXT: v_bfe_i32 v0, v0, 24, 1 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v0, v4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v3 +; GCN-NEXT: v_xor_b32_e32 v4, v4, v0 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v1 +; GCN-NEXT: v_mul_f32_e32 v3, 0x4f800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_lo_u32 v5, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v2 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v5, v5, v3 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v5, v3 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1] +; GCN-NEXT: v_mul_hi_u32 v3, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v1, v3, v2 +; GCN-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; GCN-NEXT: v_add_i32_e32 v6, vcc, -1, v3 +; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v1, v4 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v7, v2 ; GCN-NEXT: s_and_b64 s[0:1], s[0:1], vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v5, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GCN-NEXT: v_xor_b32_e32 v0, v0, v4 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc +; GCN-NEXT: v_xor_b32_e32 v1, v1, v0 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm @@ -2341,16 +2338,18 @@ define amdgpu_kernel void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) { ; GCN-LABEL: scalarize_mulhs_4xi32: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[4:7], 0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_mov_b32 s0, 0x1389c755 -; GCN-NEXT: s_mov_b32 s4, s2 -; GCN-NEXT: s_mov_b32 s5, s3 +; GCN-NEXT: s_mov_b32 s4, s6 +; GCN-NEXT: s_mov_b32 s5, s7 +; GCN-NEXT: s_mov_b32 s6, s2 +; GCN-NEXT: s_mov_b32 s7, s3 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_mul_hi_i32 v0, v0, s0 ; GCN-NEXT: v_mul_hi_i32 v1, v1, s0 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -1,252 +1,252 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i32 s0, s3, 31 +; GCN-NEXT: s_ashr_i32 s12, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s12 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: s_addc_u32 s3, s3, s12 +; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: s_sub_u32 s4, 0, s2 +; GCN-NEXT: s_subb_u32 s5, 0, s3 +; GCN-NEXT: s_ashr_i32 s14, s11, 31 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: s_mov_b32 s4, s8 -; GCN-NEXT: s_mov_b32 s5, s9 -; GCN-NEXT: s_mov_b32 s1, s0 -; GCN-NEXT: s_add_u32 s2, s2, s0 -; GCN-NEXT: s_addc_u32 s3, s3, s0 -; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[0:1] -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s14, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s15, 0, s3 -; GCN-NEXT: s_ashr_i32 s8, s11, 31 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: s_add_u32 s10, s10, s8 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: s_addc_u32 s11, s11, s8 -; GCN-NEXT: s_xor_b64 s[12:13], s[8:9], s[0:1] -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 -; GCN-NEXT: s_xor_b64 s[8:9], s[10:11], s[8:9] -; GCN-NEXT: v_mov_b32_e32 v5, s13 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mov_b32_e32 v6, s9 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: s_mov_b32 s15, s14 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v7, s14, v3 -; GCN-NEXT: v_mul_lo_u32 v8, s15, v2 -; GCN-NEXT: v_mul_hi_u32 v9, s14, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s14, v2 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v10 -; GCN-NEXT: v_mul_lo_u32 v10, v3, v10 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v12, v2, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v3, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v3, v7 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v0, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v9, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v7 -; GCN-NEXT: v_addc_u32_e64 v7, vcc, v3, v8, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v9, s14, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s15, v2 -; GCN-NEXT: v_mul_lo_u32 v11, s14, v2 -; GCN-NEXT: v_mul_lo_u32 v12, s14, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v7, v11 -; GCN-NEXT: v_mul_lo_u32 v14, v7, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v11 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v7, v9 -; GCN-NEXT: v_mul_hi_u32 v12, v2, v9 -; GCN-NEXT: v_mul_lo_u32 v15, v2, v9 -; GCN-NEXT: v_mul_lo_u32 v7, v7, v9 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v15 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v1, v12, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v14, v9 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v13, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v8 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v10, vcc -; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v8, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v9, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v3 -; GCN-NEXT: v_mul_hi_u32 v11, s9, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s9, v3 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v8, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v11, v0, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v2 -; GCN-NEXT: v_mul_lo_u32 v7, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s2, v0 -; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v2 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v2 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v8 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, s9, v1 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, s8, v7 -; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v7 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v6, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v7 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v5, s4, v3 +; GCN-NEXT: v_mul_hi_u32 v6, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v3, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[0:1] +; GCN-NEXT: s_add_u32 s0, s10, s14 +; GCN-NEXT: s_addc_u32 s1, s11, s14 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v6, s11, v2 +; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 +; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] +; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v6, s11 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v6, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v12, v10, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] -; GCN-NEXT: v_xor_b32_e32 v2, s13, v0 -; GCN-NEXT: v_xor_b32_e32 v0, s12, v1 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v5, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s0, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s1, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd +; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31 -; GCN-IR-NEXT: s_ashr_i32 s8, s13, 31 ; GCN-IR-NEXT: s_mov_b32 s3, s2 +; GCN-IR-NEXT: s_ashr_i32 s8, s1, 31 +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7] +; GCN-IR-NEXT: s_sub_u32 s10, s6, s2 ; GCN-IR-NEXT: s_mov_b32 s9, s8 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[6:7] -; GCN-IR-NEXT: s_sub_u32 s10, s0, s2 -; GCN-IR-NEXT: s_subb_u32 s11, s1, s2 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[12:13] -; GCN-IR-NEXT: s_flbit_i32_b32 s14, s10 +; GCN-IR-NEXT: s_subb_u32 s11, s7, s2 +; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[0:1] ; GCN-IR-NEXT: s_sub_u32 s6, s0, s8 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s0, s11 ; GCN-IR-NEXT: s_subb_u32 s7, s1, s8 -; GCN-IR-NEXT: s_flbit_i32_b32 s15, s6 -; GCN-IR-NEXT: s_add_i32 s14, s14, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 -; GCN-IR-NEXT: s_add_i32 s15, s15, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s16, s7 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 -; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13] -; GCN-IR-NEXT: v_mov_b32_e32 v1, s16 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s15 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[12:13], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[12:13], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] +; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[0:1] +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s10 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s11 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB0_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[12:13] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[12:13] ; GCN-IR-NEXT: s_branch BB0_7 ; GCN-IR-NEXT: BB0_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[10:11], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[10:11], v4 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[10:11], v4 ; GCN-IR-NEXT: s_add_u32 s10, s6, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s11, s7, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s11 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s10, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s6, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s7, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB0_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[2:3] ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm @@ -260,218 +260,218 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3 -; GCN-NEXT: v_mov_b32_e32 v5, 0 -; GCN-NEXT: v_mov_b32_e32 v6, 0 -; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; GCN-NEXT: v_xor_b32_e32 v8, v7, v4 -; GCN-NEXT: v_xor_b32_e32 v3, v3, v4 ; GCN-NEXT: v_xor_b32_e32 v2, v2, v4 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v7 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 -; GCN-NEXT: v_cvt_f32_u32_e32 v7, v3 -; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v2 -; GCN-NEXT: v_subb_u32_e32 v10, vcc, 0, v3, vcc -; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v7 -; GCN-NEXT: v_rcp_f32_e32 v4, v4 -; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 -; GCN-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4 -; GCN-NEXT: v_trunc_f32_e32 v7, v7 -; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7 -; GCN-NEXT: v_cvt_u32_f32_e32 v7, v7 -; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GCN-NEXT: v_mul_lo_u32 v11, v9, v7 -; GCN-NEXT: v_mul_lo_u32 v12, v10, v4 -; GCN-NEXT: v_mul_hi_u32 v13, v9, v4 -; GCN-NEXT: v_mul_lo_u32 v14, v9, v4 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v13, v11 -; GCN-NEXT: v_mul_hi_u32 v13, v4, v14 -; GCN-NEXT: v_mul_hi_u32 v15, v7, v14 -; GCN-NEXT: v_mul_lo_u32 v14, v7, v14 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v11 -; GCN-NEXT: v_mul_lo_u32 v16, v4, v11 -; GCN-NEXT: v_mul_hi_u32 v17, v7, v11 -; GCN-NEXT: v_mul_lo_u32 v11, v7, v11 -; GCN-NEXT: v_add_i32_e32 v13, vcc, v13, v16 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v12, vcc -; GCN-NEXT: v_add_i32_e32 v13, vcc, v14, v13 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v12, v15, vcc -; GCN-NEXT: v_addc_u32_e32 v13, vcc, v17, v5, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v13, vcc -; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 -; GCN-NEXT: v_addc_u32_e64 v11, vcc, v7, v12, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v13, v9, v4 -; GCN-NEXT: v_mul_lo_u32 v10, v10, v4 -; GCN-NEXT: v_mul_lo_u32 v14, v9, v4 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v12 -; GCN-NEXT: v_mul_lo_u32 v9, v9, v11 -; GCN-NEXT: v_mul_hi_u32 v12, v11, v14 -; GCN-NEXT: v_mul_lo_u32 v15, v11, v14 -; GCN-NEXT: v_mul_hi_u32 v14, v4, v14 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9 +; GCN-NEXT: v_xor_b32_e32 v3, v3, v4 +; GCN-NEXT: v_cvt_f32_u32_e32 v5, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v6, v3 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v2 +; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v3, vcc +; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 +; GCN-NEXT: v_rcp_f32_e32 v5, v5 +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 +; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 +; GCN-NEXT: v_trunc_f32_e32 v6, v6 +; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v7, v6 +; GCN-NEXT: v_mul_lo_u32 v11, v8, v5 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v11, v9 -; GCN-NEXT: v_mul_hi_u32 v13, v4, v9 -; GCN-NEXT: v_mul_lo_u32 v16, v4, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v11, v9 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v16 -; GCN-NEXT: v_addc_u32_e32 v13, vcc, v6, v13, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v15, v11 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v13, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v5, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v6, v10, vcc -; GCN-NEXT: v_addc_u32_e64 v7, vcc, v7, v10, s[4:5] -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 -; GCN-NEXT: v_mul_lo_u32 v12, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v1, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v1, v7 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v6, v11, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v5, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v7, v3, v4 -; GCN-NEXT: v_mul_lo_u32 v9, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 -; GCN-NEXT: v_add_i32_e32 v11, vcc, 2, v4 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v13, vcc, 1, v4 -; GCN-NEXT: v_addc_u32_e32 v14, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v7, v5 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11 +; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v11, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v13, v5, v10 +; GCN-NEXT: v_mul_hi_u32 v16, v6, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v9 +; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 +; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 +; GCN-NEXT: v_mul_hi_u32 v10, v6, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v11, vcc +; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v11, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v16, v14, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v11, vcc +; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v11, v7, v9 +; GCN-NEXT: v_mul_hi_u32 v12, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v8, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v7, v7, v5 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v8 +; GCN-NEXT: v_mul_lo_u32 v13, v5, v8 +; GCN-NEXT: v_mul_hi_u32 v16, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v17, v5, v8 +; GCN-NEXT: v_mul_hi_u32 v12, v9, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v9, v7 +; GCN-NEXT: v_add_i32_e32 v13, vcc, v16, v13 +; GCN-NEXT: v_mul_hi_u32 v11, v9, v8 +; GCN-NEXT: v_addc_u32_e32 v16, vcc, v15, v17, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v9, v8 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v13 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v16, v12, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v14, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v15, v9, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v6 +; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5] +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc +; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v7 +; GCN-NEXT: v_mul_lo_u32 v8, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v6 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc +; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v15, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v1, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v6 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v14, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v5 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_mul_lo_u32 v9, v2, v5 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GCN-NEXT: v_sub_i32_e32 v10, vcc, v1, v8 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v9 -; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v3, vcc -; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v2 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc +; GCN-NEXT: v_subb_u32_e64 v9, s[4:5], v10, v3, vcc +; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v0, v2 +; GCN-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v3 +; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v10, v2 +; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v9, v3 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v8, vcc +; GCN-NEXT: v_cndmask_b32_e64 v9, v11, v10, s[4:5] +; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 2, v5 +; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v6, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GCN-NEXT: v_add_i32_e64 v12, s[4:5], 1, v5 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e64 v13, s[4:5], 0, v6, s[4:5] ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v9, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v3 -; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v2, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v14, v12, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v5, v1, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v13, v11, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] -; GCN-NEXT: v_xor_b32_e32 v2, v0, v8 -; GCN-NEXT: v_xor_b32_e32 v0, v1, v8 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v8, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 +; GCN-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v9, v13, v11, s[4:5] +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v12, v10, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v9, vcc +; GCN-NEXT: v_xor_b32_e32 v2, v7, v4 +; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc +; GCN-NEXT: v_xor_b32_e32 v3, v0, v2 +; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_sdiv: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1 +; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v0 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 +; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, v0, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v4, v1 -; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v0 -; GCN-IR-NEXT: v_xor_b32_e32 v3, v5, v3 -; GCN-IR-NEXT: v_xor_b32_e32 v2, v5, v2 -; GCN-IR-NEXT: v_sub_i32_e32 v13, vcc, v0, v4 -; GCN-IR-NEXT: v_subb_u32_e32 v14, vcc, v1, v4, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v2, v5 -; GCN-IR-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc +; GCN-IR-NEXT: v_subb_u32_e32 v10, vcc, v1, v4, vcc +; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v2 +; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v5 +; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v3 +; GCN-IR-NEXT: v_subb_u32_e32 v3, vcc, v0, v5, vcc ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[13:14] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[9:10] ; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v2 -; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v3 -; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v13 -; GCN-IR-NEXT: v_ffbh_u32_e32 v8, v14 ; GCN-IR-NEXT: s_or_b64 s[6:7], vcc, s[4:5] ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 32, v0 -; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 32, v7 +; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v3 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GCN-IR-NEXT: v_cndmask_b32_e32 v16, v1, v0, vcc -; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v14 -; GCN-IR-NEXT: v_cndmask_b32_e32 v15, v8, v7, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v16, v15 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[8:9] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[8:9] +; GCN-IR-NEXT: v_cndmask_b32_e32 v13, v7, v0, vcc +; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v9 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 32, v0 +; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v10 +; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10 +; GCN-IR-NEXT: v_cndmask_b32_e32 v14, v7, v0, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v11, vcc, v13, v14 +; GCN-IR-NEXT: v_subb_u32_e64 v12, s[4:5], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[11:12] +; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[11:12] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc -; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v14, 0, s[6:7] ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1 -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v18, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v17, v12 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v13, 0, s[6:7] +; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v10, 0, s[6:7] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v17, v18 +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v9, 0, s[6:7] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v18, vcc, 1, v8 -; GCN-IR-NEXT: v_addc_u32_e32 v19, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v8 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[18:19], v[8:9] -; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[13:14], v0 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 +; GCN-IR-NEXT: v_add_i32_e32 v15, vcc, 1, v11 +; GCN-IR-NEXT: v_addc_u32_e32 v16, vcc, 0, v12, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 63, v11 +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[15:16], v[11:12] ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[9:10], v0 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[18:19], v[13:14], v18 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, -1, v2 +; GCN-IR-NEXT: v_lshr_b64 v[15:16], v[9:10], v15 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v3, vcc -; GCN-IR-NEXT: v_not_b32_e32 v10, v16 -; GCN-IR-NEXT: v_not_b32_e32 v11, v12 -; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, v10, v15 -; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, v11, v17, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 +; GCN-IR-NEXT: v_not_b32_e32 v10, v13 +; GCN-IR-NEXT: v_not_b32_e32 v11, v18 +; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, v10, v14 +; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, v11, v17, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v17, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v18, 0 ; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[18:19], 1 +; GCN-IR-NEXT: v_lshl_b64 v[15:16], v[15:16], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v8 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_or_b32_e32 v10, v15, v10 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 -; GCN-IR-NEXT: v_or_b32_e32 v8, v15, v8 -; GCN-IR-NEXT: v_or_b32_e32 v7, v14, v7 -; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v12 -; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v13, vcc -; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v10 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[12:13] -; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v0, v16 -; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v9, v17, s[4:5] +; GCN-IR-NEXT: v_sub_i32_e32 v11, vcc, v0, v10 +; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v9, v16, vcc +; GCN-IR-NEXT: v_or_b32_e32 v7, v17, v7 +; GCN-IR-NEXT: v_add_i32_e32 v17, vcc, 1, v13 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v15, 31, v11 +; GCN-IR-NEXT: v_or_b32_e32 v8, v18, v8 +; GCN-IR-NEXT: v_addc_u32_e32 v18, vcc, 0, v14, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[17:18], v[13:14] +; GCN-IR-NEXT: v_mov_b32_e32 v13, v17 +; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 +; GCN-IR-NEXT: v_and_b32_e32 v11, 1, v15 +; GCN-IR-NEXT: v_and_b32_e32 v19, v15, v3 +; GCN-IR-NEXT: v_and_b32_e32 v15, v15, v2 +; GCN-IR-NEXT: v_sub_i32_e64 v15, s[4:5], v10, v15 +; GCN-IR-NEXT: v_mov_b32_e32 v14, v18 +; GCN-IR-NEXT: v_mov_b32_e32 v18, v12 +; GCN-IR-NEXT: v_subb_u32_e64 v16, s[4:5], v16, v19, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v10 -; GCN-IR-NEXT: v_and_b32_e32 v10, 1, v12 -; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3 -; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2 -; GCN-IR-NEXT: v_sub_i32_e32 v18, vcc, v16, v12 -; GCN-IR-NEXT: v_subb_u32_e32 v19, vcc, v17, v13, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v12, v14 -; GCN-IR-NEXT: v_mov_b32_e32 v13, v15 -; GCN-IR-NEXT: v_mov_b32_e32 v15, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v14, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v17, v11 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB1_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -479,14 +479,14 @@ ; GCN-IR-NEXT: BB1_5: ; %Flow3 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[7:8], 1 -; GCN-IR-NEXT: v_or_b32_e32 v7, v11, v3 -; GCN-IR-NEXT: v_or_b32_e32 v0, v10, v2 +; GCN-IR-NEXT: v_or_b32_e32 v7, v12, v3 +; GCN-IR-NEXT: v_or_b32_e32 v0, v11, v2 ; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v6 ; GCN-IR-NEXT: v_xor_b32_e32 v2, v5, v4 -; GCN-IR-NEXT: v_xor_b32_e32 v3, v7, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v6 +; GCN-IR-NEXT: v_xor_b32_e32 v3, v7, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -498,26 +498,26 @@ ; GCN-LABEL: s_test_sdiv24_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 40 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_xor_b32 s4, s4, s8 +; GCN-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-NEXT: s_or_b32 s4, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_mov_b32_e32 v3, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -528,26 +528,26 @@ ; GCN-IR-LABEL: s_test_sdiv24_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 40 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 40 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 +; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -565,17 +565,17 @@ ; GCN-LABEL: v_test_sdiv24_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_cvt_i32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] @@ -583,17 +583,17 @@ ; GCN-IR-LABEL: v_test_sdiv24_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v3 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -607,24 +607,25 @@ ; GCN-LABEL: s_test_sdiv32_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_load_dword s6, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s7 ; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 ; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_xor_b32 s4, s7, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s7 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s8 +; GCN-NEXT: s_xor_b32 s4, s7, s6 ; GCN-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-NEXT: s_or_b32 s4, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -634,24 +635,25 @@ ; GCN-IR-LABEL: s_test_sdiv32_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s7 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 ; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_xor_b32 s4, s7, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s7 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s8 +; GCN-IR-NEXT: s_xor_b32 s4, s7, s6 ; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -668,26 +670,26 @@ ; GCN-LABEL: s_test_sdiv31_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 33 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_xor_b32 s4, s4, s8 +; GCN-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-NEXT: s_or_b32 s4, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_mov_b32_e32 v3, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31 @@ -698,26 +700,26 @@ ; GCN-IR-LABEL: s_test_sdiv31_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 33 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 +; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31 @@ -735,26 +737,26 @@ ; GCN-LABEL: s_test_sdiv23_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 41 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 41 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_xor_b32 s4, s4, s8 +; GCN-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-NEXT: s_or_b32 s4, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_mov_b32_e32 v3, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23 @@ -765,26 +767,26 @@ ; GCN-IR-LABEL: s_test_sdiv23_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 41 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 41 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 41 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 +; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23 @@ -802,26 +804,26 @@ ; GCN-LABEL: s_test_sdiv25_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 39 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_xor_b32 s4, s4, s8 +; GCN-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-NEXT: s_or_b32 s4, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_mov_b32_e32 v3, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 @@ -832,26 +834,26 @@ ; GCN-IR-LABEL: s_test_sdiv25_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 ; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 39 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s4, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 +; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 ; GCN-IR-NEXT: s_or_b32 s4, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 @@ -870,45 +872,45 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd -; GCN-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x11 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i64 s[0:1], s[10:11], 40 -; GCN-NEXT: s_ashr_i64 s[2:3], s[8:9], 40 -; GCN-NEXT: s_ashr_i64 s[8:9], s[14:15], 40 -; GCN-NEXT: s_ashr_i64 s[10:11], s[12:13], 40 -; GCN-NEXT: s_xor_b32 s1, s2, s10 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s2 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s10 -; GCN-NEXT: s_xor_b32 s2, s0, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v2, s0 -; GCN-NEXT: v_cvt_f32_i32_e32 v3, s8 -; GCN-NEXT: s_ashr_i32 s0, s1, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1 -; GCN-NEXT: s_ashr_i32 s1, s2, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-NEXT: s_ashr_i64 s[8:9], s[8:9], 40 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s8 +; GCN-NEXT: s_xor_b32 s0, s8, s0 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 40 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-NEXT: s_ashr_i64 s[10:11], s[10:11], 40 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v2, s2 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, s10 +; GCN-NEXT: s_xor_b32 s0, s10, s2 +; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-NEXT: s_or_b32 s0, s0, 1 -; GCN-NEXT: v_mul_f32_e32 v4, v0, v4 -; GCN-NEXT: s_or_b32 s1, s1, 1 -; GCN-NEXT: v_mul_f32_e32 v5, v2, v5 +; GCN-NEXT: v_mov_b32_e32 v5, s0 +; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 ; GCN-NEXT: v_trunc_f32_e32 v4, v4 -; GCN-NEXT: v_mov_b32_e32 v6, s0 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mov_b32_e32 v7, s1 -; GCN-NEXT: v_mad_f32 v0, -v4, v1, v0 +; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 -; GCN-NEXT: v_mad_f32 v2, -v5, v3, v2 -; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v3| -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v5 -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 -; GCN-NEXT: v_bfe_i32 v2, v1, 0, 24 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| +; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_bfe_i32 v2, v2, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-NEXT: s_endpgm @@ -917,45 +919,45 @@ ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd -; GCN-IR-NEXT: s_load_dwordx4 s[12:15], s[0:1], 0x11 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[10:11], 40 -; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[8:9], 40 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[14:15], 40 -; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[12:13], 40 -; GCN-IR-NEXT: s_xor_b32 s1, s2, s10 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s2 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s10 -; GCN-IR-NEXT: s_xor_b32 s2, s0, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, s8 -; GCN-IR-NEXT: s_ashr_i32 s0, s1, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v1 -; GCN-IR-NEXT: s_ashr_i32 s1, s2, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v5, v3 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 40 +; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s8 +; GCN-IR-NEXT: s_xor_b32 s0, s8, s0 +; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_or_b32 s0, s0, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 40 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc +; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[10:11], 40 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, s2 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, s10 +; GCN-IR-NEXT: s_xor_b32 s0, s10, s2 +; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-IR-NEXT: s_or_b32 s0, s0, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v4, v0, v4 -; GCN-IR-NEXT: s_or_b32 s1, s1, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v5, v2, v5 +; GCN-IR-NEXT: v_mov_b32_e32 v5, s0 +; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-IR-NEXT: v_mul_f32_e32 v4, v3, v4 ; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4 -; GCN-IR-NEXT: v_mov_b32_e32 v6, s0 -; GCN-IR-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v7, s1 -; GCN-IR-NEXT: v_mad_f32 v0, -v4, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v3, -v4, v2, v3 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 -; GCN-IR-NEXT: v_mad_f32 v2, -v5, v3, v2 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v5, v5 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v3| -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v5 -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 -; GCN-IR-NEXT: v_bfe_i32 v2, v1, 0, 24 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v2| +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-IR-NEXT: v_bfe_i32 v2, v2, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm @@ -973,29 +975,29 @@ ; GCN-NEXT: s_load_dword s2, s[0:1], 0xb ; GCN-NEXT: s_load_dword s3, s[0:1], 0xc ; GCN-NEXT: s_load_dword s8, s[0:1], 0xd -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_sext_i32_i16 s0, s3 -; GCN-NEXT: s_sext_i32_i16 s1, s9 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: s_sext_i32_i16 s1, s3 ; GCN-NEXT: v_mov_b32_e32 v0, s8 -; GCN-NEXT: v_mov_b32_e32 v1, s2 -; GCN-NEXT: v_alignbit_b32 v0, s1, v0, 24 -; GCN-NEXT: v_alignbit_b32 v1, s0, v1, 24 -; GCN-NEXT: v_xor_b32_e32 v2, v1, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-NEXT: v_or_b32_e32 v2, 1, v2 -; GCN-NEXT: v_mul_f32_e32 v3, v1, v3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v1, -v3, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: s_sext_i32_i16 s0, s0 +; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 24 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 24 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-NEXT: v_xor_b32_e32 v0, v2, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_f32_e32 v2, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v3, -v2, v1, v3 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 @@ -1004,120 +1006,122 @@ ; ; GCN-IR-LABEL: s_test_sdiv24_48: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xb ; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc -; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xd +; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 -; GCN-IR-NEXT: s_sext_i32_i16 s9, s6 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 24 -; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 -; GCN-IR-NEXT: s_ashr_i32 s6, s9, 31 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 24 +; GCN-IR-NEXT: s_sext_i32_i16 s7, s2 +; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31 +; GCN-IR-NEXT: s_sext_i32_i16 s5, s3 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[4:5], 24 +; GCN-IR-NEXT: s_ashr_i32 s4, s5, 31 +; GCN-IR-NEXT: s_mov_b32 s5, s4 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 24 +; GCN-IR-NEXT: s_xor_b64 s[8:9], s[4:5], s[8:9] +; GCN-IR-NEXT: s_sub_u32 s10, s8, s4 ; GCN-IR-NEXT: s_mov_b32 s3, s2 -; GCN-IR-NEXT: s_mov_b32 s7, s6 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[0:1] -; GCN-IR-NEXT: s_sub_u32 s10, s0, s2 -; GCN-IR-NEXT: s_subb_u32 s11, s1, s2 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[6:7], s[8:9] -; GCN-IR-NEXT: s_flbit_i32_b32 s14, s10 -; GCN-IR-NEXT: s_sub_u32 s8, s0, s6 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[10:11], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s0, s11 -; GCN-IR-NEXT: s_subb_u32 s9, s1, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s15, s8 -; GCN-IR-NEXT: s_add_i32 s14, s14, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0 -; GCN-IR-NEXT: s_add_i32 s15, s15, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s16, s9 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 +; GCN-IR-NEXT: s_subb_u32 s11, s9, s4 +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[2:3], s[6:7] +; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 +; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s10 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s11 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[12:13] -; GCN-IR-NEXT: v_mov_b32_e32 v1, s16 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s15 -; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[12:13], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[12:13], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13] +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[10:11], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[14:15] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[12:13], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_mov_b64 vcc, vcc ; GCN-IR-NEXT: s_cbranch_vccz BB9_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[12:13] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s10 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[12:13] ; GCN-IR-NEXT: s_branch BB9_7 ; GCN-IR-NEXT: BB9_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[10:11], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: BB9_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[10:11], v4 -; GCN-IR-NEXT: s_add_u32 s10, s8, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 -; GCN-IR-NEXT: s_addc_u32 s11, s9, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[10:11], v4 +; GCN-IR-NEXT: s_add_u32 s10, s6, -1 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 +; GCN-IR-NEXT: s_addc_u32 s11, s7, -1 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB9_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s11 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s10, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s8, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s9, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: BB9_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB9_7: ; %udiv-end -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[6:7], s[2:3] -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_xor_b64 s[0:1], s[2:3], s[4:5] ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s1, v1 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 -; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s10, -1 +; GCN-IR-NEXT: buffer_store_short v1, off, s[8:11], 0 offset:4 +; GCN-IR-NEXT: buffer_store_dword v0, off, s[8:11], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i48 %x, 24 %2 = ashr i48 %y, 24 @@ -1129,127 +1133,125 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_sdiv_k_num_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i32 s2, s11, 31 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: s_mov_b32 s4, s8 -; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: s_ashr_i32 s2, s7, 31 +; GCN-NEXT: s_add_u32 s0, s6, s2 +; GCN-NEXT: s_addc_u32 s1, s7, s2 ; GCN-NEXT: s_mov_b32 s3, s2 -; GCN-NEXT: s_add_u32 s0, s10, s2 -; GCN-NEXT: v_mov_b32_e32 v2, s2 -; GCN-NEXT: s_addc_u32 s1, s11, s2 ; GCN-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3] -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s8 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, s9 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GCN-NEXT: s_sub_u32 s3, 0, s8 -; GCN-NEXT: v_mov_b32_e32 v5, s9 -; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; GCN-NEXT: s_subb_u32 s10, 0, s9 -; GCN-NEXT: v_rcp_f32_e32 v3, v3 -; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 -; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 -; GCN-NEXT: v_trunc_f32_e32 v4, v4 -; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 -; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_hi_u32 v5, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s3, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s10, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s3, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] ; GCN-NEXT: v_mul_lo_u32 v6, s3, v4 -; GCN-NEXT: v_mul_lo_u32 v7, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v8, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s3, v3 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v3, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v4, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v4, v9 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v4, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc +; GCN-NEXT: v_mul_hi_u32 v7, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s10, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e64 v3, s[0:1], v3, v6 -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v4, v7, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v8, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s10, v3 -; GCN-NEXT: v_mul_lo_u32 v10, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v11, s3, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v10 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v14, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc -; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v7, s[0:1] -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_hi_u32 v5, 24, v0 +; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v6, 24, v3 +; GCN-NEXT: v_mul_hi_u32 v0, 0, v0 ; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 -; GCN-NEXT: v_mul_hi_u32 v7, 24, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v4, 24 -; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v3, s8, v1 -; GCN-NEXT: v_mul_lo_u32 v4, s9, v1 -; GCN-NEXT: v_mul_lo_u32 v6, s8, v1 -; GCN-NEXT: v_mul_lo_u32 v7, s8, v0 -; GCN-NEXT: v_add_i32_e32 v8, vcc, 2, v1 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v1 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 24, v6 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s8, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s8, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s9, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s9 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s8, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 ; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6 -; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v6 +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v3 +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] +; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, 0, v2, vcc +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 +; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v4, vcc, 0, v4, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v4 -; GCN-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v6, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v4 -; GCN-NEXT: v_cndmask_b32_e32 v4, v12, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GCN-NEXT: v_cndmask_b32_e32 v4, v11, v9, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v4, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GCN-NEXT: v_xor_b32_e32 v3, s2, v0 -; GCN-NEXT: v_xor_b32_e32 v0, s2, v1 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s2, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s2, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s2 ; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; @@ -1268,78 +1270,78 @@ ; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc5, v0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0 -; GCN-IR-NEXT: v_addc_u32_e64 v2, s[6:7], 0, -1, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[6:7], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7] +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 +; GCN-IR-NEXT: v_addc_u32_e64 v1, s[0:1], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] ; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB10_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11] ; GCN-IR-NEXT: s_branch BB10_7 ; GCN-IR-NEXT: BB10_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[1:2] -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 63, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v1 ; GCN-IR-NEXT: s_cbranch_vccz BB10_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB10_6 ; GCN-IR-NEXT: BB10_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v4 ; GCN-IR-NEXT: s_add_u32 s7, s8, -1 -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s10, s9, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB10_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s10 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s7, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s10 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s7, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s8, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s9, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB10_5 ; GCN-IR-NEXT: BB10_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB10_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm @@ -1353,114 +1355,114 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-NEXT: v_mov_b32_e32 v3, 0 -; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc -; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v6, v1 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v0 -; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v1, vcc -; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 -; GCN-NEXT: v_rcp_f32_e32 v5, v5 -; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 -; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 -; GCN-NEXT: v_trunc_f32_e32 v6, v6 -; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 -; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-NEXT: v_mul_lo_u32 v9, v7, v6 -; GCN-NEXT: v_mul_lo_u32 v10, v8, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v7, v5 -; GCN-NEXT: v_mul_lo_u32 v12, v7, v5 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v12 -; GCN-NEXT: v_mul_hi_u32 v13, v6, v12 -; GCN-NEXT: v_mul_lo_u32 v12, v6, v12 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v14, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v15, v6, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v6, v9 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v3, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v11, vcc -; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9 -; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v11, v7, v5 -; GCN-NEXT: v_mul_lo_u32 v8, v8, v5 -; GCN-NEXT: v_mul_lo_u32 v12, v7, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v7, v7, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v9, v12 -; GCN-NEXT: v_mul_lo_u32 v13, v9, v12 -; GCN-NEXT: v_mul_hi_u32 v12, v5, v12 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7 +; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0 +; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 +; GCN-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_mul_hi_u32 v7, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v3 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_mul_hi_u32 v8, v9, v7 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v14, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v9, v7 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v14 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v4, v11, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v3, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5] -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GCN-NEXT: v_mul_hi_u32 v7, 24, v5 -; GCN-NEXT: v_mul_hi_u32 v5, 0, v5 -; GCN-NEXT: v_mul_hi_u32 v8, 24, v6 -; GCN-NEXT: v_mul_lo_u32 v9, v6, 24 -; GCN-NEXT: v_mul_hi_u32 v6, 0, v6 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v3 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, 0, v7 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v5, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v3 -; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v4 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v4 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v3, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e64 v7, vcc, v4, v8, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v9, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v3 +; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v14, v3, v5 +; GCN-NEXT: v_mul_hi_u32 v15, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v7, v5 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v11 +; GCN-NEXT: v_mul_hi_u32 v9, v7, v6 +; GCN-NEXT: v_addc_u32_e32 v14, vcc, v13, v15, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v7, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, 24, v7 -; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc -; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v0 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5] +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc +; GCN-NEXT: v_mul_hi_u32 v6, 24, v3 +; GCN-NEXT: v_mul_lo_u32 v5, v4, 24 +; GCN-NEXT: v_mul_hi_u32 v7, 24, v4 +; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 0, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 24, v6 +; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v1, vcc +; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v0 +; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5] +; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v3 +; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v3 ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1 -; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v12, v10, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v1, v10, v8, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GCN-NEXT: v_xor_b32_e32 v3, v0, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 @@ -1471,26 +1473,26 @@ ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 -; GCN-IR-NEXT: s_movk_i32 s4, 0xffc5 -; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 +; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s4, v10 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] +; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s6, v10 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, 24, 0, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] @@ -1498,11 +1500,11 @@ ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v4 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 +; GCN-IR-NEXT: v_lshl_b64 v[4:5], 24, v4 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] @@ -1512,33 +1514,33 @@ ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 58, v10 -; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 +; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 ; GCN-IR-NEXT: BB11_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 -; GCN-IR-NEXT: v_or_b32_e32 v5, v15, v5 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v6, v12 +; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v7, v13, vcc ; GCN-IR-NEXT: v_or_b32_e32 v4, v14, v4 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8 +; GCN-IR-NEXT: v_and_b32_e32 v17, v14, v0 +; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14 +; GCN-IR-NEXT: v_and_b32_e32 v16, v14, v1 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v10 +; GCN-IR-NEXT: v_or_b32_e32 v5, v15, v5 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v11, vcc -; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11] -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v12 -; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v7, v13, s[4:5] -; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v8 -; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v10 -; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1 -; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v10 -; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v11, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v10, v14 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v17 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v15 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v9 +; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v14, v8 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB11_3 @@ -1551,8 +1553,8 @@ ; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v0 ; GCN-IR-NEXT: BB11_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -1565,115 +1567,115 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-NEXT: v_mov_b32_e32 v3, 0 -; GCN-NEXT: v_mov_b32_e32 v4, 0 -; GCN-NEXT: s_mov_b32 s6, 0x8000 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc -; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v6, v1 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v0 -; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v1, vcc -; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 -; GCN-NEXT: v_rcp_f32_e32 v5, v5 -; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 -; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 -; GCN-NEXT: v_trunc_f32_e32 v6, v6 -; GCN-NEXT: v_mac_f32_e32 v5, 0xcf800000, v6 -; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-NEXT: v_mul_lo_u32 v9, v7, v6 -; GCN-NEXT: v_mul_lo_u32 v10, v8, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v7, v5 -; GCN-NEXT: v_mul_lo_u32 v12, v7, v5 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v12 -; GCN-NEXT: v_mul_hi_u32 v13, v6, v12 -; GCN-NEXT: v_mul_lo_u32 v12, v6, v12 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v14, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v15, v6, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v6, v9 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v13, vcc -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v3, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v11, vcc -; GCN-NEXT: v_add_i32_e64 v5, s[4:5], v5, v9 -; GCN-NEXT: v_addc_u32_e64 v9, vcc, v6, v10, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v11, v7, v5 -; GCN-NEXT: v_mul_lo_u32 v8, v8, v5 -; GCN-NEXT: v_mul_lo_u32 v12, v7, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v7, v7, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v9, v12 -; GCN-NEXT: v_mul_lo_u32 v13, v9, v12 -; GCN-NEXT: v_mul_hi_u32 v12, v5, v12 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7 +; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v4, v1 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v0 +; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc +; GCN-NEXT: v_mov_b32_e32 v13, 0 +; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 +; GCN-NEXT: v_rcp_f32_e32 v3, v3 +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 +; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GCN-NEXT: v_mul_hi_u32 v7, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v3 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_mul_hi_u32 v8, v9, v7 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v14, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v9, v7 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v12, v14 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v4, v11, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v3, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v6, v8, s[4:5] -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GCN-NEXT: v_mul_hi_u32 v7, s6, v5 -; GCN-NEXT: v_mul_hi_u32 v5, 0, v5 -; GCN-NEXT: v_mul_hi_u32 v8, s6, v6 -; GCN-NEXT: v_lshlrev_b32_e32 v9, 15, v6 -; GCN-NEXT: v_mul_hi_u32 v6, 0, v6 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v3 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, 0, v7 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v5, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v3 -; GCN-NEXT: v_add_i32_e32 v9, vcc, 2, v4 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, 1, v4 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v3, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_add_i32_e64 v3, s[4:5], v3, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e64 v7, vcc, v4, v8, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v9, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v3 +; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v14, v3, v5 +; GCN-NEXT: v_mul_hi_u32 v15, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v7, v5 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v11 +; GCN-NEXT: v_mul_hi_u32 v9, v7, v6 +; GCN-NEXT: v_addc_u32_e32 v14, vcc, v13, v15, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v7, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v11 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v12, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v5 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, s6, v7 -; GCN-NEXT: v_subb_u32_e64 v6, s[4:5], v6, v1, vcc -; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v0 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5] +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: s_mov_b32 s4, 0x8000 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc +; GCN-NEXT: v_mul_hi_u32 v5, s4, v3 +; GCN-NEXT: v_mul_hi_u32 v6, s4, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v7, 15, v4 +; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v6, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 0, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, s4, v6 +; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v1, vcc +; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v0 +; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v1 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v0 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5] +; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v3 +; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v3 ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v6, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v1 -; GCN-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v7, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v13, v0, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v0, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v12, v10, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v11, v9, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v1, v10, v8, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GCN-NEXT: v_xor_b32_e32 v3, v0, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v1, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 @@ -1684,80 +1686,80 @@ ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-IR-NEXT: s_mov_b32 s11, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 -; GCN-IR-NEXT: s_movk_i32 s4, 0xffd0 -; GCN-IR-NEXT: s_mov_b32 s10, 0x8000 -; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v6, s10 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 +; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-IR-NEXT: v_cndmask_b32_e32 v11, v5, v4, vcc -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s4, v11 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc +; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s6, v10 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: s_mov_b32 s8, 0x8000 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc +; GCN-IR-NEXT: v_mov_b32_e32 v6, s8 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v6, 0, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] -; GCN-IR-NEXT: v_mov_b32_e32 v8, v7 +; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 +; GCN-IR-NEXT: s_mov_b32 s9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB12_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 63, v4 +; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4 +; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[4:5] +; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 +; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[8:9], v4 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[13:14], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[4:5], s[10:11], v6 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s4, 0x8000 +; GCN-IR-NEXT: v_lshr_b64 v[12:13], s[4:5], v6 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, -1, v1, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v11, vcc, 47, v11 -; GCN-IR-NEXT: v_subb_u32_e32 v12, vcc, 0, v7, vcc -; GCN-IR-NEXT: v_lshr_b64 v[15:16], s[4:5], v13 -; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 47, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 +; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, 0, v11, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 ; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[15:16], v[15:16], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v7, 31, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 +; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v5 +; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v8 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 -; GCN-IR-NEXT: v_or_b32_e32 v5, v14, v5 -; GCN-IR-NEXT: v_or_b32_e32 v4, v13, v4 -; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, 1, v11 -; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, 0, v12, vcc -; GCN-IR-NEXT: v_or_b32_e32 v7, v15, v7 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[13:14], v[11:12] -; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v6, v7 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v8, v16, s[4:5] +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v6, v12 +; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v7, v13, vcc +; GCN-IR-NEXT: v_or_b32_e32 v4, v14, v4 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v8 +; GCN-IR-NEXT: v_and_b32_e32 v17, v14, v0 +; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v14 +; GCN-IR-NEXT: v_and_b32_e32 v16, v14, v1 +; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v10 +; GCN-IR-NEXT: v_or_b32_e32 v5, v15, v5 +; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v11, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11] +; GCN-IR-NEXT: v_mov_b32_e32 v10, v14 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v17 +; GCN-IR-NEXT: v_mov_b32_e32 v11, v15 +; GCN-IR-NEXT: v_mov_b32_e32 v15, v9 +; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v11, 31, v9 -; GCN-IR-NEXT: v_and_b32_e32 v9, 1, v11 -; GCN-IR-NEXT: v_and_b32_e32 v12, v11, v1 -; GCN-IR-NEXT: v_and_b32_e32 v11, v11, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v15, vcc, v7, v11 -; GCN-IR-NEXT: v_subb_u32_e32 v16, vcc, v16, v12, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v11, v13 -; GCN-IR-NEXT: v_mov_b32_e32 v12, v14 -; GCN-IR-NEXT: v_mov_b32_e32 v14, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v13, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v14, v8 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1765,12 +1767,12 @@ ; GCN-IR-NEXT: BB12_5: ; %Flow3 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 -; GCN-IR-NEXT: v_or_b32_e32 v8, v10, v1 -; GCN-IR-NEXT: v_or_b32_e32 v6, v9, v0 +; GCN-IR-NEXT: v_or_b32_e32 v7, v9, v1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v0 ; GCN-IR-NEXT: BB12_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_xor_b32_e32 v1, v8, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v6, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v7, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -1793,87 +1795,87 @@ ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v2, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v0, v2 -; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, v1, v2, vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7] -; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v6 -; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v7 +; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v0, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v0, v7 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v2, v1 +; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_add_i32_e64 v0, s[4:5], 32, v0 -; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v1, v0, s[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 48, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v1, s[4:5], 0, 0, s[4:5] -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[0:1] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[0:1] +; GCN-IR-NEXT: v_ffbh_u32_e32 v1, v8 +; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v1, v0, s[4:5] +; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 48, v0 +; GCN-IR-NEXT: v_subb_u32_e64 v4, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[7:8] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[3:4] +; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v8, 0, s[4:5] ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v7, 0, s[4:5] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[4:5], -1 -; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v6, 0, s[4:5] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[6:7] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB13_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v0 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[6:7], v4 -; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v3 +; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v4, vcc +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[3:4] +; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 +; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[7:8], v3 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB13_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[6:7], v9 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v8 -; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 -; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc +; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9 +; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: BB13_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 -; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 -; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6 -; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc -; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v4 -; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], v[12:13], v[6:7] -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v10 -; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] -; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v11, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v6, 31, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 0x8000, v6 -; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v6 -; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v14, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v6, v12 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v13 -; GCN-IR-NEXT: v_mov_b32_e32 v9, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v8, v4 +; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4 +; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0 +; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 +; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0 +; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc +; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 +; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v7 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5 +; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 +; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v8, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8] +; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9 +; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 +; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 +; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB13_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: BB13_5: ; %Flow3 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] -; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 -; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v1 -; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v0 +; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4 +; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: BB13_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_xor_b32_e32 v1, v5, v3 -; GCN-IR-NEXT: v_xor_b32_e32 v0, v4, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v0, v5, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v3, v6, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %result = sdiv i64 %x, 32768 ret i64 %result @@ -1882,56 +1884,56 @@ define amdgpu_kernel void @s_test_sdiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_sdiv24_k_num_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-NEXT: s_or_b32 s0, s1, 1 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-NEXT: s_mov_b32 s7, 0x41c00000 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i32 s4, s6, 30 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-NEXT: v_mul_f32_e32 v1, s2, v1 -; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: s_or_b32 s4, s4, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mul_f32_e32 v1, s7, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v3, -v1, v0, s2 +; GCN-NEXT: v_mad_f32 v2, -v1, v0, s7 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv24_k_num_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-IR-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-IR-NEXT: s_or_b32 s0, s1, 1 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-IR-NEXT: s_mov_b32 s7, 0x41c00000 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_ashr_i32 s4, s6, 30 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v1, s2, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s0 +; GCN-IR-NEXT: s_or_b32 s4, s4, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_mul_f32_e32 v1, s7, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v3, -v1, v0, s2 +; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s7 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = ashr i64 %x, 40 %result = sdiv i64 24, %x.shr @@ -1942,54 +1944,54 @@ define amdgpu_kernel void @s_test_sdiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_sdiv24_k_den_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s8, 0x46b6fe00 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-NEXT: s_or_b32 s0, s1, 1 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_ashr_i32 s4, s6, 30 +; GCN-NEXT: s_or_b32 s4, s4, 1 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0 +; GCN-NEXT: v_mad_f32 v0, -v1, s8, v0 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 +; GCN-NEXT: v_mov_b32_e32 v2, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s8 ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv24_k_den_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-IR-NEXT: s_mov_b32 s8, 0x46b6fe00 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-IR-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-IR-NEXT: s_or_b32 s0, s1, 1 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_ashr_i32 s4, s6, 30 +; GCN-IR-NEXT: s_or_b32 s4, s4, 1 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s0 -; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0 +; GCN-IR-NEXT: v_mad_f32 v0, -v1, s8, v0 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s8 ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 +; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = ashr i64 %x, 40 %result = sdiv i64 %x.shr, 23423 @@ -2003,16 +2005,16 @@ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-NEXT: s_mov_b32 s4, 0x41c00000 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v3, -v2, v0, s4 +; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -2023,16 +2025,16 @@ ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-IR-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v3, -v2, v0, s4 +; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -2048,16 +2050,16 @@ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-NEXT: s_mov_b32 s4, 0x47000000 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v3, -v2, v0, s4 +; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -2068,16 +2070,16 @@ ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-IR-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v3, -v2, v0, s4 +; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -2103,15 +2105,15 @@ ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 -; GCN-IR-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v0 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v0, 1, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, s4, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v2, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -1,126 +1,126 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem: ; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd +; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GCN-NEXT: s_sub_u32 s2, 0, s12 +; GCN-NEXT: s_subb_u32 s3, 0, s13 ; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s5, s9 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s8, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mov_b32_e32 v5, s11 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s9, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v6, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v7, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s8, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v3, v9 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v11, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v6 -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v8, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v11, s8, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v10 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v14, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc -; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v7, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v6, s10, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s11, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s10, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v10, s11, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_sub_i32_e32 v1, vcc, s11, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2 -; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s13 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s12, v4 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v2 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0 -; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; @@ -129,103 +129,103 @@ ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s0, s2 -; GCN-IR-NEXT: s_add_i32 s11, s0, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s12, s3 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7 -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] -; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 -; GCN-IR-NEXT: s_add_i32 s8, s10, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s13 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 +; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 +; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], s[8:9] +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 +; GCN-IR-NEXT: s_add_i32 s10, s10, 32 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[8:9], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB0_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB0_7 ; GCN-IR-NEXT: BB0_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[6:7], v4 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: s_add_u32 s8, s2, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s3, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s9 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s8, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s9 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s8, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s2, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s3, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB0_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s10, -1 -; GCN-IR-NEXT: s_mov_b32 s8, s4 -; GCN-IR-NEXT: s_mov_b32 s9, s5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v4, s7 +; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc +; GCN-IR-NEXT: s_mov_b32 s10, -1 +; GCN-IR-NEXT: s_mov_b32 s8, s4 +; GCN-IR-NEXT: s_mov_b32 s9, s5 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-IR-NEXT: s_endpgm %result = urem i64 %x, %y @@ -238,214 +238,214 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v4, 31, v3 -; GCN-NEXT: v_mov_b32_e32 v5, 0 -; GCN-NEXT: v_mov_b32_e32 v6, 0 -; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v7 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc ; GCN-NEXT: v_xor_b32_e32 v3, v3, v4 ; GCN-NEXT: v_xor_b32_e32 v2, v2, v4 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v7 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 -; GCN-NEXT: v_cvt_f32_u32_e32 v8, v3 -; GCN-NEXT: v_sub_i32_e32 v9, vcc, 0, v2 -; GCN-NEXT: v_subb_u32_e32 v10, vcc, 0, v3, vcc -; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v8 +; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 +; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc +; GCN-NEXT: v_mov_b32_e32 v14, 0 +; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GCN-NEXT: v_rcp_f32_e32 v4, v4 +; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 -; GCN-NEXT: v_mul_f32_e32 v8, 0x2f800000, v4 -; GCN-NEXT: v_trunc_f32_e32 v8, v8 -; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v8 -; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8 +; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 +; GCN-NEXT: v_trunc_f32_e32 v5, v5 +; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GCN-NEXT: v_mul_lo_u32 v11, v9, v8 -; GCN-NEXT: v_mul_lo_u32 v12, v10, v4 -; GCN-NEXT: v_mul_hi_u32 v13, v9, v4 -; GCN-NEXT: v_mul_lo_u32 v14, v9, v4 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v13, v11 -; GCN-NEXT: v_mul_hi_u32 v13, v4, v14 -; GCN-NEXT: v_mul_hi_u32 v15, v8, v14 -; GCN-NEXT: v_mul_lo_u32 v14, v8, v14 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v11 -; GCN-NEXT: v_mul_lo_u32 v16, v4, v11 -; GCN-NEXT: v_mul_hi_u32 v17, v8, v11 -; GCN-NEXT: v_mul_lo_u32 v11, v8, v11 -; GCN-NEXT: v_add_i32_e32 v13, vcc, v13, v16 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v12, vcc -; GCN-NEXT: v_add_i32_e32 v13, vcc, v14, v13 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v12, v15, vcc -; GCN-NEXT: v_addc_u32_e32 v13, vcc, v17, v5, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v7, v4 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v6, v13, vcc -; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v11 -; GCN-NEXT: v_addc_u32_e64 v11, vcc, v8, v12, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v13, v9, v4 -; GCN-NEXT: v_mul_lo_u32 v10, v10, v4 -; GCN-NEXT: v_mul_lo_u32 v14, v9, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v12 -; GCN-NEXT: v_mul_lo_u32 v9, v9, v11 -; GCN-NEXT: v_mul_hi_u32 v12, v11, v14 -; GCN-NEXT: v_mul_lo_u32 v15, v11, v14 -; GCN-NEXT: v_mul_hi_u32 v14, v4, v14 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v13, v9 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v11, v9 -; GCN-NEXT: v_mul_hi_u32 v13, v4, v9 -; GCN-NEXT: v_mul_lo_u32 v16, v4, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v11, v9 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v14, v16 -; GCN-NEXT: v_addc_u32_e32 v13, vcc, v6, v13, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v15, v11 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v13, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v5, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v6, v10, vcc -; GCN-NEXT: v_addc_u32_e64 v8, vcc, v8, v10, s[4:5] -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v0, v8 -; GCN-NEXT: v_mul_lo_u32 v12, v0, v8 -; GCN-NEXT: v_mul_hi_u32 v13, v1, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v1, v8 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v6, v11, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v9 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v5, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v6, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 +; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v8, v6 +; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12 +; GCN-NEXT: v_mul_hi_u32 v10, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc +; GCN-NEXT: v_mul_lo_u32 v7, v8, v7 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v12 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 +; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v6 +; GCN-NEXT: v_xor_b32_e32 v0, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc +; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v14, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v9, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v1, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v10, v13, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v7, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v5 +; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v5 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc +; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v7, v3, vcc +; GCN-NEXT: v_sub_i32_e64 v7, s[4:5], v0, v2 +; GCN-NEXT: v_subb_u32_e64 v8, s[6:7], v4, v3, s[4:5] +; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v6, vcc, v0, v2 -; GCN-NEXT: v_subb_u32_e64 v8, s[4:5], v4, v3, vcc -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v2, vcc, v6, v2 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v2 ; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 -; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] -; GCN-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v3 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v10, s[4:5] +; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v7, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GCN-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GCN-NEXT: v_cndmask_b32_e32 v5, v10, v5, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v8, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v7 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v10, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v8, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_xor_b32_e32 v0, v0, v6 +; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_srem: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v1 +; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v6, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v4 ; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v4 -; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4 -; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v6 -; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v6 -; GCN-IR-NEXT: v_mov_b32_e32 v13, v12 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 -; GCN-IR-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] +; GCN-IR-NEXT: v_xor_b32_e32 v2, v2, v6 +; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, v2, v6 +; GCN-IR-NEXT: v_xor_b32_e32 v3, v3, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v3, v6, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[5:6] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] -; GCN-IR-NEXT: v_ffbh_u32_e32 v6, v2 -; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v3 -; GCN-IR-NEXT: v_ffbh_u32_e32 v8, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v9, v1 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v5 ; GCN-IR-NEXT: s_or_b64 s[6:7], vcc, s[4:5] -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 32, v6 -; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 32, v8 -; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GCN-IR-NEXT: v_cndmask_b32_e32 v15, v7, v6, vcc +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 32, v3 +; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v6 +; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 +; GCN-IR-NEXT: v_cndmask_b32_e32 v12, v7, v3, vcc +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v0 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 32, v3 +; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-IR-NEXT: v_cndmask_b32_e32 v14, v9, v8, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v15, v14 +; GCN-IR-NEXT: v_cndmask_b32_e32 v14, v7, v3, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v12, v14 ; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], 0, 0, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[7:8] ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[7:8] ; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc -; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v1, 0, s[6:7] +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1 +; GCN-IR-NEXT: v_mov_b32_e32 v2, v4 +; GCN-IR-NEXT: v_mov_b32_e32 v15, v13 +; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v1, 0, s[6:7] ; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] -; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[6:7] +; GCN-IR-NEXT: v_cndmask_b32_e64 v9, v0, 0, s[6:7] ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v7 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v8, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 63, v7 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], 63, v7 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[7:8] -; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[0:1], v6 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 +; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[0:1], v3 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, -1, v5 ; GCN-IR-NEXT: v_lshr_b64 v[16:17], v[0:1], v9 -; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, -1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v3, vcc -; GCN-IR-NEXT: v_not_b32_e32 v10, v15 -; GCN-IR-NEXT: v_not_b32_e32 v11, v12 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v6, vcc +; GCN-IR-NEXT: v_not_b32_e32 v10, v12 +; GCN-IR-NEXT: v_not_b32_e32 v11, v13 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, v10, v14 -; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, v11, v13, vcc +; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, v11, v15, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 ; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: v_lshl_b64 v[16:17], v[16:17], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v7 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 -; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 -; GCN-IR-NEXT: v_or_b32_e32 v7, v15, v7 -; GCN-IR-NEXT: v_or_b32_e32 v6, v14, v6 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v10, 31, v8 +; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v10 +; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 +; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v3, v16 +; GCN-IR-NEXT: v_subb_u32_e32 v10, vcc, v9, v17, vcc +; GCN-IR-NEXT: v_or_b32_e32 v7, v14, v7 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v14, 31, v10 +; GCN-IR-NEXT: v_and_b32_e32 v19, v14, v5 +; GCN-IR-NEXT: v_and_b32_e32 v10, 1, v14 +; GCN-IR-NEXT: v_and_b32_e32 v18, v14, v6 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v12 +; GCN-IR-NEXT: v_or_b32_e32 v8, v15, v8 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v13, vcc -; GCN-IR-NEXT: v_or_b32_e32 v16, v16, v10 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[12:13] -; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v8, v16 -; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v9, v17, s[4:5] -; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v10 -; GCN-IR-NEXT: v_and_b32_e32 v10, 1, v12 -; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3 -; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2 -; GCN-IR-NEXT: v_sub_i32_e32 v16, vcc, v16, v12 -; GCN-IR-NEXT: v_subb_u32_e32 v17, vcc, v17, v13, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v12, v14 +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v16, s[4:5], v16, v19 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v15 ; GCN-IR-NEXT: v_mov_b32_e32 v15, v11 +; GCN-IR-NEXT: v_subb_u32_e64 v17, s[4:5], v17, v18, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v14, v10 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB1_3 @@ -453,23 +453,23 @@ ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: BB1_5: ; %Flow3 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] -; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 -; GCN-IR-NEXT: v_or_b32_e32 v9, v11, v7 -; GCN-IR-NEXT: v_or_b32_e32 v6, v10, v6 +; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 +; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v8 +; GCN-IR-NEXT: v_or_b32_e32 v9, v10, v7 ; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_mul_lo_u32 v7, v2, v9 -; GCN-IR-NEXT: v_mul_hi_u32 v8, v2, v6 -; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6 -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, v8, v7 -; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_mul_lo_u32 v3, v5, v3 +; GCN-IR-NEXT: v_mul_hi_u32 v7, v5, v9 +; GCN-IR-NEXT: v_mul_lo_u32 v6, v6, v9 +; GCN-IR-NEXT: v_mul_lo_u32 v5, v5, v9 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v7, v3 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v4 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v5 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %result = srem i64 %x, %y ret i64 %result @@ -479,30 +479,30 @@ ; GCN-LABEL: s_test_srem23_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 41 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 41 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 41 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 41 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_xor_b32 s1, s6, s0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 23 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -511,30 +511,30 @@ ; GCN-IR-LABEL: s_test_srem23_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 41 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 41 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 41 +; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 41 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_xor_b32 s1, s6, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_or_b32 s1, s1, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s1 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s5 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 23 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -550,30 +550,30 @@ ; GCN-LABEL: s_test_srem24_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 40 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 40 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_xor_b32 s1, s6, s0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -582,30 +582,30 @@ ; GCN-IR-LABEL: s_test_srem24_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 40 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 40 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_xor_b32 s1, s6, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_or_b32 s1, s1, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s1 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s5 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -621,22 +621,22 @@ ; GCN-LABEL: v_test_srem24_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: v_ashr_i64 v[2:3], v[2:3], 40 ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 -; GCN-NEXT: v_ashr_i64 v[1:2], v[2:3], 40 -; GCN-NEXT: v_xor_b32_e32 v2, v0, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v3, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v4, v1 -; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v4 -; GCN-NEXT: v_or_b32_e32 v2, 1, v2 -; GCN-NEXT: v_mul_f32_e32 v5, v3, v5 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3 -; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4| -; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 -; GCN-NEXT: v_mul_lo_u32 v1, v2, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_xor_b32_e32 v5, v0, v2 +; GCN-NEXT: v_ashrrev_i32_e32 v5, 30, v5 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v3 +; GCN-NEXT: v_or_b32_e32 v5, 1, v5 +; GCN-NEXT: v_mul_f32_e32 v4, v1, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v1, -v4, v3, v1 +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3| +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; GCN-NEXT: v_mul_lo_u32 v1, v1, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -645,22 +645,22 @@ ; GCN-IR-LABEL: v_test_srem24_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-IR-NEXT: v_ashr_i64 v[2:3], v[2:3], 40 ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 -; GCN-IR-NEXT: v_ashr_i64 v[1:2], v[2:3], 40 -; GCN-IR-NEXT: v_xor_b32_e32 v2, v0, v1 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v4, v1 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 30, v2 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v5, v4 -; GCN-IR-NEXT: v_or_b32_e32 v2, 1, v2 -; GCN-IR-NEXT: v_mul_f32_e32 v5, v3, v5 -; GCN-IR-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-IR-NEXT: v_mad_f32 v3, -v5, v4, v3 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v5, v5 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4| -; GCN-IR-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc -; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v5, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v1, v2, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_xor_b32_e32 v5, v0, v2 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v5, 30, v5 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v4, v3 +; GCN-IR-NEXT: v_or_b32_e32 v5, 1, v5 +; GCN-IR-NEXT: v_mul_f32_e32 v4, v1, v4 +; GCN-IR-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-IR-NEXT: v_mad_f32 v1, -v4, v3, v1 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3| +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v4, v1 +; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 @@ -675,30 +675,30 @@ ; GCN-LABEL: s_test_srem25_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 39 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 39 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 39 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_xor_b32 s1, s6, s0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -707,30 +707,30 @@ ; GCN-IR-LABEL: s_test_srem25_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 39 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 39 +; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 39 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_xor_b32 s1, s6, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_or_b32 s1, s1, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s1 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s5 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -746,30 +746,30 @@ ; GCN-LABEL: s_test_srem31_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-NEXT: s_ashr_i64 s[6:7], s[8:9], 33 -; GCN-NEXT: s_xor_b32 s5, s4, s6 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 33 +; GCN-NEXT: s_ashr_i64 s[0:1], s[0:1], 33 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_xor_b32 s1, s6, s0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s1 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -778,30 +778,30 @@ ; GCN-IR-LABEL: s_test_srem31_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[8:9], 33 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s6 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 33 +; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[0:1], 33 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 ; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s6 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_xor_b32 s1, s6, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_or_b32 s1, s1, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s1 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s5 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s6 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -818,27 +818,27 @@ ; GCN-LABEL: s_test_srem32_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, s7 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 +; GCN-NEXT: s_xor_b32 s1, s7, s0 +; GCN-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mov_b32_e32 v3, s1 ; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_xor_b32 s4, s7, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s7 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s8 -; GCN-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: s_or_b32 s4, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v3, s4 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s7, v0 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -847,27 +847,27 @@ ; GCN-IR-LABEL: s_test_srem32_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s7 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 +; GCN-IR-NEXT: s_xor_b32 s1, s7, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s1, 30 +; GCN-IR-NEXT: s_or_b32 s1, s1, 1 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s1 ; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_xor_b32 s4, s7, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s7 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s8 -; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: s_or_b32 s4, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s4 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v1| +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| ; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s7, v0 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 @@ -884,258 +884,258 @@ ; GCN-LABEL: s_test_srem33_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s8 -; GCN-NEXT: s_mov_b32 s5, s9 -; GCN-NEXT: s_ashr_i64 s[0:1], s[10:11], 31 -; GCN-NEXT: s_ashr_i32 s8, s3, 31 -; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 31 -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: s_add_u32 s2, s2, s8 -; GCN-NEXT: s_addc_u32 s3, s3, s8 -; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s12, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s13, 0, s3 -; GCN-NEXT: s_ashr_i32 s8, s11, 31 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: s_add_u32 s0, s0, s8 -; GCN-NEXT: v_mov_b32_e32 v3, s8 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: s_addc_u32 s1, s1, s8 -; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mov_b32_e32 v6, s11 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: s_ashr_i64 s[2:3], s[10:11], 31 +; GCN-NEXT: s_ashr_i64 s[4:5], s[0:1], 31 +; GCN-NEXT: s_ashr_i32 s0, s1, 31 +; GCN-NEXT: s_add_u32 s4, s4, s0 +; GCN-NEXT: s_mov_b32 s1, s0 +; GCN-NEXT: s_addc_u32 s5, s5, s0 +; GCN-NEXT: s_xor_b64 s[12:13], s[4:5], s[0:1] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GCN-NEXT: s_sub_u32 s4, 0, s12 +; GCN-NEXT: s_subb_u32 s5, 0, s13 +; GCN-NEXT: s_ashr_i32 s10, s11, 31 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_mov_b32 s11, s10 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v7, s12, v5 -; GCN-NEXT: v_mul_lo_u32 v8, s13, v2 -; GCN-NEXT: v_mul_hi_u32 v9, s12, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s12, v2 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v10 -; GCN-NEXT: v_mul_lo_u32 v10, v5, v10 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v12, v2, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v5, v7 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v0, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v9, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v7 -; GCN-NEXT: v_addc_u32_e64 v7, vcc, v5, v8, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v9, s12, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s13, v2 -; GCN-NEXT: v_mul_lo_u32 v11, s12, v2 -; GCN-NEXT: v_mul_lo_u32 v12, s12, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v7, v11 -; GCN-NEXT: v_mul_lo_u32 v14, v7, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v11 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v12 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v7, v9 -; GCN-NEXT: v_mul_hi_u32 v12, v2, v9 -; GCN-NEXT: v_mul_lo_u32 v15, v2, v9 -; GCN-NEXT: v_mul_lo_u32 v7, v7, v9 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v11, v15 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v1, v12, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v14, v9 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v13, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v10, v0, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v10, vcc -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v8, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v7, s10, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s11, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 -; GCN-NEXT: v_mul_hi_u32 v9, s10, v5 -; GCN-NEXT: v_mul_lo_u32 v10, s10, v5 -; GCN-NEXT: v_mul_hi_u32 v11, s11, v5 -; GCN-NEXT: v_mul_lo_u32 v5, s11, v5 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v9, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v7 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v8, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v11, v0, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v5, s3, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5 -; GCN-NEXT: v_sub_i32_e32 v1, vcc, s11, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2 -; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subb_u32_e32 v0, vcc, v6, v0, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v6, vcc, s2, v2 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v6 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v8, vcc, s2, v6 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0 -; GCN-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v7, v10, v7, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v5, s4, v3 +; GCN-NEXT: v_mul_hi_u32 v6, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v3, v5 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v7, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v10 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[0:1] +; GCN-NEXT: s_add_u32 s0, s2, s10 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: s_addc_u32 s1, s3, s10 +; GCN-NEXT: s_xor_b64 s[14:15], s[0:1], s[10:11] +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s14, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s14, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s14, v2 +; GCN-NEXT: v_mul_hi_u32 v6, s15, v2 +; GCN-NEXT: v_mul_lo_u32 v2, s15, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s15, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s15, v0 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s15, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s13 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s14, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s12, v4 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v8, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] -; GCN-NEXT: v_xor_b32_e32 v2, s8, v0 -; GCN-NEXT: v_xor_b32_e32 v0, s8, v1 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v3, s15 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_xor_b32_e32 v0, s10, v0 +; GCN-NEXT: v_xor_b32_e32 v1, s10, v1 +; GCN-NEXT: v_mov_b32_e32 v2, s10 +; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem33_64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd +; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[6:7], 31 ; GCN-IR-NEXT: s_ashr_i32 s2, s7, 31 -; GCN-IR-NEXT: s_ashr_i32 s6, s9, 31 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[8:9], 31 +; GCN-IR-NEXT: s_ashr_i64 s[10:11], s[0:1], 31 +; GCN-IR-NEXT: s_ashr_i32 s0, s1, 31 +; GCN-IR-NEXT: s_mov_b32 s1, s0 +; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[6:7], 31 ; GCN-IR-NEXT: s_mov_b32 s3, s2 -; GCN-IR-NEXT: s_mov_b32 s7, s6 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] -; GCN-IR-NEXT: s_xor_b64 s[10:11], s[8:9], s[6:7] -; GCN-IR-NEXT: s_sub_u32 s8, s0, s2 -; GCN-IR-NEXT: s_subb_u32 s9, s1, s2 -; GCN-IR-NEXT: s_flbit_i32_b32 s7, s8 -; GCN-IR-NEXT: s_sub_u32 s10, s10, s6 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s12, s9 -; GCN-IR-NEXT: s_subb_u32 s11, s11, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s10 -; GCN-IR-NEXT: s_add_i32 s14, s7, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0 -; GCN-IR-NEXT: s_add_i32 s12, s13, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s11 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 -; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s12 +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[8:9], s[2:3] +; GCN-IR-NEXT: s_xor_b64 s[10:11], s[10:11], s[0:1] +; GCN-IR-NEXT: s_sub_u32 s8, s6, s2 +; GCN-IR-NEXT: s_subb_u32 s9, s7, s2 +; GCN-IR-NEXT: s_sub_u32 s10, s10, s0 +; GCN-IR-NEXT: s_subb_u32 s11, s11, s0 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[10:11], 0 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[8:9], 0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s11, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[6:7], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[6:7], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7] -; GCN-IR-NEXT: s_cbranch_vccz BB8_2 +; GCN-IR-NEXT: s_or_b64 s[6:7], s[0:1], s[6:7] +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s10 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s11 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s8 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s9 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-IR-NEXT: s_cbranch_vccz BB8_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s9 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[6:7] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[6:7] ; GCN-IR-NEXT: s_branch BB8_7 ; GCN-IR-NEXT: BB8_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[8:9], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB8_6 ; GCN-IR-NEXT: BB8_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[8:9], v4 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: s_add_u32 s6, s10, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[8:9], v4 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s11, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB8_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s7 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s6, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s10, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s11, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s10, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s11, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB8_5 ; GCN-IR-NEXT: BB8_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB8_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s10, v1 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s10, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s11, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s10, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v4, s9 -; GCN-IR-NEXT: v_mov_b32_e32 v5, s3 +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s8, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v2, s9 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 31 @@ -1151,32 +1151,32 @@ ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-NEXT: s_load_dword s2, s[0:1], 0xb ; GCN-NEXT: s_load_dword s3, s[0:1], 0xc -; GCN-NEXT: s_load_dword s8, s[0:1], 0xd -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: s_load_dword s6, s[0:1], 0xd +; GCN-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_sext_i32_i16 s0, s3 -; GCN-NEXT: s_sext_i32_i16 s1, s9 -; GCN-NEXT: v_mov_b32_e32 v0, s8 -; GCN-NEXT: v_mov_b32_e32 v1, s2 -; GCN-NEXT: v_alignbit_b32 v0, s1, v0, 24 -; GCN-NEXT: v_alignbit_b32 v1, s0, v1, 24 -; GCN-NEXT: v_xor_b32_e32 v2, v1, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v3, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v4, v0 -; GCN-NEXT: v_ashrrev_i32_e32 v2, 30, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v4 -; GCN-NEXT: v_or_b32_e32 v2, 1, v2 -; GCN-NEXT: v_mul_f32_e32 v5, v3, v5 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mad_f32 v3, -v5, v4, v3 -; GCN-NEXT: v_cvt_i32_f32_e32 v5, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v4| -; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_lo_u32 v0, v2, v0 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: s_sext_i32_i16 s1, s3 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: s_sext_i32_i16 s0, s0 +; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 24 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 24 +; GCN-NEXT: v_cvt_f32_i32_e32 v3, v2 +; GCN-NEXT: v_xor_b32_e32 v5, v2, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v1 +; GCN-NEXT: v_ashrrev_i32_e32 v5, 30, v5 +; GCN-NEXT: v_or_b32_e32 v5, 1, v5 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v1, v3 +; GCN-NEXT: v_cvt_i32_f32_e32 v4, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v2, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 @@ -1185,126 +1185,128 @@ ; ; GCN-IR-LABEL: s_test_srem24_48: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dword s7, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc -; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe ; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb -; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd +; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xc +; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_sext_i32_i16 s3, s3 -; GCN-IR-NEXT: s_sext_i32_i16 s7, s7 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 24 +; GCN-IR-NEXT: s_sext_i32_i16 s5, s3 +; GCN-IR-NEXT: s_ashr_i32 s10, s5, 31 +; GCN-IR-NEXT: s_sext_i32_i16 s3, s6 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[2:3], 24 ; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 -; GCN-IR-NEXT: s_ashr_i32 s10, s7, 31 -; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 24 ; GCN-IR-NEXT: s_mov_b32 s3, s2 +; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[4:5], 24 ; GCN-IR-NEXT: s_mov_b32 s11, s10 -; GCN-IR-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3] -; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11] -; GCN-IR-NEXT: s_sub_u32 s8, s0, s2 -; GCN-IR-NEXT: s_subb_u32 s9, s1, s2 -; GCN-IR-NEXT: s_flbit_i32_b32 s11, s8 -; GCN-IR-NEXT: s_sub_u32 s6, s6, s10 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[8:9], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s12, s9 -; GCN-IR-NEXT: s_subb_u32 s7, s7, s10 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s6 -; GCN-IR-NEXT: s_add_i32 s14, s11, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0 -; GCN-IR-NEXT: s_add_i32 s12, s13, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s14 +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3] +; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], s[10:11] +; GCN-IR-NEXT: s_sub_u32 s6, s6, s2 +; GCN-IR-NEXT: s_subb_u32 s7, s7, s2 +; GCN-IR-NEXT: s_sub_u32 s8, s4, s10 +; GCN-IR-NEXT: s_subb_u32 s9, s5, s10 +; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s8 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s9 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s9, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v1, s13 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s12 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[10:11], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[10:11], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[10:11] +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 0 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[10:11], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_mov_b64 vcc, vcc ; GCN-IR-NEXT: s_cbranch_vccz BB9_2 ; GCN-IR-NEXT: ; %bb.1: -; GCN-IR-NEXT: v_mov_b32_e32 v0, s9 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11] +; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11] ; GCN-IR-NEXT: s_branch BB9_7 ; GCN-IR-NEXT: BB9_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: BB9_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[8:9], v4 -; GCN-IR-NEXT: s_add_u32 s10, s6, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 -; GCN-IR-NEXT: s_addc_u32 s11, s7, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 +; GCN-IR-NEXT: s_add_u32 s10, s8, -1 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 +; GCN-IR-NEXT: s_addc_u32 s11, s9, -1 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB9_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s11 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s10, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s6, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s7, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: BB9_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB9_7: ; %udiv-end -; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1 -; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0 -; GCN-IR-NEXT: v_mul_lo_u32 v3, s7, v0 -; GCN-IR-NEXT: v_mul_lo_u32 v0, s6, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v4, s9 -; GCN-IR-NEXT: v_mov_b32_e32 v5, s3 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v3, s9, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v0, s8, v0 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s8, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 ; GCN-IR-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 ; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm @@ -1318,121 +1320,119 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_srem_k_num_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i32 s8, s3, 31 +; GCN-NEXT: s_ashr_i32 s0, s7, 31 +; GCN-NEXT: s_add_u32 s2, s6, s0 +; GCN-NEXT: s_addc_u32 s3, s7, s0 +; GCN-NEXT: s_mov_b32 s1, s0 +; GCN-NEXT: s_xor_b64 s[8:9], s[2:3], s[0:1] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GCN-NEXT: s_sub_u32 s2, 0, s8 +; GCN-NEXT: s_subb_u32 s3, 0, s9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: s_add_u32 s0, s2, s8 -; GCN-NEXT: s_addc_u32 s1, s3, s8 -; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], s[8:9] -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s8, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s9, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v6, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s8, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v8 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v2, v5 -; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v0, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v5 -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_mul_hi_u32 v8, v5, v7 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v7 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v10, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v5, 24, v2 -; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 +; GCN-NEXT: v_mul_hi_u32 v5, 24, v0 +; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v6, 24, v3 -; GCN-NEXT: v_mul_lo_u32 v7, v3, 24 +; GCN-NEXT: v_mul_hi_u32 v0, 0, v0 ; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, 0, v5 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v2, s2, v1 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v1 -; GCN-NEXT: v_mul_lo_u32 v1, s2, v1 -; GCN-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v0 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v1 -; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v2, v4, vcc -; GCN-NEXT: v_subb_u32_e32 v0, vcc, 0, v0, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v3 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0 -; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1] +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s8, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s8, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s9, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s8, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s9 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s8, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v4 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; @@ -1451,78 +1451,78 @@ ; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc5, v0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 -; GCN-IR-NEXT: v_addc_u32_e64 v2, s[6:7], 0, -1, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[6:7], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[6:7] +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 +; GCN-IR-NEXT: v_addc_u32_e64 v1, s[0:1], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] ; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB10_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB10_7 ; GCN-IR-NEXT: BB10_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[1:2] -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 63, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v1 ; GCN-IR-NEXT: s_cbranch_vccz BB10_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB10_6 ; GCN-IR-NEXT: BB10_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v4 ; GCN-IR-NEXT: s_add_u32 s7, s2, -1 -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s8, s3, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB10_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s8 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s7, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s7, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s2, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s3, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB10_5 ; GCN-IR-NEXT: BB10_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB10_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0 +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 @@ -1539,138 +1539,138 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-NEXT: v_mov_b32_e32 v3, 0 -; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, v1 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v0 -; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v1, vcc -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v5 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 +; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v8, v6, v5 -; GCN-NEXT: v_mul_lo_u32 v9, v7, v2 -; GCN-NEXT: v_mul_hi_u32 v10, v6, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v6, v2 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v11 -; GCN-NEXT: v_mul_hi_u32 v12, v5, v11 -; GCN-NEXT: v_mul_lo_u32 v11, v5, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v14, v5, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v9, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v3, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8 -; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v10, v6, v2 -; GCN-NEXT: v_mul_lo_u32 v7, v7, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v6, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v8, v11 -; GCN-NEXT: v_mul_lo_u32 v12, v8, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v11 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v8, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v7, vcc -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, 24, v2 -; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, 24, v5 -; GCN-NEXT: v_mul_lo_u32 v8, v5, 24 -; GCN-NEXT: v_mul_hi_u32 v5, 0, v5 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v9, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v7, v3, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 +; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v6, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v10 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5] +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_hi_u32 v5, 24, v2 +; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 +; GCN-NEXT: v_mul_hi_u32 v6, 24, v3 +; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 +; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v11, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v3, v0, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc +; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0 +; GCN-NEXT: v_subb_u32_e64 v6, s[6:7], v4, v1, s[4:5] +; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v0 ; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 +; GCN-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v7 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v6, vcc, v2, v0 -; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v1, vcc -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v6, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] +; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1 +; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc +; GCN-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v6, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[6:7] +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[6:7] +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_srem_k_num_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 -; GCN-IR-NEXT: s_movk_i32 s4, 0xffc5 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc -; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s4, v8 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] +; GCN-IR-NEXT: s_movk_i32 s6, 0xffc5 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v8 ; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, 24, 0, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] @@ -1678,47 +1678,47 @@ ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, 1, v3 ; GCN-IR-NEXT: v_addc_u32_e32 v6, vcc, 0, v4, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v3 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v3 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[5:6], v[3:4] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v2 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB11_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v5 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v0 +; GCN-IR-NEXT: v_lshr_b64 v[10:11], 24, v5 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 58, v8 -; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 +; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: BB11_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v4, v10 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v5, v11, vcc ; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 +; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0 +; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 +; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 +; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] -; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v10 -; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v5, v11, s[4:5] -; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 -; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v1 -; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v8 -; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v9, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 +; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB11_3 @@ -1735,8 +1735,8 @@ ; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2 -; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v3 -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -1749,193 +1749,193 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-NEXT: v_mov_b32_e32 v3, 0 -; GCN-NEXT: v_mov_b32_e32 v4, 0 -; GCN-NEXT: s_mov_b32 s6, 0x8000 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc ; GCN-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, v1 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v0 -; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v1, vcc -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v5 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 +; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc +; GCN-NEXT: v_mov_b32_e32 v12, 0 +; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v8, v6, v5 -; GCN-NEXT: v_mul_lo_u32 v9, v7, v2 -; GCN-NEXT: v_mul_hi_u32 v10, v6, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v6, v2 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v11 -; GCN-NEXT: v_mul_hi_u32 v12, v5, v11 -; GCN-NEXT: v_mul_lo_u32 v11, v5, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v14, v5, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v9, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v3, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8 -; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v10, v6, v2 -; GCN-NEXT: v_mul_lo_u32 v7, v7, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v6, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v8, v11 -; GCN-NEXT: v_mul_lo_u32 v12, v8, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v11 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v8, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v3, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v7, vcc -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, s6, v2 -; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s6, v5 -; GCN-NEXT: v_lshlrev_b32_e32 v8, 15, v5 -; GCN-NEXT: v_mul_hi_u32 v5, 0, v5 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v9, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v7, v3, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 +; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v6, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v10 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5] +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: s_mov_b32 s4, 0x8000 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_hi_u32 v4, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v5, s4, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v6, 15, v3 +; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v5, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v11, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v3, v0, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v2 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc +; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0 +; GCN-NEXT: v_subb_u32_e64 v6, s[6:7], v4, v1, s[4:5] +; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v0 ; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 +; GCN-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v7 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v6, vcc, v2, v0 -; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v1, vcc -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v6, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] +; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1 +; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc +; GCN-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v6, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[6:7] +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[6:7] +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_srem_pow2_k_num_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-IR-NEXT: s_mov_b32 s11, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: s_movk_i32 s4, 0xffd0 -; GCN-IR-NEXT: s_mov_b32 s10, 0x8000 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_mov_b32_e32 v5, s10 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-IR-NEXT: v_cndmask_b32_e32 v9, v3, v2, vcc -; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s4, v9 +; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc +; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v8 +; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] -; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] +; GCN-IR-NEXT: s_mov_b32 s8, 0x8000 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc -; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v5, 0, s[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, s8 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] -; GCN-IR-NEXT: v_mov_b32_e32 v5, v6 +; GCN-IR-NEXT: s_mov_b32 s9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB12_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v3 -; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v4, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v3 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[2:3] +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 +; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[11:12], v[3:4] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[10:11], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s4, 0x8000 +; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v4 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v1, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v9, vcc, 47, v9 -; GCN-IR-NEXT: v_subb_u32_e32 v10, vcc, 0, v6, vcc -; GCN-IR-NEXT: v_lshr_b64 v[13:14], s[4:5], v11 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 +; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[13:14], v[13:14], 1 +; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 +; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v3, v12, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v11, v2 -; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v9 -; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v10, vcc -; GCN-IR-NEXT: v_or_b32_e32 v6, v13, v6 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[9:10] -; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v4, v6 -; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], v5, v14, s[4:5] +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v4, v10 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v5, v11, vcc +; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 +; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0 +; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 +; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1 +; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 +; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 +; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 +; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 +; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v7 -; GCN-IR-NEXT: v_and_b32_e32 v7, 1, v9 -; GCN-IR-NEXT: v_and_b32_e32 v10, v9, v1 -; GCN-IR-NEXT: v_and_b32_e32 v9, v9, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v13, vcc, v6, v9 -; GCN-IR-NEXT: v_subb_u32_e32 v14, vcc, v14, v10, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v9, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v10, v12 -; GCN-IR-NEXT: v_mov_b32_e32 v12, v8 -; GCN-IR-NEXT: v_mov_b32_e32 v11, v7 +; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1943,17 +1943,17 @@ ; GCN-IR-NEXT: BB12_5: ; %Flow3 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v5, v8, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v7, v2 +; GCN-IR-NEXT: v_or_b32_e32 v5, v7, v3 +; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v2 ; GCN-IR-NEXT: BB12_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v5 -; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2 -; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v3 +; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5 +; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 -; GCN-IR-NEXT: v_add_i32_e64 v1, s[4:5], v2, v1 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %result = srem i64 32768, %x @@ -1977,72 +1977,72 @@ ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 31, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 -; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] -; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 -; GCN-IR-NEXT: v_add_i32_e64 v4, s[4:5], 32, v4 +; GCN-IR-NEXT: v_add_i32_e64 v3, s[4:5], 32, v3 +; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 -; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v5, v4, s[4:5] +; GCN-IR-NEXT: v_cndmask_b32_e64 v8, v4, v3, s[4:5] ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v8 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v3, v2 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[6:7] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB13_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 63, v4 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[9:10], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v6 +; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB13_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v9 +; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 +; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: BB13_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v16, 0 -; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v8 -; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 -; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5 -; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4 -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], v[14:15], v[8:9] -; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v12 -; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] -; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v13, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 -; GCN-IR-NEXT: v_and_b32_e32 v8, 0x8000, v8 -; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v8 -; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v16, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v8, v14 -; GCN-IR-NEXT: v_mov_b32_e32 v9, v15 -; GCN-IR-NEXT: v_mov_b32_e32 v11, v7 -; GCN-IR-NEXT: v_mov_b32_e32 v10, v6 +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc +; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 +; GCN-IR-NEXT: v_and_b32_e32 v14, 0x8000, v12 +; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 +; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 +; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 +; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 +; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 +; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v14 +; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v15, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB13_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -2057,8 +2057,8 @@ ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[6:7], 15 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc -; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3 ; GCN-IR-NEXT: v_xor_b32_e32 v0, v0, v2 +; GCN-IR-NEXT: v_xor_b32_e32 v1, v1, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -2070,59 +2070,55 @@ ; GCN-LABEL: s_test_srem24_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_mov_b32 s6, 0x41c00000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-NEXT: s_or_b32 s1, s1, 1 +; GCN-NEXT: s_ashr_i64 s[4:5], s[2:3], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-NEXT: s_ashr_i32 s5, s4, 30 +; GCN-NEXT: s_or_b32 s5, s5, 1 +; GCN-NEXT: v_mov_b32_e32 v3, s5 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-NEXT: v_mul_f32_e32 v1, s2, v1 -; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_mul_f32_e32 v1, s6, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v3, -v1, v0, s2 +; GCN-NEXT: v_mad_f32 v2, -v1, v0, s6 ; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0| +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem24_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_mov_b32 s6, 0x41c00000 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-IR-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-IR-NEXT: s_or_b32 s1, s1, 1 +; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[2:3], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s4 +; GCN-IR-NEXT: s_ashr_i32 s5, s4, 30 +; GCN-IR-NEXT: s_or_b32 s5, s5, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v3, s5 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v1, s2, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: v_mul_f32_e32 v1, s6, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v3, -v1, v0, s2 +; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s6 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, |v0| -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0| +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = ashr i64 %x, 40 %result = srem i64 24, %x.shr @@ -2133,60 +2129,60 @@ define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_srem24_k_den_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s8, 0x46b6fe00 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-NEXT: s_or_b32 s1, s1, 1 -; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 -; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mov_b32_e32 v2, s1 -; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0 -; GCN-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 -; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: s_movk_i32 s1, 0x5b7f -; GCN-NEXT: v_mul_lo_u32 v0, v0, s1 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-NEXT: s_ashr_i32 s0, s6, 30 +; GCN-NEXT: s_or_b32 s0, s0, 1 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: v_mul_f32_e32 v2, 0x38331158, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v0, -v2, s8, v0 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s8 +; GCN-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-NEXT: s_movk_i32 s0, 0x5b7f +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem24_k_den_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-IR-NEXT: s_mov_b32 s8, 0x46b6fe00 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_ashr_i64 s[0:1], s[2:3], 40 -; GCN-IR-NEXT: s_ashr_i32 s1, s0, 30 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s0 -; GCN-IR-NEXT: s_or_b32 s1, s1, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 -; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s1 -; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-IR-NEXT: s_movk_i32 s1, 0x5b7f -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s1 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GCN-IR-NEXT: s_ashr_i64 s[6:7], s[6:7], 40 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s6 +; GCN-IR-NEXT: s_ashr_i32 s0, s6, 30 +; GCN-IR-NEXT: s_or_b32 s0, s0, 1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38331158, v0 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v0, -v2, s8, v0 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s8 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc +; GCN-IR-NEXT: s_movk_i32 s0, 0x5b7f +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = ashr i64 %x, 40 %result = srem i64 %x.shr, 23423 @@ -2200,17 +2196,17 @@ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-NEXT: s_mov_b32 s4, 0x41c00000 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v2, v0 -; GCN-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v2 -; GCN-NEXT: v_mul_f32_e32 v3, s4, v3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v4, -v3, v2, s4 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v3, 30, v0 +; GCN-NEXT: v_or_b32_e32 v3, 1, v3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v4, -v2, v1, s4 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-NEXT: v_mul_lo_u32 v0, v1, v0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -2222,17 +2218,17 @@ ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, v0 -; GCN-IR-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mul_f32_e32 v3, s4, v3 -; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v4, -v3, v2, s4 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v3, 1, v3 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v4, -v2, v1, s4 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -2249,17 +2245,17 @@ ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-NEXT: s_mov_b32 s4, 0x47000000 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-NEXT: v_cvt_f32_i32_e32 v2, v0 -; GCN-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v2 -; GCN-NEXT: v_mul_f32_e32 v3, s4, v3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v4, -v3, v2, s4 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 +; GCN-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-NEXT: v_ashrrev_i32_e32 v3, 30, v0 +; GCN-NEXT: v_or_b32_e32 v3, 1, v3 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mad_f32 v4, -v2, v1, s4 +; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1| +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-NEXT: v_mul_lo_u32 v0, v1, v0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -2271,17 +2267,17 @@ ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, v0 -; GCN-IR-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mul_f32_e32 v3, s4, v3 -; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v4, -v3, v2, s4 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v2| -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v3, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v3, 1, v3 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mad_f32 v4, -v2, v1, s4 +; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, |v1| +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 24 @@ -2310,15 +2306,15 @@ ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_ashr_i64 v[0:1], v[0:1], 40 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 30, v0 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v2, v0 -; GCN-IR-NEXT: v_or_b32_e32 v1, 1, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v3, 0x38000000, v2 +; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v2, 30, v0 +; GCN-IR-NEXT: v_or_b32_e32 v2, 1, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v3, 0x38000000, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v2, -v3, s4, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v3, s4, v1 ; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, s4 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4 +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v3, v1 ; GCN-IR-NEXT: v_lshlrev_b32_e32 v1, 15, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -1,127 +1,127 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_udiv_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s8 -; GCN-NEXT: s_mov_b32 s5, s9 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s8, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mov_b32_e32 v5, s11 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s9, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: s_sub_u32 s4, 0, s2 +; GCN-NEXT: s_subb_u32 s5, 0, s3 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v6, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v7, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s8, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v3, v9 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v11, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc +; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s5, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, s4, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v6 -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v8, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v11, s8, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v10 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v14, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GCN-NEXT: v_mul_lo_u32 v7, s4, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc -; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v7, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v6, s10, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s11, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s10, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v10, s11, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v2 -; GCN-NEXT: v_mul_lo_u32 v6, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 -; GCN-NEXT: v_add_i32_e32 v8, vcc, 2, v2 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, 1, v2 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v7 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, s11, v1 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, s10, v6 -; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v6 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v5, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v6 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 +; GCN-NEXT: v_mov_b32_e32 v5, s3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 +; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] +; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v6, s11 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v10, v8, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; @@ -130,89 +130,89 @@ ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s0, s2 -; GCN-IR-NEXT: s_add_i32 s11, s0, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s12, s3 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7 -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] -; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 -; GCN-IR-NEXT: s_add_i32 s8, s10, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s13 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 +; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 +; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], s[8:9] +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 +; GCN-IR-NEXT: s_add_i32 s10, s10, 32 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[8:9], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB0_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB0_7 ; GCN-IR-NEXT: BB0_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[6:7], v4 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 ; GCN-IR-NEXT: s_add_u32 s6, s2, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s3, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s7 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s6, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s2, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s3, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB0_7: ; %udiv-end ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 @@ -231,110 +231,110 @@ ; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc -; GCN-NEXT: v_mov_b32_e32 v8, 0 -; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 ; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GCN-NEXT: v_rcp_f32_e32 v4, v4 +; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 ; GCN-NEXT: v_trunc_f32_e32 v5, v5 ; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GCN-NEXT: v_mul_lo_u32 v10, v6, v5 -; GCN-NEXT: v_mul_lo_u32 v11, v7, v4 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v4 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v12, v10 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v13 -; GCN-NEXT: v_mul_hi_u32 v14, v5, v13 -; GCN-NEXT: v_mul_lo_u32 v13, v5, v13 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v4, v10 -; GCN-NEXT: v_mul_lo_u32 v15, v4, v10 -; GCN-NEXT: v_mul_hi_u32 v16, v5, v10 -; GCN-NEXT: v_mul_lo_u32 v10, v5, v10 -; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v15 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v11, vcc -; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v11, v14, vcc -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v16, v8, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v12, vcc -; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v10 -; GCN-NEXT: v_addc_u32_e64 v10, vcc, v5, v11, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v12, v6, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v7, v4 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v11 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v10, v13 -; GCN-NEXT: v_mul_lo_u32 v14, v10, v13 -; GCN-NEXT: v_mul_hi_u32 v13, v4, v13 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 +; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v8, v6 +; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12 +; GCN-NEXT: v_mul_hi_u32 v10, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc +; GCN-NEXT: v_mul_lo_u32 v7, v8, v7 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v12 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v10, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v6 -; GCN-NEXT: v_mul_lo_u32 v15, v4, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v10, v6 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v15 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v12, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v14, v10 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v12, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v5 -; GCN-NEXT: v_mul_lo_u32 v11, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v12, v1, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v11 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v9, v10, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v8, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v7, v3, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v9, v2, v5 -; GCN-NEXT: v_add_i32_e32 v10, vcc, 2, v4 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v12, vcc, 1, v4 -; GCN-NEXT: v_addc_u32_e32 v13, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_sub_i32_e32 v7, vcc, v1, v6 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v8 -; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; GCN-NEXT: v_sub_i32_e32 v8, vcc, v1, v6 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 +; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v8, v3, vcc ; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2 +; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2 +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc +; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5] +; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v4 +; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5] ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v6, vcc, 0, v7, s[4:5] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v8, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 -; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v6, v3 -; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v12, v10, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v4, v1, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v13, v11, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v5, v1, s[4:5] +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 +; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc +; GCN-NEXT: v_cndmask_b32_e64 v7, v10, v8, s[4:5] +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v11, v9, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_udiv_i64: @@ -343,37 +343,37 @@ ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2 -; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v6, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v1 -; GCN-IR-NEXT: s_or_b64 s[6:7], vcc, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 32, v6 -; GCN-IR-NEXT: v_mov_b32_e32 v9, v8 +; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GCN-IR-NEXT: v_cndmask_b32_e32 v11, v5, v4, vcc +; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc +; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 +; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v7, v6, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v11, v10 -; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc +; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v8, v10 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[6:7] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[6:7] -; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc -; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[6:7] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1 -; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[6:7] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; GCN-IR-NEXT: v_mov_b32_e32 v11, v9 +; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5] +; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v6 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7] -; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] @@ -382,36 +382,36 @@ ; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, -1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc -; GCN-IR-NEXT: v_not_b32_e32 v6, v11 -; GCN-IR-NEXT: v_not_b32_e32 v7, v8 +; GCN-IR-NEXT: v_not_b32_e32 v6, v8 +; GCN-IR-NEXT: v_not_b32_e32 v7, v9 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v6, v10 -; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, v7, v9, vcc +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, v7, v11, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 -; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5 +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v0, v12 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v1, v13, vcc ; GCN-IR-NEXT: v_or_b32_e32 v4, v10, v4 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v6 +; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v2 +; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v10 +; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v3 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v8 +; GCN-IR-NEXT: v_or_b32_e32 v5, v11, v5 ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9] -; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v12 -; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v13, s[4:5] -; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 -; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v3 -; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v2 -; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v8 -; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v9, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v8, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v12, v15 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v7 +; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v14, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v10, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB1_3 @@ -435,50 +435,50 @@ ; GCN-LABEL: s_test_udiv24_64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_lshr_b32 s4, s7, 8 -; GCN-NEXT: s_lshr_b32 s5, s8, 8 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_lshr_b32 s0, s0, 8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_lshr_b32 s0, s7, 8 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv24_64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 ; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_lshr_b32 s4, s7, 8 -; GCN-IR-NEXT: s_lshr_b32 s5, s8, 8 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_lshr_b32 s0, s0, 8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_lshr_b32 s0, s7, 8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 40 @@ -492,37 +492,37 @@ ; GCN-LABEL: v_test_udiv24_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_udiv24_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v3 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %1 = lshr i64 %x, 40 %2 = lshr i64 %y, 40 @@ -533,46 +533,48 @@ define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_udiv32_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s7 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s8 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv32_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s7 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s8 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 32 %2 = lshr i64 %y, 32 @@ -585,50 +587,50 @@ ; GCN-LABEL: s_test_udiv31_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_lshr_b32 s4, s7, 1 -; GCN-NEXT: s_lshr_b32 s5, s8, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_lshr_b32 s0, s0, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_lshr_b32 s0, s7, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv31_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 ; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_lshr_b32 s4, s7, 1 -; GCN-IR-NEXT: s_lshr_b32 s5, s8, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_lshr_b32 s0, s0, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_lshr_b32 s0, s7, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 33 @@ -642,50 +644,50 @@ ; GCN-LABEL: s_test_udiv23_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_lshr_b32 s4, s7, 9 -; GCN-NEXT: s_lshr_b32 s5, s8, 9 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: s_lshr_b32 s0, s0, 9 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_lshr_b32 s0, s7, 9 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv23_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 ; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_lshr_b32 s4, s7, 9 -; GCN-IR-NEXT: s_lshr_b32 s5, s8, 9 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: s_lshr_b32 s0, s0, 9 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_lshr_b32 s0, s7, 9 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 41 @@ -698,226 +700,229 @@ define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) { ; GCN-LABEL: s_test_udiv24_i48: ; GCN: ; %bb.0: +; GCN-NEXT: s_load_dword s2, s[0:1], 0xd +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s5, 0xff000000 +; GCN-NEXT: s_mov_b32 s4, 0xffff +; GCN-NEXT: s_load_dword s6, s[0:1], 0xb +; GCN-NEXT: s_load_dword s7, s[0:1], 0xc +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_and_b32 s2, s2, s5 +; GCN-NEXT: s_and_b32 s3, s3, s4 +; GCN-NEXT: v_mov_b32_e32 v0, s2 +; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 24 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0 +; GCN-NEXT: v_cvt_f32_ubyte3_e32 v2, s3 +; GCN-NEXT: s_and_b32 s7, s7, s4 +; GCN-NEXT: s_and_b32 s6, s6, s5 +; GCN-NEXT: v_mac_f32_e32 v1, 0x4f800000, v2 +; GCN-NEXT: v_rcp_f32_e32 v1, v1 +; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 24 +; GCN-NEXT: s_sub_u32 s8, 0, s2 +; GCN-NEXT: s_subb_u32 s9, 0, s3 +; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mul_hi_u32 v4, s8, v1 +; GCN-NEXT: v_mul_lo_u32 v3, s8, v2 +; GCN-NEXT: v_mul_lo_u32 v5, s9, v1 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s2, s[0:1], 0xb -; GCN-NEXT: s_load_dword s3, s[0:1], 0xc -; GCN-NEXT: s_load_dword s8, s[0:1], 0xd -; GCN-NEXT: s_load_dword s9, s[0:1], 0xe +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s8, v1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v2, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e64 v1, s[2:3], v1, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[2:3] +; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 +; GCN-NEXT: v_mul_hi_u32 v6, s8, v1 +; GCN-NEXT: v_mul_lo_u32 v7, s9, v1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v6, s8, v1 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_mul_lo_u32 v11, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v13, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v12, v1, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v11 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[2:3] +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_mov_b32_e32 v3, s6 +; GCN-NEXT: v_alignbit_b32 v3, s7, v3, 24 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GCN-NEXT: v_mul_hi_u32 v5, v3, v1 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v1, 0, v1 +; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v1 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v1 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s0, 0xffff -; GCN-NEXT: s_mov_b32 s10, 0xff000000 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_and_b32 s11, s3, s0 -; GCN-NEXT: s_and_b32 s12, s2, s10 -; GCN-NEXT: s_and_b32 s1, s9, s0 -; GCN-NEXT: s_and_b32 s0, s8, s10 -; GCN-NEXT: s_lshr_b64 s[2:3], s[0:1], 24 -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: v_alignbit_b32 v2, s1, v2, 24 -; GCN-NEXT: v_cvt_f32_ubyte3_e32 v3, s1 -; GCN-NEXT: v_mov_b32_e32 v4, s12 -; GCN-NEXT: v_alignbit_b32 v4, s11, v4, 24 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, v2 -; GCN-NEXT: s_sub_u32 s2, 0, s2 -; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s3, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v3, v5 -; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 -; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v3 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mac_f32_e32 v3, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_mul_lo_u32 v6, s2, v5 -; GCN-NEXT: v_mul_lo_u32 v7, s3, v3 -; GCN-NEXT: v_mul_hi_u32 v8, s2, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s2, v3 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v3, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v5, v9 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v11, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v5, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v5, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e64 v3, s[0:1], v3, v6 -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v5, v7, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v8, s2, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v10, s2, v3 -; GCN-NEXT: v_mul_lo_u32 v11, s2, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v10 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v14, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[0:1] -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v4, v3 -; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 -; GCN-NEXT: v_mul_hi_u32 v7, v4, v5 -; GCN-NEXT: v_mul_lo_u32 v8, v4, v5 -; GCN-NEXT: v_mul_hi_u32 v5, 0, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, 0, v6 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v3, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, 0, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v5, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v6, v2, v0 -; GCN-NEXT: v_add_i32_e32 v7, vcc, 2, v3 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v3 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v6 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_sub_i32_e32 v5, vcc, v4, v2 -; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v4, v2 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, -1, v4, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc +; GCN-NEXT: v_sub_i32_e32 v5, vcc, v3, v0 +; GCN-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v4, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 -; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v2, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v9, v7, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v2, v10, v8, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GCN-NEXT: buffer_store_short v0, off, s[4:7], 0 offset:4 -; GCN-NEXT: buffer_store_dword v1, off, s[4:7], 0 +; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v1 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v2, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v1 +; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v0 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v6, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v7, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 +; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv24_i48: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases -; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb ; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc -; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd -; GCN-IR-NEXT: s_load_dword s7, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s8, 0xffff -; GCN-IR-NEXT: s_mov_b32 s9, 0xff000000 +; GCN-IR-NEXT: s_load_dword s7, s[0:1], 0xd +; GCN-IR-NEXT: s_load_dword s5, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s4, 0xffff +; GCN-IR-NEXT: s_mov_b32 s6, 0xff000000 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_and_b32 s1, s3, s8 -; GCN-IR-NEXT: s_and_b32 s0, s2, s9 -; GCN-IR-NEXT: s_and_b32 s3, s7, s8 -; GCN-IR-NEXT: s_and_b32 s2, s6, s9 -; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[0:1], 24 -; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[2:3], 24 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 -; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 -; GCN-IR-NEXT: s_flbit_i32_b32 s12, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7 -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] -; GCN-IR-NEXT: s_add_i32 s8, s10, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 -; GCN-IR-NEXT: s_add_i32 s9, s12, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s13 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s8 +; GCN-IR-NEXT: s_and_b32 s3, s3, s4 +; GCN-IR-NEXT: s_and_b32 s2, s2, s6 +; GCN-IR-NEXT: s_and_b32 s5, s5, s4 +; GCN-IR-NEXT: s_and_b32 s4, s7, s6 +; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[2:3], 24 +; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[4:5], 24 +; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s2 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s3 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v0, s9 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[8:9], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[10:11] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_mov_b64 vcc, vcc ; GCN-IR-NEXT: s_cbranch_vccz BB7_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB7_7 ; GCN-IR-NEXT: BB7_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB7_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB7_6 ; GCN-IR-NEXT: BB7_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[6:7], v4 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 ; GCN-IR-NEXT: s_add_u32 s6, s2, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s7, s3, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB7_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s7 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s6, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s2, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s3, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB7_5 ; GCN-IR-NEXT: BB7_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB7_7: ; %udiv-end ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 @@ -934,119 +939,120 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_udiv_k_num_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s8, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s9, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GCN-NEXT: s_sub_u32 s2, 0, s6 +; GCN-NEXT: s_subb_u32 s3, 0, s7 +; GCN-NEXT: s_mov_b32 s8, s4 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_mov_b32 s9, s5 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v6, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s8, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v8 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v2, v5 -; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v0, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v5 -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_mul_hi_u32 v8, v5, v7 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v7 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v10, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v2, v2, 24 -; GCN-NEXT: v_mul_hi_u32 v5, v3, 24 -; GCN-NEXT: v_mul_lo_u32 v3, v3, 24 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v1, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v2 -; GCN-NEXT: v_mul_lo_u32 v5, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 -; GCN-NEXT: v_add_i32_e32 v7, vcc, 2, v2 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v2 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v0, vcc -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v6 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v5, vcc, 24, v5 -; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v5 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 +; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 +; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 +; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 +; GCN-NEXT: v_mov_b32_e32 v5, s7 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s6, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v2 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 +; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc +; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s6, v3 +; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v5 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] +; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, 0, v2, vcc +; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v2 +; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v6, v5, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v11, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v2 +; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv_k_num_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 @@ -1054,72 +1060,71 @@ ; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc5, v0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 -; GCN-IR-NEXT: v_addc_u32_e64 v2, s[2:3], 0, -1, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[2:3], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3] -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 +; GCN-IR-NEXT: v_addc_u32_e64 v1, s[0:1], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB8_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB8_7 ; GCN-IR-NEXT: BB8_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[1:2] -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 63, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v1 ; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB8_6 ; GCN-IR-NEXT: BB8_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v4 ; GCN-IR-NEXT: s_add_u32 s3, s6, -1 -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s8, s7, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB8_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s8 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s3, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s3, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s6, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s7, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB8_5 ; GCN-IR-NEXT: BB8_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB8_7: ; %udiv-end ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, s2 @@ -1143,119 +1148,119 @@ ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc -; GCN-NEXT: v_mov_b32_e32 v6, 0 -; GCN-NEXT: v_mov_b32_e32 v7, 0 -; GCN-NEXT: s_mov_b32 s6, 0x8000 +; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v8, v4, v3 -; GCN-NEXT: v_mul_lo_u32 v9, v5, v2 -; GCN-NEXT: v_mul_hi_u32 v10, v4, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v2 +; GCN-NEXT: v_mul_lo_u32 v9, v4, v2 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v11 -; GCN-NEXT: v_mul_hi_u32 v12, v3, v11 -; GCN-NEXT: v_mul_lo_u32 v11, v3, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v14, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v8 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v9, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v6, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8 -; GCN-NEXT: v_addc_u32_e64 v8, vcc, v3, v9, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v10, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v9 -; GCN-NEXT: v_mul_lo_u32 v4, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v8, v11 -; GCN-NEXT: v_mul_lo_u32 v12, v8, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v11 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v6, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v10 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_mul_hi_u32 v5, v8, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v8, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v7, v10, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5] ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v2 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v7, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v2 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc +; GCN-NEXT: s_mov_b32 s4, 0x8000 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, s6, v5 -; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], 0, v3 -; GCN-NEXT: v_sub_i32_e64 v10, s[4:5], v4, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v4, v0 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[6:7] -; GCN-NEXT: v_subb_u32_e64 v5, s[6:7], v5, v1, vcc -; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v10, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[6:7] +; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 +; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v3 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s4, v4 +; GCN-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v1, vcc +; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v0 +; GCN-NEXT: v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v0 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1 +; GCN-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[4:5] +; GCN-NEXT: v_add_i32_e64 v6, s[4:5], 2, v2 +; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5] +; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 1, v2 ; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5] +; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v6, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v11, v0, vcc +; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v9, v6, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] -; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 -; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 -; GCN-IR-NEXT: s_mov_b32 s10, 0x8000 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc +; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, s6, v8 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s10 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: s_mov_b32 s8, 0x8000 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc +; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v9 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] @@ -1263,50 +1268,50 @@ ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[10:11], v2 +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[4:5] +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB9_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: s_mov_b32 s5, 0 -; GCN-IR-NEXT: s_mov_b32 s4, 0x8000 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v1, vcc +; GCN-IR-NEXT: s_mov_b32 s5, 0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x8000 ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8 +; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 +; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v10 ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_lshr_b64 v[12:13], s[4:5], v10 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v8 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9] -; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v12 -; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v5, v13, s[4:5] +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v4, v10 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v5, v11, vcc +; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 +; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0 +; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 +; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1 +; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 +; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 +; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 +; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 +; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 -; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v1 -; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v8 -; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v9, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v8, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v9, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v11, v7 -; GCN-IR-NEXT: v_mov_b32_e32 v10, v6 +; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB9_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1336,67 +1341,67 @@ ; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[4:5] ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v6 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[6:7] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB10_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB10_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7 +; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: BB10_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 +; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], v[10:11], v[0:1] -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s12, v8 -; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] -; GCN-IR-NEXT: v_subb_u32_e32 v0, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x8000, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v8, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, v9, v12, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v0, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v1, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v4 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc +; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 +; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 +; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 +; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] +; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 +; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7 +; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 +; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v11, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB10_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1418,108 +1423,108 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_udiv_k_den_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 -; GCN-NEXT: s_movk_i32 s8, 0xffe8 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_movk_i32 s2, 0xffe8 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v5, v3, s8 -; GCN-NEXT: v_mul_hi_u32 v6, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v7, v0, s8 -; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v0, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v3, v7 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v0, v5 -; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v1, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 +; GCN-NEXT: v_mul_lo_u32 v3, v1, s2 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v7, vcc -; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v5 -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v7, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v8, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v9, v5, s8 -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v7 -; GCN-NEXT: v_mul_lo_u32 v12, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v7 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v12 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v9, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v1, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v8, vcc -; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 -; GCN-NEXT: v_mul_hi_u32 v6, s3, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s3, v0 -; GCN-NEXT: v_mul_hi_u32 v7, s2, v3 -; GCN-NEXT: v_mul_lo_u32 v8, s2, v3 -; GCN-NEXT: v_mul_hi_u32 v9, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v3 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v7, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v9, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc -; GCN-NEXT: v_mul_hi_u32 v2, v0, 24 -; GCN-NEXT: v_mul_lo_u32 v3, v0, 24 -; GCN-NEXT: v_mul_lo_u32 v5, v1, 24 -; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v0 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v0 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3 -; GCN-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc -; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v3 -; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_hi_u32 v4, v0, s2 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v5, v2, s2 +; GCN-NEXT: v_mul_lo_u32 v6, v0, s2 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 +; GCN-NEXT: s_mov_b32 s5, s9 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v2, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v6 +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v10, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s10, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s11, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 +; GCN-NEXT: v_mul_hi_u32 v3, v0, 24 +; GCN-NEXT: v_mul_lo_u32 v4, v0, 24 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v4 +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, 24, v4 ; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc -; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 -; GCN-NEXT: v_cndmask_b32_e32 v2, -1, v3, vcc +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 -; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v4, vcc +; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v4 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v9, v7, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1] ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 +; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc ; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v6, vcc ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm @@ -1529,74 +1534,74 @@ ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s2, s7 -; GCN-IR-NEXT: s_add_i32 s3, s0, 32 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 59, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v2, s[2:3], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[2:3], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3] +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB11_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[2:3] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[2:3] ; GCN-IR-NEXT: s_branch BB11_7 ; GCN-IR-NEXT: BB11_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[1:2] -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 63, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v1 ; GCN-IR-NEXT: s_cbranch_vccz BB11_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB11_6 ; GCN-IR-NEXT: BB11_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[6:7], v4 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffc4, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v3 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffc4, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], 0, -1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB11_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], 23, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], 0, v9, s[0:1] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, 24, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v4 -; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[0:1], 0, v9, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v8, 24, v8 +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8 +; GCN-IR-NEXT: v_add_i32_e64 v8, s[0:1], 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e64 v9, s[0:1], 0, v5, s[0:1] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB11_5 ; GCN-IR-NEXT: BB11_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB11_7: ; %udiv-end ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 @@ -1612,165 +1617,165 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 -; GCN-NEXT: s_movk_i32 s6, 0xffe8 -; GCN-NEXT: v_mov_b32_e32 v3, 0 -; GCN-NEXT: v_mov_b32_e32 v4, 0 ; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: s_movk_i32 s6, 0xffe8 +; GCN-NEXT: v_mov_b32_e32 v10, 0 +; GCN-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v2 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_trunc_f32_e32 v3, v3 +; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v6, v5, s6 -; GCN-NEXT: v_mul_hi_u32 v7, v2, s6 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_hi_u32 v4, v2, s6 +; GCN-NEXT: v_mul_lo_u32 v5, v3, s6 +; GCN-NEXT: v_mul_lo_u32 v6, v2, s6 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_mul_hi_u32 v6, v2, s6 +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v7, v4, s6 ; GCN-NEXT: v_mul_lo_u32 v8, v2, s6 -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v2, v7 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v10, v5, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 +; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v2, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v11, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v5, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v5, v6 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v3, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v8, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v5, v7, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v8, v2, s6 -; GCN-NEXT: v_mul_lo_u32 v9, v2, s6 -; GCN-NEXT: v_mul_lo_u32 v10, v6, s6 -; GCN-NEXT: v_subrev_i32_e32 v8, vcc, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v9 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v6, v9 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v14, v6, v8 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v4, v10, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v3, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v4, v9, vcc -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v1, v2 -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v5 -; GCN-NEXT: v_mul_lo_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v1, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v4, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v10, v3, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v4, v2, 24 -; GCN-NEXT: v_mul_lo_u32 v5, v2, 24 -; GCN-NEXT: v_mul_lo_u32 v6, v3, 24 -; GCN-NEXT: v_add_i32_e32 v7, vcc, 2, v2 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, 1, v2 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v3, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v2, v8 +; GCN-NEXT: v_mul_hi_u32 v12, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v13, v4, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v10, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v12, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v9, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[4:5] +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v1, v2 +; GCN-NEXT: v_mul_hi_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v10, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 +; GCN-NEXT: v_mul_hi_u32 v5, v2, 24 +; GCN-NEXT: v_mul_lo_u32 v6, v2, 24 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc ; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v0 -; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], 23, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5] ; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v1, vcc ; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v4 ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, -1, v0, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 -; GCN-NEXT: v_cndmask_b32_e32 v1, -1, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v7, vcc +; GCN-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v2 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v3, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v2 +; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], 23, v0 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 +; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5] +; GCN-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v1, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc +; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5] ; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_udiv_k_den_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[4:5] ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v6 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[4:5] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[6:7] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB12_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v4 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffc4, v6 -; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7 -; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 +; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 -; GCN-IR-NEXT: v_or_b32_e32 v3, v1, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v0, v2 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[4:5], 23, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[4:5], 0, v9, s[4:5] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v0, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 24, v0 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v0 -; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_subbrev_u32_e64 v9, vcc, 0, v9, s[4:5] -; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v0, v4 -; GCN-IR-NEXT: v_mov_b32_e32 v1, v5 +; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6 +; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 +; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc +; GCN-IR-NEXT: v_add_i32_e64 v9, s[4:5], 1, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 +; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 +; GCN-IR-NEXT: v_addc_u32_e64 v10, s[4:5], 0, v1, s[4:5] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], v[9:10], v[0:1] +; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 +; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7 +; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 +; GCN-IR-NEXT: v_sub_i32_e32 v7, vcc, v6, v7 +; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 +; GCN-IR-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v8, vcc +; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1793,47 +1798,43 @@ ; GCN-LABEL: s_test_udiv24_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_lshr_b32 s0, s3, 8 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_lshr_b32 s2, s3, 8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-NEXT: v_mul_f32_e32 v1, s2, v1 +; GCN-NEXT: v_mul_f32_e32 v1, s4, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v2, -v1, v0, s2 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv24_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_lshr_b32 s0, s3, 8 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v1, s2, v1 +; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = lshr i64 %x, 40 %result = udiv i64 24, %x.shr @@ -1844,46 +1845,46 @@ define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_udiv24_k_den_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_lshr_b32 s0, s3, 8 +; GCN-NEXT: s_mov_b32 s6, 0x46b6fe00 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_lshr_b32 s0, s7, 8 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v0, -v1, s6, v0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s6 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv24_k_den_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_lshr_b32 s0, s3, 8 +; GCN-IR-NEXT: s_mov_b32 s6, 0x46b6fe00 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_lshr_b32 s0, s7, 8 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mad_f32 v0, -v1, s6, v0 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s6 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = lshr i64 %x, 40 %result = udiv i64 %x.shr, 23423 @@ -1896,34 +1897,34 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GCN-NEXT: v_mul_f32_e32 v1, s4, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v2, -v1, v0, s4 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_udiv24_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s4 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %x.shr = lshr i64 %x, 40 %result = udiv i64 24, %x.shr @@ -1935,34 +1936,34 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GCN-NEXT: v_mul_f32_e32 v1, s4, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v2, -v1, v0, s4 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s4 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %x.shr = lshr i64 %x, 40 %result = udiv i64 32768, %x.shr @@ -1981,16 +1982,16 @@ ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38000000, v0 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s4, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %x.shr = lshr i64 %x, 40 %result = udiv i64 %x.shr, 32768 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -1,126 +1,126 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_urem_i64: ; GCN: ; %bb.0: +; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd +; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 +; GCN-NEXT: s_sub_u32 s2, 0, s12 +; GCN-NEXT: s_subb_u32 s3, 0, s13 ; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s5, s9 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s8, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mov_b32_e32 v5, s11 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s9, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v6, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v7, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s8, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v9 -; GCN-NEXT: v_mul_lo_u32 v9, v3, v9 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 -; GCN-NEXT: v_mul_lo_u32 v11, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v0, vcc +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v6 -; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v8, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v11, s8, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v10 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v10 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v6, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v14, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v8 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v14 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v1, v11, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v13, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v1, v9, vcc -; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v7, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v6, s10, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s11, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 -; GCN-NEXT: v_mul_hi_u32 v8, s10, v3 -; GCN-NEXT: v_mul_lo_u32 v9, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v10, s11, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 +; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v8, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v1, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_sub_i32_e32 v1, vcc, s11, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s10, v2 -; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subb_u32_e32 v0, vcc, v5, v0, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s13 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s12, v4 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 ; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v2 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0 -; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v3, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; @@ -129,103 +129,103 @@ ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s0, s2 -; GCN-IR-NEXT: s_add_i32 s11, s0, 32 -; GCN-IR-NEXT: s_flbit_i32_b32 s12, s3 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 -; GCN-IR-NEXT: s_flbit_i32_b32 s13, s7 -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] -; GCN-IR-NEXT: v_mov_b32_e32 v0, s12 -; GCN-IR-NEXT: s_add_i32 s8, s10, 32 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s13 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s11 +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 +; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 +; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], s[8:9] +; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 +; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 +; GCN-IR-NEXT: s_add_i32 s10, s10, 32 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v0, s8 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, v1, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v3, s[8:9], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[2:3] -; GCN-IR-NEXT: s_or_b64 s[8:9], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] +; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB0_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB0_7 ; GCN-IR-NEXT: BB0_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[2:3] -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[6:7], v4 +; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: s_add_u32 s8, s2, -1 -; GCN-IR-NEXT: v_not_b32_e32 v1, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s9, s3, -1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v1, v0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s9 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s8, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s9 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s8, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s2, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s3, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB0_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s10, -1 -; GCN-IR-NEXT: s_mov_b32 s8, s4 -; GCN-IR-NEXT: s_mov_b32 s9, s5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s3, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v4, s7 +; GCN-IR-NEXT: s_mov_b32 s11, 0xf000 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc +; GCN-IR-NEXT: s_mov_b32 s10, -1 +; GCN-IR-NEXT: s_mov_b32 s8, s4 +; GCN-IR-NEXT: s_mov_b32 s9, s5 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-IR-NEXT: s_endpgm %result = urem i64 %x, %y @@ -241,109 +241,109 @@ ; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc -; GCN-NEXT: v_mov_b32_e32 v8, 0 -; GCN-NEXT: v_mov_b32_e32 v9, 0 +; GCN-NEXT: v_mov_b32_e32 v14, 0 ; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GCN-NEXT: v_rcp_f32_e32 v4, v4 +; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 ; GCN-NEXT: v_trunc_f32_e32 v5, v5 ; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GCN-NEXT: v_mul_lo_u32 v10, v6, v5 -; GCN-NEXT: v_mul_lo_u32 v11, v7, v4 -; GCN-NEXT: v_mul_hi_u32 v12, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v4 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v12, v10 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v13 -; GCN-NEXT: v_mul_hi_u32 v14, v5, v13 -; GCN-NEXT: v_mul_lo_u32 v13, v5, v13 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v4, v10 -; GCN-NEXT: v_mul_lo_u32 v15, v4, v10 -; GCN-NEXT: v_mul_hi_u32 v16, v5, v10 -; GCN-NEXT: v_mul_lo_u32 v10, v5, v10 -; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v15 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v11, vcc -; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v11, v14, vcc -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v16, v8, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v9, v12, vcc -; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v10 -; GCN-NEXT: v_addc_u32_e64 v10, vcc, v5, v11, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v12, v6, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v7, v4 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 +; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 -; GCN-NEXT: v_mul_lo_u32 v13, v6, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v11 -; GCN-NEXT: v_mul_lo_u32 v6, v6, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v10, v13 -; GCN-NEXT: v_mul_lo_u32 v14, v10, v13 -; GCN-NEXT: v_mul_hi_u32 v13, v4, v13 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 +; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v8, v6 +; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12 +; GCN-NEXT: v_mul_hi_u32 v10, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc +; GCN-NEXT: v_mul_lo_u32 v7, v8, v7 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v12 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_mul_hi_u32 v7, v10, v6 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v6 -; GCN-NEXT: v_mul_lo_u32 v15, v4, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v10, v6 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v15 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v12, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v14, v10 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v12, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v8, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc -; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v5 -; GCN-NEXT: v_mul_lo_u32 v11, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v12, v1, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v11 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v9, v10, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v8, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v6, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v5 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc +; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2 +; GCN-NEXT: v_subb_u32_e64 v7, s[6:7], v4, v3, s[4:5] +; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5] ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v6, vcc, v0, v2 -; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v3, vcc -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v2, vcc, v6, v2 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v3 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v3 -; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3 -; GCN-NEXT: v_cndmask_b32_e32 v3, v10, v8, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v2 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v3 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[4:5] +; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v6, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 +; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc +; GCN-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v8 +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 +; GCN-NEXT: v_subbrev_u32_e64 v2, s[4:5], 0, v7, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[6:7] +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v2, s[6:7] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_urem_i64: @@ -352,75 +352,75 @@ ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2 -; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v6, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v7, v1 -; GCN-IR-NEXT: s_or_b64 s[6:7], vcc, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 32, v6 -; GCN-IR-NEXT: v_mov_b32_e32 v11, v10 +; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 -; GCN-IR-NEXT: v_cndmask_b32_e32 v13, v5, v4, vcc +; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc +; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 +; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 -; GCN-IR-NEXT: v_cndmask_b32_e32 v12, v7, v6, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v13, v12 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[4:5], 63, v[4:5] -; GCN-IR-NEXT: s_or_b64 s[6:7], s[6:7], vcc -; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[6:7] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[6:7], -1 -; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[6:7] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[4:5] +; GCN-IR-NEXT: v_cndmask_b32_e32 v12, v5, v4, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, v10, v12 +; GCN-IR-NEXT: v_subb_u32_e64 v6, s[6:7], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6] +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 +; GCN-IR-NEXT: v_mov_b32_e32 v13, v11 +; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5] +; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 63, v4 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[6:7], v[4:5] -; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v8 +; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v5 +; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v6, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v5 +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[5:6] ; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 +; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB1_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v6 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, -1, v2 +; GCN-IR-NEXT: v_lshr_b64 v[14:15], v[0:1], v7 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, -1, v3, vcc -; GCN-IR-NEXT: v_not_b32_e32 v8, v13 -; GCN-IR-NEXT: v_not_b32_e32 v9, v10 +; GCN-IR-NEXT: v_not_b32_e32 v8, v10 +; GCN-IR-NEXT: v_not_b32_e32 v9, v11 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, v8, v12 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, v9, v11, vcc +; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, v9, v13, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: BB1_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: v_lshl_b64 v[14:15], v[14:15], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v8, 31, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 -; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, v6, v14 +; GCN-IR-NEXT: v_subb_u32_e32 v8, vcc, v7, v15, vcc ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v8 +; GCN-IR-NEXT: v_and_b32_e32 v17, v12, v2 +; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v12 +; GCN-IR-NEXT: v_and_b32_e32 v16, v12, v3 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v10 +; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v11, vcc -; GCN-IR-NEXT: v_or_b32_e32 v14, v14, v8 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[10:11] -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v14 -; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v7, v15, s[4:5] -; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v8 -; GCN-IR-NEXT: v_and_b32_e32 v8, 1, v10 -; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v3 -; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v2 -; GCN-IR-NEXT: v_sub_i32_e32 v14, vcc, v14, v10 -; GCN-IR-NEXT: v_subb_u32_e32 v15, vcc, v15, v11, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v10, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v14, s[4:5], v14, v17 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v9 +; GCN-IR-NEXT: v_subb_u32_e64 v15, s[4:5], v15, v16, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v12, v8 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB1_3 @@ -430,15 +430,15 @@ ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_or_b32_e32 v7, v9, v5 -; GCN-IR-NEXT: v_or_b32_e32 v6, v8, v4 +; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4 ; GCN-IR-NEXT: BB1_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_mul_lo_u32 v4, v2, v7 -; GCN-IR-NEXT: v_mul_hi_u32 v5, v2, v6 -; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6 -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-IR-NEXT: v_mul_lo_u32 v5, v2, v7 +; GCN-IR-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] @@ -449,55 +449,53 @@ define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_urem31_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_lshr_b32 s4, s7, 1 -; GCN-NEXT: s_lshr_b32 s5, s8, 1 +; GCN-NEXT: s_lshr_b32 s4, s2, 1 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_lshr_b32 s5, s3, 1 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s5 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 +; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem31_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_lshr_b32 s4, s7, 1 -; GCN-IR-NEXT: s_lshr_b32 s5, s8, 1 +; GCN-IR-NEXT: s_lshr_b32 s4, s2, 1 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_lshr_b32 s5, s3, 1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s5 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 +; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 33 @@ -510,86 +508,86 @@ define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { ; GCN-LABEL: s_test_urem31_v2i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x11 -; GCN-NEXT: s_mov_b32 s15, 0xf000 -; GCN-NEXT: s_mov_b32 s14, -1 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: s_brev_b32 s0, -2 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s1, s7, 1 -; GCN-NEXT: s_lshr_b32 s2, s5, 1 -; GCN-NEXT: s_lshr_b32 s3, s11, 1 -; GCN-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-NEXT: s_lshr_b32 s0, s1, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2 +; GCN-NEXT: s_lshr_b32 s3, s3, 1 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, s3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-NEXT: v_mul_f32_e32 v5, v0, v5 -; GCN-NEXT: v_mul_f32_e32 v6, v3, v6 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_trunc_f32_e32 v6, v6 -; GCN-NEXT: v_mad_f32 v0, -v5, v2, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-NEXT: v_mad_f32 v3, -v6, v4, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_lshr_b32 s1, s11, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: v_mul_f32_e32 v2, v3, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 +; GCN-NEXT: v_mad_f32 v2, -v2, v4, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_brev_b32 s0, -2 ; GCN-NEXT: v_and_b32_e32 v0, s0, v0 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GCN-NEXT: v_and_b32_e32 v2, s0, v2 ; GCN-NEXT: v_mov_b32_e32 v3, v1 -; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem31_v2i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x11 -; GCN-IR-NEXT: s_mov_b32 s15, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s14, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: s_brev_b32 s0, -2 +; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s1, s7, 1 -; GCN-IR-NEXT: s_lshr_b32 s2, s5, 1 -; GCN-IR-NEXT: s_lshr_b32 s3, s11, 1 -; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-IR-NEXT: s_lshr_b32 s0, s1, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2 +; GCN-IR-NEXT: s_lshr_b32 s3, s3, 1 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s3 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v5, v2 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-IR-NEXT: v_mul_f32_e32 v5, v0, v5 -; GCN-IR-NEXT: v_mul_f32_e32 v6, v3, v6 -; GCN-IR-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-IR-NEXT: v_trunc_f32_e32 v6, v6 -; GCN-IR-NEXT: v_mad_f32 v0, -v5, v2, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-IR-NEXT: v_mad_f32 v3, -v6, v4, v3 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_lshr_b32 s1, s11, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 +; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v3 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 +; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: s_brev_b32 s0, -2 ; GCN-IR-NEXT: v_and_b32_e32 v0, s0, v0 +; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, s0, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 -; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 +; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr <2 x i64> %x, %2 = lshr <2 x i64> %y, @@ -601,55 +599,53 @@ define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_urem24_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_lshr_b32 s4, s7, 8 -; GCN-NEXT: s_lshr_b32 s5, s8, 8 +; GCN-NEXT: s_lshr_b32 s4, s2, 8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_lshr_b32 s5, s3, 8 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s5 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem24_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_lshr_b32 s4, s7, 8 -; GCN-IR-NEXT: s_lshr_b32 s5, s8, 8 +; GCN-IR-NEXT: s_lshr_b32 s4, s2, 8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_lshr_b32 s5, s3, 8 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v0, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s5 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s4, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 40 @@ -662,86 +658,86 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) { ; GCN-LABEL: s_test_urem23_64_v2i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x11 -; GCN-NEXT: s_mov_b32 s15, 0xf000 -; GCN-NEXT: s_mov_b32 s14, -1 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: s_brev_b32 s0, -2 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s1, s7, 9 -; GCN-NEXT: s_lshr_b32 s2, s5, 1 -; GCN-NEXT: s_lshr_b32 s3, s11, 9 -; GCN-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-NEXT: s_lshr_b32 s0, s1, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2 +; GCN-NEXT: s_lshr_b32 s3, s3, 9 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, s3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v5, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-NEXT: v_mul_f32_e32 v5, v0, v5 -; GCN-NEXT: v_mul_f32_e32 v6, v3, v6 -; GCN-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-NEXT: v_trunc_f32_e32 v6, v6 -; GCN-NEXT: v_mad_f32 v0, -v5, v2, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-NEXT: v_mad_f32 v3, -v6, v4, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: s_lshr_b32 s1, s11, 9 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 +; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: v_mul_f32_e32 v2, v3, v2 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 +; GCN-NEXT: v_mad_f32 v2, -v2, v4, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_brev_b32 s0, -2 ; GCN-NEXT: v_and_b32_e32 v0, s0, v0 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GCN-NEXT: v_and_b32_e32 v2, s0, v2 ; GCN-NEXT: v_mov_b32_e32 v3, v1 -; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 +; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem23_64_v2i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd -; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x11 -; GCN-IR-NEXT: s_mov_b32 s15, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s14, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: s_brev_b32 s0, -2 +; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xd +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x11 +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s1, s7, 9 -; GCN-IR-NEXT: s_lshr_b32 s2, s5, 1 -; GCN-IR-NEXT: s_lshr_b32 s3, s11, 9 -; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-IR-NEXT: s_lshr_b32 s0, s1, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2 +; GCN-IR-NEXT: s_lshr_b32 s3, s3, 9 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s3 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v5, v2 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-IR-NEXT: v_mul_f32_e32 v5, v0, v5 -; GCN-IR-NEXT: v_mul_f32_e32 v6, v3, v6 -; GCN-IR-NEXT: v_trunc_f32_e32 v5, v5 -; GCN-IR-NEXT: v_trunc_f32_e32 v6, v6 -; GCN-IR-NEXT: v_mad_f32 v0, -v5, v2, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GCN-IR-NEXT: v_mad_f32 v3, -v6, v4, v3 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v2 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: s_lshr_b32 s1, s11, 9 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v3, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2 +; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v6, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v2, v3, v2 +; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v5, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 +; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v3 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 +; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s3 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: s_brev_b32 s0, -2 ; GCN-IR-NEXT: v_and_b32_e32 v0, s0, v0 +; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s1, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, s0, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 -; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[12:15], 0 +; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr <2 x i64> %x, %2 = lshr <2 x i64> %y, @@ -753,118 +749,119 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_urem_k_num_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s3 -; GCN-NEXT: s_sub_u32 s8, 0, s2 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GCN-NEXT: s_subb_u32 s9, 0, s3 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GCN-NEXT: s_sub_u32 s2, 0, s6 +; GCN-NEXT: s_subb_u32 s3, 0, s7 +; GCN-NEXT: s_mov_b32 s8, s4 +; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_mov_b32 s9, s5 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 -; GCN-NEXT: v_mul_lo_u32 v6, s9, v2 -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s8, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v8 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v2, v5 -; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v6, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v0, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v7, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[0:1], v2, v5 -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v7, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v8, s9, v2 -; GCN-NEXT: v_mul_lo_u32 v9, s8, v2 -; GCN-NEXT: v_mul_lo_u32 v10, s8, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v9 -; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 +; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 +; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc +; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 +; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 +; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc +; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_mul_hi_u32 v8, v5, v7 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v7 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v7 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v1, v10, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v12, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v1, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v2, v2, 24 -; GCN-NEXT: v_mul_hi_u32 v5, v3, 24 -; GCN-NEXT: v_mul_lo_u32 v3, v3, 24 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc -; GCN-NEXT: v_mul_hi_u32 v2, s2, v1 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v1 -; GCN-NEXT: v_mul_lo_u32 v1, s2, v1 -; GCN-NEXT: v_mul_lo_u32 v0, s2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v2, v0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v0 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v1 -; GCN-NEXT: v_subb_u32_e64 v1, s[0:1], v2, v4, vcc -; GCN-NEXT: v_subb_u32_e32 v0, vcc, 0, v0, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v5, vcc, s2, v3 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v1, v4, vcc -; GCN-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, s2, v5 -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v0 -; GCN-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v1, v0, v1, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v0, v3, v0, s[0:1] -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 +; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 +; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v1, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s6, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s7, v0 +; GCN-NEXT: v_mul_lo_u32 v0, s6, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1 +; GCN-NEXT: v_mov_b32_e32 v3, s7 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 +; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s6, v0 +; GCN-NEXT: v_subb_u32_e64 v3, s[2:3], v2, v3, s[0:1] +; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v4 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v2 +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] +; GCN-NEXT: v_subrev_i32_e64 v6, s[0:1], s6, v4 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 +; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GCN-NEXT: v_cndmask_b32_e64 v2, v4, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem_k_num_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 ; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 @@ -872,83 +869,82 @@ ; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 0xffffffc5, v0 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 -; GCN-IR-NEXT: v_addc_u32_e64 v2, s[2:3], 0, -1, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[2:3], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3] -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 +; GCN-IR-NEXT: v_addc_u32_e64 v1, s[0:1], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB6_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[8:9] ; GCN-IR-NEXT: s_branch BB6_7 ; GCN-IR-NEXT: BB6_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[1:2] -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 63, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], 24, v1 ; GCN-IR-NEXT: s_cbranch_vccz BB6_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB6_6 ; GCN-IR-NEXT: BB6_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], 24, v4 ; GCN-IR-NEXT: s_add_u32 s3, s6, -1 -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: s_addc_u32 s8, s7, -1 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB6_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v12, s8 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], s3, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], v12, v9, s[0:1] +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 +; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s3, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 +; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v5, s6, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, s7, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[0:1], v9, v4, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB6_5 ; GCN-IR-NEXT: BB6_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB6_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v3, s7, v0 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s6, v0 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_mov_b32 s1, s5 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm @@ -960,108 +956,108 @@ define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_urem_k_den_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 -; GCN-NEXT: s_movk_i32 s8, 0xffe8 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: s_movk_i32 s2, 0xffe8 +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v5, v3, s8 -; GCN-NEXT: v_mul_hi_u32 v6, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v7, v0, s8 -; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v0, v6 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 -; GCN-NEXT: v_mul_lo_u32 v7, v3, v7 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v0, v5 -; GCN-NEXT: v_mul_lo_u32 v10, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v1, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s11, 0xf000 +; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 +; GCN-NEXT: v_mul_lo_u32 v3, v1, s2 +; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 +; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v7, vcc -; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v5 -; GCN-NEXT: v_addc_u32_e64 v5, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_mul_hi_u32 v7, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v8, v0, s8 -; GCN-NEXT: v_mul_lo_u32 v9, v5, s8 -; GCN-NEXT: v_subrev_i32_e32 v7, vcc, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v8 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v7 -; GCN-NEXT: v_mul_lo_u32 v12, v0, v7 -; GCN-NEXT: v_mul_hi_u32 v13, v5, v7 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v7 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v12 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v9, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v11, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v1, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v8, vcc -; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 -; GCN-NEXT: v_mul_hi_u32 v6, s3, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s3, v0 -; GCN-NEXT: v_mul_hi_u32 v7, s2, v3 -; GCN-NEXT: v_mul_lo_u32 v8, s2, v3 -; GCN-NEXT: v_mul_hi_u32 v9, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v3 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v7, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v5 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v9, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s8, s4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_hi_u32 v4, v0, s2 +; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] +; GCN-NEXT: v_mul_lo_u32 v5, v2, s2 +; GCN-NEXT: v_mul_lo_u32 v6, v0, s2 +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 +; GCN-NEXT: s_mov_b32 s9, s5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v11, v2, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc +; GCN-NEXT: v_mul_lo_u32 v10, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v6 +; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v10, v5 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s6, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s7, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s7, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s7, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GCN-NEXT: v_mul_hi_u32 v2, v0, 24 -; GCN-NEXT: v_mul_lo_u32 v0, v0, 24 ; GCN-NEXT: v_mul_lo_u32 v1, v1, 24 +; GCN-NEXT: v_mul_lo_u32 v0, v0, 24 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s7 +; GCN-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, 24, v0 -; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v0 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v1, vcc -; GCN-NEXT: v_subrev_i32_e32 v5, vcc, 24, v2 -; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v2 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1 -; GCN-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[0:1] -; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GCN-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v1, vcc +; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v2 +; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc +; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v2 +; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; GCN-NEXT: v_cndmask_b32_e32 v6, -1, v6, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc +; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v0 +; GCN-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v1 +; GCN-NEXT: v_cndmask_b32_e64 v5, -1, v5, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] ; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem_k_den_i64: @@ -1069,86 +1065,86 @@ ; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_flbit_i32_b32 s0, s6 -; GCN-IR-NEXT: s_flbit_i32_b32 s2, s7 -; GCN-IR-NEXT: s_add_i32 s3, s0, 32 -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s2 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s3 +; GCN-IR-NEXT: s_flbit_i32_b32 s1, s7 +; GCN-IR-NEXT: s_add_i32 s0, s0, 32 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s1 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s0 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 -; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 59, v0 -; GCN-IR-NEXT: v_subb_u32_e64 v2, s[2:3], 0, 0, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 63, v[1:2] -; GCN-IR-NEXT: s_or_b64 s[2:3], s[0:1], vcc -; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3] +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2 +; GCN-IR-NEXT: v_subb_u32_e64 v1, s[0:1], 0, 0, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[2:3], s[6:7], 0 +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], 63, v[0:1] +; GCN-IR-NEXT: s_or_b64 s[2:3], s[2:3], vcc +; GCN-IR-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_cbranch_vccz BB7_2 ; GCN-IR-NEXT: ; %bb.1: ; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 -; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[2:3] ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 -; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] +; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[2:3] ; GCN-IR-NEXT: s_branch BB7_7 ; GCN-IR-NEXT: BB7_2: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[1:2] -; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, 63, v1 +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 +; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[6:7], v1 ; GCN-IR-NEXT: s_cbranch_vccz BB7_4 ; GCN-IR-NEXT: ; %bb.3: -; GCN-IR-NEXT: v_mov_b32_e32 v0, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: s_branch BB7_6 ; GCN-IR-NEXT: BB7_4: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[6:7], v4 -; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffc4, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v3 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffc4, v2 +; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], 0, -1, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: BB7_5: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 -; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v3 -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v4 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v5, vcc -; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 -; GCN-IR-NEXT: v_or_b32_e32 v3, v7, v3 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5] -; GCN-IR-NEXT: v_sub_i32_e64 v0, s[0:1], 23, v8 -; GCN-IR-NEXT: v_subb_u32_e64 v0, s[0:1], 0, v9, s[0:1] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v4, 31, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 1, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, 24, v4 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[0:1], v8, v4 -; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc -; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[0:1], 0, v9, s[0:1] -; GCN-IR-NEXT: v_mov_b32_e32 v4, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v5, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v1 -; GCN-IR-NEXT: v_mov_b32_e32 v6, v0 +; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 +; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 +; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6 +; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 +; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 +; GCN-IR-NEXT: v_and_b32_e32 v8, 24, v8 +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v6, v8 +; GCN-IR-NEXT: v_add_i32_e64 v8, s[0:1], 1, v4 +; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 +; GCN-IR-NEXT: v_addc_u32_e64 v9, s[0:1], 0, v5, s[0:1] +; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[8:9], v[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 +; GCN-IR-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 +; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] +; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: s_cbranch_vccz BB7_5 ; GCN-IR-NEXT: BB7_6: ; %udiv-loop-exit -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v0, v0, v2 -; GCN-IR-NEXT: v_or_b32_e32 v1, v1, v3 +; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 +; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 +; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: BB7_7: ; %udiv-end -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, 24 ; GCN-IR-NEXT: v_mul_hi_u32 v2, v0, 24 +; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, 24 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, 24 -; GCN-IR-NEXT: v_mov_b32_e32 v3, s7 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 -; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v3, v1, vcc +; GCN-IR-NEXT: s_mov_b32 s0, s4 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %result = urem i64 %x, 24 @@ -1170,60 +1166,59 @@ ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc -; GCN-NEXT: v_mov_b32_e32 v6, 0 -; GCN-NEXT: v_mov_b32_e32 v7, 0 -; GCN-NEXT: s_mov_b32 s6, 0x8000 +; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 +; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; GCN-NEXT: v_trunc_f32_e32 v3, v3 ; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v8, v4, v3 -; GCN-NEXT: v_mul_lo_u32 v9, v5, v2 -; GCN-NEXT: v_mul_hi_u32 v10, v4, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v8, v5, v2 +; GCN-NEXT: v_mul_lo_u32 v9, v4, v2 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 +; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v11 -; GCN-NEXT: v_mul_hi_u32 v12, v3, v11 -; GCN-NEXT: v_mul_lo_u32 v11, v3, v11 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v8 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v8 -; GCN-NEXT: v_mul_hi_u32 v14, v3, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v8 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v13 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v9, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v6, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc -; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v8 -; GCN-NEXT: v_addc_u32_e64 v8, vcc, v3, v9, s[4:5] -; GCN-NEXT: v_mul_hi_u32 v10, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 +; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] +; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v9 -; GCN-NEXT: v_mul_lo_u32 v4, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v8, v11 -; GCN-NEXT: v_mul_lo_u32 v12, v8, v11 -; GCN-NEXT: v_mul_hi_u32 v11, v2, v11 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 +; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v6, v4 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10 +; GCN-NEXT: v_mul_hi_u32 v8, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc +; GCN-NEXT: v_mul_lo_u32 v5, v6, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v10 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_mul_hi_u32 v5, v8, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v13, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v8, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v11, v13 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v7, v10, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v12, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5] ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc @@ -1231,69 +1226,70 @@ ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 +; GCN-NEXT: s_mov_b32 s4, 0x8000 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-NEXT: v_sub_i32_e64 v4, s[4:5], 0, v3 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v0 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5] +; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v2 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc -; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_sub_i32_e32 v6, vcc, v2, v0 -; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v4, v1, vcc -; GCN-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v6, v0 -; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GCN-NEXT: v_sub_i32_e32 v0, vcc, v6, v0 -; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] +; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0 +; GCN-NEXT: v_subb_u32_e64 v6, s[6:7], v4, v1, s[4:5] +; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5] ; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v4, v1 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[4:5] -; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[4:5] -; GCN-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v7, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v10, v8, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 -; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5] -; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v7, vcc -; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v0 +; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc +; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] +; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v4, v1 +; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[4:5] +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 +; GCN-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, v7 +; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 +; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0 +; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc +; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1 +; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc +; GCN-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v6, s[4:5] +; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[6:7] +; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; GCN-NEXT: v_cndmask_b32_e64 v1, v4, v1, s[6:7] +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] -; GCN-IR-NEXT: s_mov_b32 s11, 0 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 -; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 -; GCN-IR-NEXT: s_mov_b32 s10, 0x8000 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v3, v2, vcc -; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, s6, v8 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v2, s10 -; GCN-IR-NEXT: v_addc_u32_e64 v4, s[6:7], 0, -1, vcc -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[3:4] +; GCN-IR-NEXT: s_movk_i32 s6, 0xffd0 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, s6, v8 +; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc +; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3] +; GCN-IR-NEXT: s_mov_b32 s8, 0x8000 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc -; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] +; GCN-IR-NEXT: v_mov_b32_e32 v4, s8 +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] +; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 +; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 -; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[3:4] +; GCN-IR-NEXT: s_mov_b32 s9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB8_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v3 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v4, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 63, v3 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 -; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[10:11], v[3:4] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[10:11], v2 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc +; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[4:5], v[2:3] +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] @@ -1301,38 +1297,38 @@ ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: s_mov_b32 s5, 0 ; GCN-IR-NEXT: s_mov_b32 s4, 0x8000 +; GCN-IR-NEXT: v_lshr_b64 v[10:11], s[4:5], v4 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, -1, v0 ; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, -1, v1, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, 47, v8 +; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_subb_u32_e32 v9, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_lshr_b64 v[12:13], s[4:5], v10 -; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: BB8_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 +; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 -; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v8 -; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v9, vcc -; GCN-IR-NEXT: v_or_b32_e32 v12, v12, v6 -; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9] -; GCN-IR-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v12 -; GCN-IR-NEXT: v_subb_u32_e64 v6, s[4:5], v5, v13, s[4:5] +; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v4, v10 +; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v5, v11, vcc +; GCN-IR-NEXT: v_or_b32_e32 v2, v12, v2 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 +; GCN-IR-NEXT: v_and_b32_e32 v15, v12, v0 +; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 +; GCN-IR-NEXT: v_and_b32_e32 v14, v12, v1 +; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 +; GCN-IR-NEXT: v_or_b32_e32 v3, v13, v3 +; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 +; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15 +; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 +; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 +; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] -; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8 -; GCN-IR-NEXT: v_and_b32_e32 v9, v8, v1 -; GCN-IR-NEXT: v_and_b32_e32 v8, v8, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v12, vcc, v12, v8 -; GCN-IR-NEXT: v_subb_u32_e32 v13, vcc, v13, v9, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v8, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v9, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v11, v7 -; GCN-IR-NEXT: v_mov_b32_e32 v10, v6 +; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB8_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1341,16 +1337,16 @@ ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_or_b32_e32 v5, v7, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v6, v2 +; GCN-IR-NEXT: v_or_b32_e32 v4, v6, v2 ; GCN-IR-NEXT: BB8_6: ; %Flow4 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] -; GCN-IR-NEXT: v_mul_lo_u32 v3, v0, v5 -; GCN-IR-NEXT: v_mul_hi_u32 v4, v0, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v2 -; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v4, v3 +; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5 +; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 -; GCN-IR-NEXT: v_add_i32_e64 v1, s[4:5], v2, v1 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %result = urem i64 32768, %x @@ -1368,67 +1364,67 @@ ; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64: ; GCN-IR: ; %bb.0: ; %_udiv-special-cases ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 -; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 +; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 ; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[4:5] ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v6 ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5] +; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3] -; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[2:3] ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3] +; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5] -; GCN-IR-NEXT: s_xor_b64 s[8:9], s[4:5], -1 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5] -; GCN-IR-NEXT: s_and_b64 s[4:5], s[8:9], s[6:7] +; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB9_6 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v2 ; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 63, v2 -; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3] -; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v4 +; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 +; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 +; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_cbranch_execz BB9_5 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader -; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v7 +; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 +; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6 -; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 -; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc +; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 -; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 +; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 -; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 +; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 -; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6 -; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc -; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v4 -; GCN-IR-NEXT: v_or_b32_e32 v3, v9, v3 -; GCN-IR-NEXT: v_or_b32_e32 v2, v8, v2 -; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], v[12:13], v[6:7] -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v10 -; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9] -; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v11, vcc -; GCN-IR-NEXT: v_ashrrev_i32_e32 v6, 31, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v6 -; GCN-IR-NEXT: v_and_b32_e32 v6, 0x8000, v6 -; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, v10, v6 -; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, v11, v14, vcc -; GCN-IR-NEXT: v_mov_b32_e32 v6, v12 -; GCN-IR-NEXT: v_mov_b32_e32 v7, v13 -; GCN-IR-NEXT: v_mov_b32_e32 v9, v5 -; GCN-IR-NEXT: v_mov_b32_e32 v8, v4 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8 +; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc +; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 +; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v10 +; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 +; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 +; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 +; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc +; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] +; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 +; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 +; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 +; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 +; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 +; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v12 +; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v13, s[4:5] +; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] +; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_cbranch_execnz BB9_3 ; GCN-IR-NEXT: ; %bb.4: ; %Flow @@ -1452,51 +1448,47 @@ ; GCN-LABEL: s_test_urem24_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_mov_b32 s5, 0x41c00000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_lshr_b32 s0, s3, 8 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_lshr_b32 s4, s3, 8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-NEXT: v_mul_f32_e32 v1, s2, v1 +; GCN-NEXT: v_mul_f32_e32 v1, s5, v1 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v2, -v1, v0, s2 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v1, -v1, v0, s5 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem24_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_mov_b32 s5, 0x41c00000 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, 0x41c00000 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_lshr_b32 s0, s3, 8 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_lshr_b32 s4, s3, 8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v1, s2, v1 +; GCN-IR-NEXT: v_mul_f32_e32 v1, s5, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v2, -v1, v0, s2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s5 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = lshr i64 %x, 40 %result = urem i64 24, %x.shr @@ -1507,52 +1499,52 @@ define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { ; GCN-LABEL: s_test_urem24_k_den_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: s_mov_b32 s8, 0x46b6fe00 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-NEXT: s_mov_b32 s1, 0x46b6fe00 +; GCN-NEXT: s_movk_i32 s0, 0x5b7f +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_movk_i32 s2, 0x5b7f -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_lshr_b32 s0, s3, 8 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-NEXT: s_lshr_b32 s6, s7, 8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-NEXT: v_mad_f32 v0, -v1, s8, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s8 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-NEXT: v_mad_f32 v0, -v1, s1, v0 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s1 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 +; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem24_k_den_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s6, -1 -; GCN-IR-NEXT: s_mov_b32 s8, 0x46b6fe00 +; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GCN-IR-NEXT: s_mov_b32 s1, 0x46b6fe00 +; GCN-IR-NEXT: s_movk_i32 s0, 0x5b7f +; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s2, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_movk_i32 s2, 0x5b7f -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_lshr_b32 s0, s3, 8 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GCN-IR-NEXT: s_lshr_b32 s6, s7, 8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 -; GCN-IR-NEXT: v_mad_f32 v0, -v1, s8, v0 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s8 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s2 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 +; GCN-IR-NEXT: v_mad_f32 v0, -v1, s1, v0 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s1 +; GCN-IR-NEXT: s_mov_b32 s1, s5 +; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s0 +; GCN-IR-NEXT: s_mov_b32 s0, s4 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s6, v0 +; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %x.shr = lshr i64 %x, 40 %result = urem i64 %x.shr, 23423 @@ -1565,38 +1557,38 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0 +; GCN-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_urem24_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %x.shr = lshr i64 %x, 40 %result = urem i64 24, %x.shr @@ -1608,38 +1600,38 @@ ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0 +; GCN-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v3, -v2, v1, s4 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; ; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64: ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1 ; GCN-IR-NEXT: v_mul_f32_e32 v2, s4, v2 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v3, -v2, v1, s4 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v1 -; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 +; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4 +; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1 +; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %x.shr = lshr i64 %x, 40 %result = urem i64 32768, %x.shr @@ -1658,14 +1650,14 @@ ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 -; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0 +; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4 -; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc ; GCN-IR-NEXT: v_lshlrev_b32_e32 v1, 15, v1 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 diff --git a/llvm/test/CodeGen/AMDGPU/v_mac.ll b/llvm/test/CodeGen/AMDGPU/v_mac.ll --- a/llvm/test/CodeGen/AMDGPU/v_mac.ll +++ b/llvm/test/CodeGen/AMDGPU/v_mac.ll @@ -1,4 +1,4 @@ -; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-FLUSH -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=+fp64-fp16-denormals,-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-DENORM -check-prefix=GCN %s