Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -594,7 +594,6 @@
     .widenScalarToNextPow2(0, 32)
     .widenScalarToNextPow2(1, 32);
 
-  // TODO: Expand for > s32
   getActionDefinitionsBuilder({G_BSWAP, G_BITREVERSE})
     .legalFor({S32})
     .clampScalar(0, S32, S32)
Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -3164,6 +3164,7 @@
   case AMDGPU::G_FMAXNUM_IEEE:
   case AMDGPU::G_FCANONICALIZE:
   case AMDGPU::G_INTRINSIC_TRUNC:
+  case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar?
   case AMDGPU::G_AMDGPU_FFBH_U32:
   case AMDGPU::G_AMDGPU_FMIN_LEGACY:
   case AMDGPU::G_AMDGPU_FMAX_LEGACY:
@@ -3250,7 +3251,6 @@
   case AMDGPU::G_BITCAST:
   case AMDGPU::G_INTTOPTR:
   case AMDGPU::G_PTRTOINT:
-  case AMDGPU::G_BSWAP:
   case AMDGPU::G_BITREVERSE:
   case AMDGPU::G_FABS:
   case AMDGPU::G_FNEG: {
Index: llvm/lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstructions.td
+++ llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1782,8 +1782,8 @@
 def : GCNPat <
   (i32 (bswap i32:$a)),
   (V_BFI_B32 (S_MOV_B32 (i32 0x00ff00ff)),
-             (V_ALIGNBIT_B32 $a, $a, (i32 24)),
-             (V_ALIGNBIT_B32 $a, $a, (i32 8)))
+             (V_ALIGNBIT_B32 VSrc_b32:$a, VSrc_b32:$a, (i32 24)),
+             (V_ALIGNBIT_B32 VSrc_b32:$a, VSrc_b32:$a, (i32 8)))
 >;
 
 // FIXME: This should have been narrowed to i32 during legalization.
@@ -1809,8 +1809,9 @@
   sub1)
 >;
 
-
-let SubtargetPredicate = isGFX8Plus in {
+// FIXME: The AddedComplexity should not be needed, but in GlobalISel
+// the BFI pattern ends up taking precedence without it.
+let SubtargetPredicate = isGFX8Plus, AddedComplexity = 1 in {
 // Magic number: 3 | (2 << 8) | (1 << 16) | (0 << 24)
 //
 // My reading of the manual suggests we should be using src0 for the
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -0,0 +1,526 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii -o - %s | FileCheck -check-prefix=GFX7
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9
+
+define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) {
+; GFX7-LABEL: s_bswap_i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_alignbit_b32 v0, s0, s0, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, s0, s0, 24
+; GFX7-NEXT:    s_mov_b32 s0, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s0, v1, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_bswap_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    s_mov_b32 s0, 0x10203
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_bswap_i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    s_mov_b32 s0, 0x10203
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    ; return to shader part epilog
+  %bswap = call i32 @llvm.bswap.i32(i32 %src)
+  %to.sgpr = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap)
+  ret i32 %to.sgpr
+}
+
+define i32 @v_bswap_i32(i32 %src) {
+; GFX7-LABEL: v_bswap_i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_alignbit_b32 v1, v0, v0, 8
+; GFX7-NEXT:    v_alignbit_b32 v0, v0, v0, 24
+; GFX7-NEXT:    s_mov_b32 s4, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v1
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bswap_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0x10203
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_bswap_i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s4, 0x10203
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %bswap = call i32 @llvm.bswap.i32(i32 %src)
+  ret i32 %bswap
+}
+
+define amdgpu_ps <2 x i32> @s_bswap_v2i32(<2 x i32> inreg %src) {
+; GFX7-LABEL: s_bswap_v2i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_alignbit_b32 v0, s0, s0, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, s0, s0, 24
+; GFX7-NEXT:    s_mov_b32 s0, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s0, v1, v0
+; GFX7-NEXT:    v_alignbit_b32 v1, s1, s1, 8
+; GFX7-NEXT:    v_alignbit_b32 v2, s1, s1, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s0, v2, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_bswap_v2i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    s_mov_b32 s0, 0x10203
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_perm_b32 v1, 0, v1, s0
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_bswap_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    s_mov_b32 s0, 0x10203
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_perm_b32 v1, 0, v1, s0
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+  %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
+  %bswap.0 = extractelement <2 x i32> %bswap, i32 0
+  %bswap.1 = extractelement <2 x i32> %bswap, i32 1
+  %to.sgpr0 = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap.0)
+  %to.sgpr1 = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap.1)
+  %ins.0 = insertelement <2 x i32> undef, i32 %to.sgpr0, i32 0
+  %ins.1 = insertelement <2 x i32> %ins.0, i32 %to.sgpr1, i32 1
+  ret <2 x i32> %ins.1
+}
+
+define <2 x i32> @v_bswap_v2i32(<2 x i32> %src) {
+; GFX7-LABEL: v_bswap_v2i32:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_alignbit_b32 v2, v0, v0, 8
+; GFX7-NEXT:    v_alignbit_b32 v0, v0, v0, 24
+; GFX7-NEXT:    s_mov_b32 s4, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v2
+; GFX7-NEXT:    v_alignbit_b32 v2, v1, v1, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, v1, v1, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s4, v1, v2
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bswap_v2i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0x10203
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX8-NEXT:    v_perm_b32 v1, 0, v1, s4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_bswap_v2i32:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s4, 0x10203
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX9-NEXT:    v_perm_b32 v1, 0, v1, s4
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
+  ret <2 x i32> %bswap
+}
+
+define amdgpu_ps <2 x i32> @s_bswap_i64(i64 inreg %src) {
+; GFX7-LABEL: s_bswap_i64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_alignbit_b32 v0, s1, s1, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, s1, s1, 24
+; GFX7-NEXT:    s_mov_b32 s1, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s1, v1, v0
+; GFX7-NEXT:    v_alignbit_b32 v1, s0, s0, 8
+; GFX7-NEXT:    v_alignbit_b32 v2, s0, s0, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s1, v2, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_bswap_i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s1
+; GFX8-NEXT:    s_mov_b32 s1, 0x10203
+; GFX8-NEXT:    v_mov_b32_e32 v1, s0
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s1
+; GFX8-NEXT:    v_perm_b32 v1, 0, v1, s1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_bswap_i64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    s_mov_b32 s1, 0x10203
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s1
+; GFX9-NEXT:    v_perm_b32 v1, 0, v1, s1
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    ; return to shader part epilog
+  %bswap = call i64 @llvm.bswap.i64(i64 %src)
+  %cast = bitcast i64 %bswap to <2 x i32>
+  %elt0 = extractelement <2 x i32> %cast, i32 0
+  %elt1 = extractelement <2 x i32> %cast, i32 1
+  %to.sgpr0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt0)
+  %to.sgpr1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt1)
+  %ins.0 = insertelement <2 x i32> undef, i32 %to.sgpr0, i32 0
+  %ins.1 = insertelement <2 x i32> %ins.0, i32 %to.sgpr1, i32 1
+  ret <2 x i32> %ins.1
+}
+
+define i64 @v_bswap_i64(i64 %src) {
+; GFX7-LABEL: v_bswap_i64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_alignbit_b32 v2, v1, v1, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, v1, v1, 24
+; GFX7-NEXT:    s_mov_b32 s4, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v2, s4, v1, v2
+; GFX7-NEXT:    v_alignbit_b32 v1, v0, v0, 8
+; GFX7-NEXT:    v_alignbit_b32 v0, v0, v0, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s4, v0, v1
+; GFX7-NEXT:    v_mov_b32_e32 v0, v2
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bswap_i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0x10203
+; GFX8-NEXT:    v_perm_b32 v2, 0, v1, s4
+; GFX8-NEXT:    v_perm_b32 v1, 0, v0, s4
+; GFX8-NEXT:    v_mov_b32_e32 v0, v2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_bswap_i64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s4, 0x10203
+; GFX9-NEXT:    v_perm_b32 v2, 0, v1, s4
+; GFX9-NEXT:    v_perm_b32 v1, 0, v0, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, v2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %bswap = call i64 @llvm.bswap.i64(i64 %src)
+  ret i64 %bswap
+}
+
+define amdgpu_ps <4 x i32> @s_bswap_v2i64(<2 x i64> inreg %src) {
+; GFX7-LABEL: s_bswap_v2i64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_alignbit_b32 v0, s1, s1, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, s1, s1, 24
+; GFX7-NEXT:    s_mov_b32 s1, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s1, v1, v0
+; GFX7-NEXT:    v_alignbit_b32 v1, s0, s0, 8
+; GFX7-NEXT:    v_alignbit_b32 v2, s0, s0, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s1, v2, v1
+; GFX7-NEXT:    v_alignbit_b32 v2, s3, s3, 8
+; GFX7-NEXT:    v_alignbit_b32 v3, s3, s3, 24
+; GFX7-NEXT:    v_bfi_b32 v2, s1, v3, v2
+; GFX7-NEXT:    v_alignbit_b32 v3, s2, s2, 8
+; GFX7-NEXT:    v_alignbit_b32 v4, s2, s2, 24
+; GFX7-NEXT:    v_bfi_b32 v3, s1, v4, v3
+; GFX7-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX7-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_bswap_v2i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s1
+; GFX8-NEXT:    s_mov_b32 s1, 0x10203
+; GFX8-NEXT:    v_mov_b32_e32 v1, s0
+; GFX8-NEXT:    v_mov_b32_e32 v2, s3
+; GFX8-NEXT:    v_mov_b32_e32 v3, s2
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s1
+; GFX8-NEXT:    v_perm_b32 v2, 0, v2, s1
+; GFX8-NEXT:    v_perm_b32 v3, 0, v3, s1
+; GFX8-NEXT:    v_perm_b32 v1, 0, v1, s1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_bswap_v2i64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v0, s1
+; GFX9-NEXT:    s_mov_b32 s1, 0x10203
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NEXT:    v_mov_b32_e32 v2, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s1
+; GFX9-NEXT:    v_perm_b32 v2, 0, v2, s1
+; GFX9-NEXT:    v_perm_b32 v3, 0, v3, s1
+; GFX9-NEXT:    v_perm_b32 v1, 0, v1, s1
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX9-NEXT:    v_readfirstlane_b32 s2, v2
+; GFX9-NEXT:    v_readfirstlane_b32 s3, v3
+; GFX9-NEXT:    ; return to shader part epilog
+  %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
+  %cast = bitcast <2 x i64> %bswap to <4 x i32>
+  %bswap.0 = extractelement <4 x i32> %cast, i32 0
+  %bswap.1 = extractelement <4 x i32> %cast, i32 1
+  %bswap.2 = extractelement <4 x i32> %cast, i32 2
+  %bswap.3 = extractelement <4 x i32> %cast, i32 3
+  %to.sgpr0 = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap.0)
+  %to.sgpr1 = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap.1)
+  %to.sgpr2 = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap.2)
+  %to.sgpr3 = call i32 @llvm.amdgcn.readfirstlane(i32 %bswap.3)
+  %ins.0 = insertelement <4 x i32> undef, i32 %to.sgpr0, i32 0
+  %ins.1 = insertelement <4 x i32> %ins.0, i32 %to.sgpr1, i32 1
+  %ins.2 = insertelement <4 x i32> %ins.1, i32 %to.sgpr2, i32 2
+  %ins.3 = insertelement <4 x i32> %ins.2, i32 %to.sgpr3, i32 3
+  ret <4 x i32> %ins.3
+}
+
+define <2 x i64> @v_bswap_v2i64(<2 x i64> %src) {
+; GFX7-LABEL: v_bswap_v2i64:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_alignbit_b32 v4, v1, v1, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, v1, v1, 24
+; GFX7-NEXT:    s_mov_b32 s4, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v4, s4, v1, v4
+; GFX7-NEXT:    v_alignbit_b32 v1, v0, v0, 8
+; GFX7-NEXT:    v_alignbit_b32 v0, v0, v0, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s4, v0, v1
+; GFX7-NEXT:    v_alignbit_b32 v0, v3, v3, 8
+; GFX7-NEXT:    v_alignbit_b32 v3, v3, v3, 24
+; GFX7-NEXT:    v_bfi_b32 v5, s4, v3, v0
+; GFX7-NEXT:    v_alignbit_b32 v0, v2, v2, 8
+; GFX7-NEXT:    v_alignbit_b32 v2, v2, v2, 24
+; GFX7-NEXT:    v_bfi_b32 v3, s4, v2, v0
+; GFX7-NEXT:    v_mov_b32_e32 v0, v4
+; GFX7-NEXT:    v_mov_b32_e32 v2, v5
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bswap_v2i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0x10203
+; GFX8-NEXT:    v_perm_b32 v4, 0, v1, s4
+; GFX8-NEXT:    v_perm_b32 v5, 0, v3, s4
+; GFX8-NEXT:    v_perm_b32 v1, 0, v0, s4
+; GFX8-NEXT:    v_perm_b32 v3, 0, v2, s4
+; GFX8-NEXT:    v_mov_b32_e32 v0, v4
+; GFX8-NEXT:    v_mov_b32_e32 v2, v5
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_bswap_v2i64:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s4, 0x10203
+; GFX9-NEXT:    v_perm_b32 v4, 0, v1, s4
+; GFX9-NEXT:    v_perm_b32 v5, 0, v3, s4
+; GFX9-NEXT:    v_perm_b32 v1, 0, v0, s4
+; GFX9-NEXT:    v_perm_b32 v3, 0, v2, s4
+; GFX9-NEXT:    v_mov_b32_e32 v0, v4
+; GFX9-NEXT:    v_mov_b32_e32 v2, v5
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
+  ret <2 x i64> %bswap
+}
+
+define amdgpu_ps i16 @s_bswap_i16(i16 inreg %src) {
+; GFX7-LABEL: s_bswap_i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_alignbit_b32 v0, s0, s0, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, s0, s0, 24
+; GFX7-NEXT:    s_mov_b32 s0, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s0, v1, v0
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX7-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_bswap_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    s_mov_b32 s0, 0x10203
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v1, 0xffff
+; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_bswap_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    s_mov_b32 s0, 0x10203
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0xffff
+; GFX9-NEXT:    v_and_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    ; return to shader part epilog
+  %bswap = call i16 @llvm.bswap.i16(i16 %src)
+  %zext = zext i16 %bswap to i32
+  %to.sgpr = call i32 @llvm.amdgcn.readfirstlane(i32 %zext)
+  %trunc = trunc i32 %to.sgpr to i16
+  ret i16 %trunc
+}
+
+define i16 @v_bswap_i16(i16 %src) {
+; GFX7-LABEL: v_bswap_i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_alignbit_b32 v1, v0, v0, 8
+; GFX7-NEXT:    v_alignbit_b32 v0, v0, v0, 24
+; GFX7-NEXT:    s_mov_b32 s4, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bswap_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b32 s4, 0x10203
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_bswap_i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s4, 0x10203
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %bswap = call i16 @llvm.bswap.i16(i16 %src)
+  ret i16 %bswap
+}
+
+define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) {
+; GFX7-LABEL: s_bswap_v2i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    v_alignbit_b32 v0, s0, s0, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, s0, s0, 24
+; GFX7-NEXT:    s_mov_b32 s0, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s0, v1, v0
+; GFX7-NEXT:    v_alignbit_b32 v1, s1, s1, 8
+; GFX7-NEXT:    v_alignbit_b32 v2, s1, s1, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s0, v2, v1
+; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    s_mov_b32 s0, 0xffff
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_and_b32_e32 v1, s0, v1
+; GFX7-NEXT:    v_and_b32_e32 v0, s0, v0
+; GFX7-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX7-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: s_bswap_v2i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX8-NEXT:    v_mov_b32_e32 v0, s0
+; GFX8-NEXT:    s_mov_b32 s0, 0x10203
+; GFX8-NEXT:    v_mov_b32_e32 v1, s1
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0xffff
+; GFX8-NEXT:    v_perm_b32 v1, 0, v1, s0
+; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX9-LABEL: s_bswap_v2i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    s_mov_b32 s0, 0x10203
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    v_perm_b32 v1, 0, v1, s0
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s0
+; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v1
+; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX9-NEXT:    ; return to shader part epilog
+  %bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)
+  %cast0 = bitcast <2 x i16> %bswap to i32
+  %to.sgpr = call i32 @llvm.amdgcn.readfirstlane(i32 %cast0)
+  ret i32 %to.sgpr
+}
+
+define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {
+; GFX7-LABEL: v_bswap_v2i16:
+; GFX7:       ; %bb.0:
+; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT:    v_alignbit_b32 v2, v0, v0, 8
+; GFX7-NEXT:    v_alignbit_b32 v0, v0, v0, 24
+; GFX7-NEXT:    s_mov_b32 s4, 0xff00ff
+; GFX7-NEXT:    v_bfi_b32 v0, s4, v0, v2
+; GFX7-NEXT:    v_alignbit_b32 v2, v1, v1, 8
+; GFX7-NEXT:    v_alignbit_b32 v1, v1, v1, 24
+; GFX7-NEXT:    v_bfi_b32 v1, s4, v1, v2
+; GFX7-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX7-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_bswap_v2i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX8-NEXT:    s_mov_b32 s4, 0x10203
+; GFX8-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0xffff
+; GFX8-NEXT:    v_perm_b32 v1, 0, v1, s4
+; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: v_bswap_v2i16:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
+; GFX9-NEXT:    s_mov_b32 s4, 0x10203
+; GFX9-NEXT:    v_perm_b32 v1, 0, v1, s4
+; GFX9-NEXT:    v_perm_b32 v0, 0, v0, s4
+; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v1
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+  %bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)
+  ret <2 x i16> %bswap
+}
+
+; FIXME
+; define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) {
+;   %bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %ext.src)
+;   ret <3 x i16> %bswap
+; }
+
+declare i32 @llvm.amdgcn.readfirstlane(i32) #0
+declare i16 @llvm.bswap.i16(i16) #1
+declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>) #1
+declare <3 x i16> @llvm.bswap.v3i16(<3 x i16>) #1
+declare i32 @llvm.bswap.i32(i32) #1
+declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) #1
+declare i64 @llvm.bswap.i64(i64) #1
+declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) #1
+
+attributes #0 = { convergent nounwind readnone }
+attributes #1 = { nounwind readnone speculatable willreturn }
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
@@ -0,0 +1,28 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX8 %s
+
+---
+name: bswap_i32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; GFX7-LABEL: name: bswap_i32_vv
+    ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX7: [[V_ALIGNBIT_B32_:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32 [[COPY]], [[COPY]], 8, implicit $exec
+    ; GFX7: [[V_ALIGNBIT_B32_1:%[0-9]+]]:vgpr_32 = V_ALIGNBIT_B32 [[COPY]], [[COPY]], 24, implicit $exec
+    ; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16711935
+    ; GFX7: [[V_BFI_B32_:%[0-9]+]]:vgpr_32 = V_BFI_B32 [[S_MOV_B32_]], [[V_ALIGNBIT_B32_1]], [[V_ALIGNBIT_B32_]], implicit $exec
+    ; GFX7: S_ENDPGM 0, implicit [[V_BFI_B32_]]
+    ; GFX8-LABEL: name: bswap_i32_vv
+    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 66051
+    ; GFX8: [[V_PERM_B32_:%[0-9]+]]:vgpr_32 = V_PERM_B32 0, [[COPY]], [[S_MOV_B32_]], implicit $exec
+    ; GFX8: S_ENDPGM 0, implicit [[V_PERM_B32_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_BSWAP %0
+    S_ENDPGM 0, implicit %1
+...
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
@@ -129,3 +129,20 @@
     $vgpr0_vgpr1 = COPY %1
 ...
 
+---
+name: bswap_s64
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: bswap_s64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[UV1]]
+    ; CHECK: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[UV]]
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[BSWAP]](s32), [[BSWAP1]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = G_BSWAP %0
+    $vgpr0_vgpr1 = COPY %1
+...
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
@@ -11,7 +11,8 @@
     liveins: $sgpr0
     ; CHECK-LABEL: name: bswap_i32_s
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[BSWAP:%[0-9]+]]:sgpr(s32) = G_BSWAP [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+    ; CHECK: [[BSWAP:%[0-9]+]]:vgpr(s32) = G_BSWAP [[COPY1]]
     %0:_(s32) = COPY $sgpr0
     %1:_(s32) = G_BSWAP %0
 ...