Index: lib/Target/X86/X86FastISel.cpp
===================================================================
--- lib/Target/X86/X86FastISel.cpp
+++ lib/Target/X86/X86FastISel.cpp
@@ -2009,10 +2009,25 @@
     if (V->getType()->isFloatTy()) {
       unsigned OpReg = getRegForValue(V);
       if (OpReg == 0) return false;
-      unsigned ResultReg = createResultReg(&X86::FR64RegClass);
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-              TII.get(X86::CVTSS2SDrr), ResultReg)
-        .addReg(OpReg);
+      // Avoid introducing a legacy SSE instruction if the target has AVX.
+      bool HasAVX = Subtarget->hasAVX();
+      unsigned Opc = HasAVX ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr;
+
+      unsigned ImplicitDefReg = 0;
+      const TargetRegisterClass *RC = &X86::FR64RegClass;
+      if (HasAVX) {
+        ImplicitDefReg = createResultReg(RC);
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+                TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
+      }
+
+      MachineInstrBuilder MIB;
+      unsigned ResultReg = createResultReg(RC);
+      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
+                    ResultReg);
+      if (ImplicitDefReg)
+        MIB.addReg(ImplicitDefReg);
+      MIB.addReg(OpReg);
       updateValueMap(I, ResultReg);
       return true;
     }
@@ -2022,19 +2037,32 @@
 }
 
 bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
-  if (X86ScalarSSEf64) {
-    if (I->getType()->isFloatTy()) {
-      const Value *V = I->getOperand(0);
-      if (V->getType()->isDoubleTy()) {
-        unsigned OpReg = getRegForValue(V);
-        if (OpReg == 0) return false;
-        unsigned ResultReg = createResultReg(&X86::FR32RegClass);
+  if (X86ScalarSSEf64 && I->getType()->isFloatTy()) {
+    const Value *V = I->getOperand(0);
+    if (V->getType()->isDoubleTy()) {
+      unsigned OpReg = getRegForValue(V);
+      if (OpReg == 0) return false;
+      // Avoid introducing a legacy SSE instruction if the target has AVX.
+      bool HasAVX = Subtarget->hasAVX();
+      unsigned Opc = HasAVX ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr;
+
+      unsigned ImplicitDefReg = 0;
+      const TargetRegisterClass *RC = &X86::FR32RegClass;
+      if (HasAVX) {
+        ImplicitDefReg = createResultReg(RC);
         BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-                TII.get(X86::CVTSD2SSrr), ResultReg)
-          .addReg(OpReg);
-        updateValueMap(I, ResultReg);
-        return true;
+                TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
       }
+
+      MachineInstrBuilder MIB;
+      unsigned ResultReg = createResultReg(RC);
+      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
+                    ResultReg);
+      if (ImplicitDefReg)
+        MIB.addReg(ImplicitDefReg);
+      MIB.addReg(OpReg);
+      updateValueMap(I, ResultReg);
+      return true;
     }
   }
 
Index: test/CodeGen/X86/fast-isel-fptrunc-fpext.ll
===================================================================
--- test/CodeGen/X86/fast-isel-fptrunc-fpext.ll
+++ test/CodeGen/X86/fast-isel-fptrunc-fpext.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -fast-isel | FileCheck %s --check-prefix=ALL --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -fast-isel | FileCheck %s --check-prefix=ALL --check-prefix=AVX
+;
+; Verify that fast-isel doesn't select legacy SSE instructions on targets that
+; feature AVX.
+;
+; Test cases are obtained from the following code snippet:
+; ///
+; double single_to_double_rr(float x) {
+;   return (double)x;
+; }
+; float double_to_single_rr(double x) {
+;   return (float)x;
+; }
+; double single_to_double_rm(float *x) {
+;   return (double)*x;
+; }
+; float double_to_single_rm(double *x) {
+;   return (float)*x;
+; }
+; ///
+
+define double @single_to_double_rr(float %x) {
+; ALL-LABEL: single_to_double_rr:
+; SSE: cvtss2sd %xmm0, %xmm0
+; AVX: vcvtss2sd %xmm0, %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %conv = fpext float %x to double
+  ret double %conv
+}
+
+define float @double_to_single_rr(double %x) {
+; ALL-LABEL: double_to_single_rr:
+; SSE: cvtsd2ss %xmm0, %xmm0
+; AVX: vcvtsd2ss %xmm0, %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %conv = fptrunc double %x to float
+  ret float %conv
+}
+
+define double @single_to_double_rm(float* %x) {
+; ALL-LABEL: single_to_double_rm:
+; SSE: cvtss2sd (%rdi), %xmm0
+; AVX: vcvtss2sd (%rdi), %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = load float* %x, align 4
+  %conv = fpext float %0 to double
+  ret double %conv
+}
+
+define float @double_to_single_rm(double* %x) {
+; ALL-LABEL: double_to_single_rm:
+; SSE: cvtsd2ss (%rdi), %xmm0
+; AVX: vcvtsd2ss (%rdi), %xmm0, %xmm0
+; ALL-NEXT: ret
+entry:
+  %0 = load double* %x, align 8
+  %conv = fptrunc double %0 to float
+  ret float %conv
+}