diff --git a/llvm/include/llvm/MC/MCInstPrinter.h b/llvm/include/llvm/MC/MCInstPrinter.h --- a/llvm/include/llvm/MC/MCInstPrinter.h +++ b/llvm/include/llvm/MC/MCInstPrinter.h @@ -129,14 +129,17 @@ struct AliasPatternCond { enum CondKind : uint8_t { - K_Feature, // Match only if a feature is enabled. - K_NegFeature, // Match only if a feature is disabled. - K_Ignore, // Match any operand. - K_Reg, // Match a specific register. - K_TiedReg, // Match another already matched register. - K_Imm, // Match a specific immediate. - K_RegClass, // Match registers in a class. - K_Custom, // Call custom matcher by index. + K_Feature, // Match only if a feature is enabled. + K_NegFeature, // Match only if a feature is disabled. + K_OrFeature, // Match only if one of a set of features is enabled. + K_OrNegFeature, // Match only if one of a set of features is disabled. + K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features. + K_Ignore, // Match any operand. + K_Reg, // Match a specific register. + K_TiedReg, // Match another already matched register. + K_Imm, // Match a specific immediate. + K_RegClass, // Match registers in a class. + K_Custom, // Call custom matcher by index. }; CondKind Kind; diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -664,14 +664,21 @@ /// feature from the AssemblerPredicate class in addition to Predicate. bit AssemblerMatcherPredicate = 0; - /// AssemblerCondString - Name of the subtarget feature being tested used - /// as alternative condition string used for assembler matcher. - /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". - /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". - /// It can also list multiple features separated by ",". - /// e.g. "ModeThumb,FeatureThumb2" is translated to + /// AssemblerCondDag - Set of subtarget features being tested used + /// as alternative condition string used for assembler matcher. Must be used + /// with (all_of) to indicate that all features must be present, or (any_of) + /// to indicate that at least one must be. The required lack of presence of + /// a feature can be tested using a (not) node including the feature. + /// e.g. "(all_of ModeThumb)" is translated to "(Bits & ModeThumb) != 0". + /// "(all_of (not ModeThumb))" is translated to + /// "(Bits & ModeThumb) == 0". + /// "(all_of ModeThumb, FeatureThumb2)" is translated to /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". - string AssemblerCondString = ""; + /// "(any_of ModeTumb, FeatureThumb2)" is translated to + /// "(Bits & ModeThumb) != 0 || (Bits & FeatureThumb2) != 0". + /// all_of and any_of cannot be combined in a single dag, instead multiple + /// predicates can be placed onto Instruction definitions. + dag AssemblerCondDag; /// PredicateName - User-level name to use for the predicate. Mainly for use /// in diagnostics such as missing feature errors in the asm matcher. @@ -1352,11 +1359,15 @@ } def DefaultAsmParserVariant : AsmParserVariant; +// Operators for combining SubtargetFeatures in AssemblerPredicates +def any_of; +def all_of; + /// AssemblerPredicate - This is a Predicate that can be used when the assembler /// matches instructions and aliases. -class AssemblerPredicate { +class AssemblerPredicate { bit AssemblerMatcherPredicate = 1; - string AssemblerCondString = cond; + dag AssemblerCondDag = cond; string PredicateName = name; } diff --git a/llvm/lib/MC/MCInstPrinter.cpp b/llvm/lib/MC/MCInstPrinter.cpp --- a/llvm/lib/MC/MCInstPrinter.cpp +++ b/llvm/lib/MC/MCInstPrinter.cpp @@ -62,12 +62,29 @@ static bool matchAliasCondition(const MCInst &MI, const MCSubtargetInfo *STI, const MCRegisterInfo &MRI, unsigned &OpIdx, const AliasMatchingData &M, - const AliasPatternCond &C) { + const AliasPatternCond &C, + bool &OrPredicateResult) { // Feature tests are special, they don't consume operands. if (C.Kind == AliasPatternCond::K_Feature) return STI->getFeatureBits().test(C.Value); if (C.Kind == AliasPatternCond::K_NegFeature) return !STI->getFeatureBits().test(C.Value); + // For feature tests where just one feature is required in a list, set the + // predicate result bit to whether the expression will return true, and only + // return the real result at the end of list marker. + if (C.Kind == AliasPatternCond::K_OrFeature) { + OrPredicateResult |= STI->getFeatureBits().test(C.Value); + return true; + } + if (C.Kind == AliasPatternCond::K_OrNegFeature) { + OrPredicateResult |= !(STI->getFeatureBits().test(C.Value)); + return true; + } + if (C.Kind == AliasPatternCond::K_EndOrFeatures) { + bool Res = OrPredicateResult; + OrPredicateResult = false; + return Res; + } // Get and consume an operand. const MCOperand &Opnd = MI.getOperand(OpIdx); @@ -95,6 +112,9 @@ return true; case AliasPatternCond::K_Feature: case AliasPatternCond::K_NegFeature: + case AliasPatternCond::K_OrFeature: + case AliasPatternCond::K_OrNegFeature: + case AliasPatternCond::K_EndOrFeatures: llvm_unreachable("handled earlier"); } llvm_unreachable("invalid kind"); @@ -125,8 +145,10 @@ ArrayRef Conds = M.PatternConds.slice(P.AliasCondStart, P.NumConds); unsigned OpIdx = 0; + bool OrPredicateResult = false; if (llvm::all_of(Conds, [&](const AliasPatternCond &C) { - return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C); + return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C, + OrPredicateResult); })) { // If all conditions matched, use this asm string. AsmStrOffset = P.AsmStrOffset; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -14,134 +14,134 @@ // ARM Instruction Predicate Definitions. // def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, - AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; + AssemblerPredicate<(all_of HasV8_1aOps), "armv8.1a">; def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, - AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; + AssemblerPredicate<(all_of HasV8_2aOps), "armv8.2a">; def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, - AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; + AssemblerPredicate<(all_of HasV8_3aOps), "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, - AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; + AssemblerPredicate<(all_of HasV8_4aOps), "armv8.4a">; def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, - AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; + AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">; def HasVH : Predicate<"Subtarget->hasVH()">, - AssemblerPredicate<"FeatureVH", "vh">; + AssemblerPredicate<(all_of FeatureVH), "vh">; def HasLOR : Predicate<"Subtarget->hasLOR()">, - AssemblerPredicate<"FeatureLOR", "lor">; + AssemblerPredicate<(all_of FeatureLOR), "lor">; def HasPA : Predicate<"Subtarget->hasPA()">, - AssemblerPredicate<"FeaturePA", "pa">; + AssemblerPredicate<(all_of FeaturePA), "pa">; def HasJS : Predicate<"Subtarget->hasJS()">, - AssemblerPredicate<"FeatureJS", "jsconv">; + AssemblerPredicate<(all_of FeatureJS), "jsconv">; def HasCCIDX : Predicate<"Subtarget->hasCCIDX()">, - AssemblerPredicate<"FeatureCCIDX", "ccidx">; + AssemblerPredicate<(all_of FeatureCCIDX), "ccidx">; def HasComplxNum : Predicate<"Subtarget->hasComplxNum()">, - AssemblerPredicate<"FeatureComplxNum", "complxnum">; + AssemblerPredicate<(all_of FeatureComplxNum), "complxnum">; def HasNV : Predicate<"Subtarget->hasNV()">, - AssemblerPredicate<"FeatureNV", "nv">; + AssemblerPredicate<(all_of FeatureNV), "nv">; def HasRASv8_4 : Predicate<"Subtarget->hasRASv8_4()">, - AssemblerPredicate<"FeatureRASv8_4", "rasv8_4">; + AssemblerPredicate<(all_of FeatureRASv8_4), "rasv8_4">; def HasMPAM : Predicate<"Subtarget->hasMPAM()">, - AssemblerPredicate<"FeatureMPAM", "mpam">; + AssemblerPredicate<(all_of FeatureMPAM), "mpam">; def HasDIT : Predicate<"Subtarget->hasDIT()">, - AssemblerPredicate<"FeatureDIT", "dit">; + AssemblerPredicate<(all_of FeatureDIT), "dit">; def HasTRACEV8_4 : Predicate<"Subtarget->hasTRACEV8_4()">, - AssemblerPredicate<"FeatureTRACEV8_4", "tracev8.4">; + AssemblerPredicate<(all_of FeatureTRACEV8_4), "tracev8.4">; def HasAM : Predicate<"Subtarget->hasAM()">, - AssemblerPredicate<"FeatureAM", "am">; + AssemblerPredicate<(all_of FeatureAM), "am">; def HasSEL2 : Predicate<"Subtarget->hasSEL2()">, - AssemblerPredicate<"FeatureSEL2", "sel2">; + AssemblerPredicate<(all_of FeatureSEL2), "sel2">; def HasPMU : Predicate<"Subtarget->hasPMU()">, - AssemblerPredicate<"FeaturePMU", "pmu">; + AssemblerPredicate<(all_of FeaturePMU), "pmu">; def HasTLB_RMI : Predicate<"Subtarget->hasTLB_RMI()">, - AssemblerPredicate<"FeatureTLB_RMI", "tlb-rmi">; + AssemblerPredicate<(all_of FeatureTLB_RMI), "tlb-rmi">; def HasFMI : Predicate<"Subtarget->hasFMI()">, - AssemblerPredicate<"FeatureFMI", "fmi">; + AssemblerPredicate<(all_of FeatureFMI), "fmi">; def HasRCPC_IMMO : Predicate<"Subtarget->hasRCPCImm()">, - AssemblerPredicate<"FeatureRCPC_IMMO", "rcpc-immo">; + AssemblerPredicate<(all_of FeatureRCPC_IMMO), "rcpc-immo">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, - AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; + AssemblerPredicate<(all_of FeatureFPARMv8), "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, - AssemblerPredicate<"FeatureNEON", "neon">; + AssemblerPredicate<(all_of FeatureNEON), "neon">; def HasCrypto : Predicate<"Subtarget->hasCrypto()">, - AssemblerPredicate<"FeatureCrypto", "crypto">; + AssemblerPredicate<(all_of FeatureCrypto), "crypto">; def HasSM4 : Predicate<"Subtarget->hasSM4()">, - AssemblerPredicate<"FeatureSM4", "sm4">; + AssemblerPredicate<(all_of FeatureSM4), "sm4">; def HasSHA3 : Predicate<"Subtarget->hasSHA3()">, - AssemblerPredicate<"FeatureSHA3", "sha3">; + AssemblerPredicate<(all_of FeatureSHA3), "sha3">; def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, - AssemblerPredicate<"FeatureSHA2", "sha2">; + AssemblerPredicate<(all_of FeatureSHA2), "sha2">; def HasAES : Predicate<"Subtarget->hasAES()">, - AssemblerPredicate<"FeatureAES", "aes">; + AssemblerPredicate<(all_of FeatureAES), "aes">; def HasDotProd : Predicate<"Subtarget->hasDotProd()">, - AssemblerPredicate<"FeatureDotProd", "dotprod">; + AssemblerPredicate<(all_of FeatureDotProd), "dotprod">; def HasCRC : Predicate<"Subtarget->hasCRC()">, - AssemblerPredicate<"FeatureCRC", "crc">; + AssemblerPredicate<(all_of FeatureCRC), "crc">; def HasLSE : Predicate<"Subtarget->hasLSE()">, - AssemblerPredicate<"FeatureLSE", "lse">; + AssemblerPredicate<(all_of FeatureLSE), "lse">; def HasRAS : Predicate<"Subtarget->hasRAS()">, - AssemblerPredicate<"FeatureRAS", "ras">; + AssemblerPredicate<(all_of FeatureRAS), "ras">; def HasRDM : Predicate<"Subtarget->hasRDM()">, - AssemblerPredicate<"FeatureRDM", "rdm">; + AssemblerPredicate<(all_of FeatureRDM), "rdm">; def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">; def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, - AssemblerPredicate<"FeatureFullFP16", "fullfp16">; + AssemblerPredicate<(all_of FeatureFullFP16), "fullfp16">; def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, - AssemblerPredicate<"FeatureFP16FML", "fp16fml">; + AssemblerPredicate<(all_of FeatureFP16FML), "fp16fml">; def HasSPE : Predicate<"Subtarget->hasSPE()">, - AssemblerPredicate<"FeatureSPE", "spe">; + AssemblerPredicate<(all_of FeatureSPE), "spe">; def HasFuseAES : Predicate<"Subtarget->hasFuseAES()">, - AssemblerPredicate<"FeatureFuseAES", + AssemblerPredicate<(all_of FeatureFuseAES), "fuse-aes">; def HasSVE : Predicate<"Subtarget->hasSVE()">, - AssemblerPredicate<"FeatureSVE", "sve">; + AssemblerPredicate<(all_of FeatureSVE), "sve">; def HasSVE2 : Predicate<"Subtarget->hasSVE2()">, - AssemblerPredicate<"FeatureSVE2", "sve2">; + AssemblerPredicate<(all_of FeatureSVE2), "sve2">; def HasSVE2AES : Predicate<"Subtarget->hasSVE2AES()">, - AssemblerPredicate<"FeatureSVE2AES", "sve2-aes">; + AssemblerPredicate<(all_of FeatureSVE2AES), "sve2-aes">; def HasSVE2SM4 : Predicate<"Subtarget->hasSVE2SM4()">, - AssemblerPredicate<"FeatureSVE2SM4", "sve2-sm4">; + AssemblerPredicate<(all_of FeatureSVE2SM4), "sve2-sm4">; def HasSVE2SHA3 : Predicate<"Subtarget->hasSVE2SHA3()">, - AssemblerPredicate<"FeatureSVE2SHA3", "sve2-sha3">; + AssemblerPredicate<(all_of FeatureSVE2SHA3), "sve2-sha3">; def HasSVE2BitPerm : Predicate<"Subtarget->hasSVE2BitPerm()">, - AssemblerPredicate<"FeatureSVE2BitPerm", "sve2-bitperm">; + AssemblerPredicate<(all_of FeatureSVE2BitPerm), "sve2-bitperm">; def HasRCPC : Predicate<"Subtarget->hasRCPC()">, - AssemblerPredicate<"FeatureRCPC", "rcpc">; + AssemblerPredicate<(all_of FeatureRCPC), "rcpc">; def HasAltNZCV : Predicate<"Subtarget->hasAlternativeNZCV()">, - AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">; + AssemblerPredicate<(all_of FeatureAltFPCmp), "altnzcv">; def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">, - AssemblerPredicate<"FeatureFRInt3264", "frint3264">; + AssemblerPredicate<(all_of FeatureFRInt3264), "frint3264">; def HasSB : Predicate<"Subtarget->hasSB()">, - AssemblerPredicate<"FeatureSB", "sb">; + AssemblerPredicate<(all_of FeatureSB), "sb">; def HasPredRes : Predicate<"Subtarget->hasPredRes()">, - AssemblerPredicate<"FeaturePredRes", "predres">; + AssemblerPredicate<(all_of FeaturePredRes), "predres">; def HasCCDP : Predicate<"Subtarget->hasCCDP()">, - AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">; + AssemblerPredicate<(all_of FeatureCacheDeepPersist), "ccdp">; def HasBTI : Predicate<"Subtarget->hasBTI()">, - AssemblerPredicate<"FeatureBranchTargetId", "bti">; + AssemblerPredicate<(all_of FeatureBranchTargetId), "bti">; def HasMTE : Predicate<"Subtarget->hasMTE()">, - AssemblerPredicate<"FeatureMTE", "mte">; + AssemblerPredicate<(all_of FeatureMTE), "mte">; def HasTME : Predicate<"Subtarget->hasTME()">, - AssemblerPredicate<"FeatureTME", "tme">; + AssemblerPredicate<(all_of FeatureTME), "tme">; def HasETE : Predicate<"Subtarget->hasETE()">, - AssemblerPredicate<"FeatureETE", "ete">; + AssemblerPredicate<(all_of FeatureETE), "ete">; def HasTRBE : Predicate<"Subtarget->hasTRBE()">, - AssemblerPredicate<"FeatureTRBE", "trbe">; + AssemblerPredicate<(all_of FeatureTRBE), "trbe">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; @@ -149,7 +149,7 @@ : Predicate<"Subtarget->useAlternateSExtLoadCVTF32Pattern()">; def UseNegativeImmediates - : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates", + : Predicate<"false">, AssemblerPredicate<(all_of (not FeatureNoNegativeImmediates)), "NegativeImmediates">; def AArch64LocalRecover : SDNode<"ISD::LOCAL_RECOVER", diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -18,18 +18,18 @@ //===----------------------------------------------------------------------===// def HasCCPP : Predicate<"Subtarget->hasCCPP()">, - AssemblerPredicate<"FeatureCCPP", "ccpp">; + AssemblerPredicate<(all_of FeatureCCPP), "ccpp">; def HasPAN : Predicate<"Subtarget->hasPAN()">, - AssemblerPredicate<"FeaturePAN", + AssemblerPredicate<(all_of FeaturePAN), "ARM v8.1 Privileged Access-Never extension">; def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">, - AssemblerPredicate<"FeaturePsUAO", + AssemblerPredicate<(all_of FeaturePsUAO), "ARM v8.2 UAO PState extension (psuao)">; def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">, - AssemblerPredicate<"FeaturePAN_RWV", + AssemblerPredicate<(all_of FeaturePAN_RWV), "ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -980,193 +980,193 @@ def isGFX6 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">, - AssemblerPredicate<"FeatureSouthernIslands">; + AssemblerPredicate<(all_of FeatureSouthernIslands)>; def isGFX6GFX7 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, - AssemblerPredicate<"!FeatureGCN3Encoding,!FeatureGFX10Insts">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding), (not FeatureGFX10Insts))>; def isGFX6GFX7GFX10 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">, - AssemblerPredicate<"!FeatureGCN3Encoding">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding))>; def isGFX7Only : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">, - AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts,!FeatureGFX10Insts">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts, (not FeatureGFX10Insts))>; def isGFX7GFX10 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">, - AssemblerPredicate<"!FeatureGCN3Encoding,FeatureCIInsts">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureCIInsts)>; def isGFX7GFX8GFX9 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, - AssemblerPredicate<"FeatureGFX7GFX8GFX9Insts">; + AssemblerPredicate<(all_of FeatureGFX7GFX8GFX9Insts)>; def isGFX6GFX7GFX8GFX9 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, - AssemblerPredicate<"!FeatureGFX10Insts">; + AssemblerPredicate<(all_of (not FeatureGFX10Insts))>; def isGFX7Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">, - AssemblerPredicate<"FeatureCIInsts">; + AssemblerPredicate<(all_of FeatureCIInsts)>; def isGFX8Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS">, - AssemblerPredicate<"FeatureGFX8Insts">; + AssemblerPredicate<(all_of FeatureGFX8Insts)>; def isGFX8Only : Predicate<"Subtarget->getGeneration() ==" "AMDGPUSubtarget::VOLCANIC_ISLANDS">, - AssemblerPredicate <"FeatureVolcanicIslands">; + AssemblerPredicate <(all_of FeatureVolcanicIslands)>; def isGFX9Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">, - AssemblerPredicate<"FeatureGFX9Insts">; + AssemblerPredicate<(all_of FeatureGFX9Insts)>; def isGFX9Only : Predicate < "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, - AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts">; + AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts)>; def isGFX8GFX9 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::GFX9">, - AssemblerPredicate<"FeatureGFX8Insts,FeatureGCN3Encoding">; + AssemblerPredicate<(all_of FeatureGFX8Insts, FeatureGCN3Encoding)>; def isGFX10Plus : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10">, - AssemblerPredicate<"FeatureGFX10Insts">; + AssemblerPredicate<(all_of FeatureGFX10Insts)>; def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">, - AssemblerPredicate<"FeatureFlatAddressSpace">; + AssemblerPredicate<(all_of FeatureFlatAddressSpace)>; def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">, - AssemblerPredicate<"FeatureFlatGlobalInsts">; + AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>; def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">, - AssemblerPredicate<"FeatureFlatScratchInsts">; + AssemblerPredicate<(all_of FeatureFlatScratchInsts)>; def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">, - AssemblerPredicate<"FeatureScalarFlatScratchInsts">; + AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>; def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">, - AssemblerPredicate<"FeatureGFX9Insts">; + AssemblerPredicate<(all_of FeatureGFX9Insts)>; def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">, - AssemblerPredicate<"FeatureUnpackedD16VMem">; + AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>; def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">, - AssemblerPredicate<"!FeatureUnpackedD16VMem">; + AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>; def D16PreservesUnusedBits : Predicate<"Subtarget->d16PreservesUnusedBits()">, - AssemblerPredicate<"FeatureGFX9Insts,!FeatureSRAMECC">; + AssemblerPredicate<(all_of FeatureGFX9Insts, (not FeatureSRAMECC))>; def LDSRequiresM0Init : Predicate<"Subtarget->ldsRequiresM0Init()">; def NotLDSRequiresM0Init : Predicate<"!Subtarget->ldsRequiresM0Init()">; def HasDSAddTid : Predicate<"Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9">, - AssemblerPredicate<"FeatureGFX9Insts">; + AssemblerPredicate<(all_of FeatureGFX9Insts)>; def HasAddNoCarryInsts : Predicate<"Subtarget->hasAddNoCarry()">, - AssemblerPredicate<"FeatureAddNoCarryInsts">; + AssemblerPredicate<(all_of FeatureAddNoCarryInsts)>; def NotHasAddNoCarryInsts : Predicate<"!Subtarget->hasAddNoCarry()">; def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">, - AssemblerPredicate<"Feature16BitInsts">; + AssemblerPredicate<(all_of Feature16BitInsts)>; def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">, - AssemblerPredicate<"FeatureVOP3P">; + AssemblerPredicate<(all_of FeatureVOP3P)>; def HasSDWA : Predicate<"Subtarget->hasSDWA()">, - AssemblerPredicate<"FeatureSDWA,FeatureVolcanicIslands">; + AssemblerPredicate<(all_of FeatureSDWA, FeatureVolcanicIslands)>; def HasSDWA9 : Predicate<"Subtarget->hasSDWA()">, - AssemblerPredicate<"FeatureGCN3Encoding,FeatureGFX9Insts,FeatureSDWA">; + AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureGFX9Insts,FeatureSDWA)>; def HasSDWA10 : Predicate<"Subtarget->hasSDWA()">, - AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureSDWA">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureSDWA)>; def HasDPP : Predicate<"Subtarget->hasDPP()">, - AssemblerPredicate<"FeatureGCN3Encoding,FeatureDPP">; + AssemblerPredicate<(all_of FeatureGCN3Encoding, FeatureDPP)>; def HasDPP8 : Predicate<"Subtarget->hasDPP8()">, - AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP8">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP8)>; def HasR128A16 : Predicate<"Subtarget->hasR128A16()">, - AssemblerPredicate<"FeatureR128A16">; + AssemblerPredicate<(all_of FeatureR128A16)>; def HasGFX10A16 : Predicate<"Subtarget->hasGFX10A16()">, - AssemblerPredicate<"FeatureGFX10A16">; + AssemblerPredicate<(all_of FeatureGFX10A16)>; def HasDPP16 : Predicate<"Subtarget->hasDPP()">, - AssemblerPredicate<"!FeatureGCN3Encoding,FeatureGFX10Insts,FeatureDPP">; + AssemblerPredicate<(all_of (not FeatureGCN3Encoding), FeatureGFX10Insts, FeatureDPP)>; def HasIntClamp : Predicate<"Subtarget->hasIntClamp()">, - AssemblerPredicate<"FeatureIntClamp">; + AssemblerPredicate<(all_of FeatureIntClamp)>; def HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">, - AssemblerPredicate<"FeatureMadMixInsts">; + AssemblerPredicate<(all_of FeatureMadMixInsts)>; def HasScalarStores : Predicate<"Subtarget->hasScalarStores()">, - AssemblerPredicate<"FeatureScalarStores">; + AssemblerPredicate<(all_of FeatureScalarStores)>; def HasScalarAtomics : Predicate<"Subtarget->hasScalarAtomics()">, - AssemblerPredicate<"FeatureScalarAtomics">; + AssemblerPredicate<(all_of FeatureScalarAtomics)>; def HasNoSdstCMPX : Predicate<"Subtarget->hasNoSdstCMPX()">, - AssemblerPredicate<"FeatureNoSdstCMPX">; + AssemblerPredicate<(all_of FeatureNoSdstCMPX)>; def HasSdstCMPX : Predicate<"!Subtarget->hasNoSdstCMPX()">, - AssemblerPredicate<"!FeatureNoSdstCMPX">; + AssemblerPredicate<(all_of (not FeatureNoSdstCMPX))>; def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">, - AssemblerPredicate<"FeatureVGPRIndexMode">; + AssemblerPredicate<(all_of FeatureVGPRIndexMode)>; def HasMovrel : Predicate<"Subtarget->hasMovrel()">, - AssemblerPredicate<"FeatureMovrel">; + AssemblerPredicate<(all_of FeatureMovrel)>; def HasFmaMixInsts : Predicate<"Subtarget->hasFmaMixInsts()">, - AssemblerPredicate<"FeatureFmaMixInsts">; + AssemblerPredicate<(all_of FeatureFmaMixInsts)>; def HasDLInsts : Predicate<"Subtarget->hasDLInsts()">, - AssemblerPredicate<"FeatureDLInsts">; + AssemblerPredicate<(all_of FeatureDLInsts)>; def HasDot1Insts : Predicate<"Subtarget->hasDot1Insts()">, - AssemblerPredicate<"FeatureDot1Insts">; + AssemblerPredicate<(all_of FeatureDot1Insts)>; def HasDot2Insts : Predicate<"Subtarget->hasDot2Insts()">, - AssemblerPredicate<"FeatureDot2Insts">; + AssemblerPredicate<(all_of FeatureDot2Insts)>; def HasDot3Insts : Predicate<"Subtarget->hasDot3Insts()">, - AssemblerPredicate<"FeatureDot3Insts">; + AssemblerPredicate<(all_of FeatureDot3Insts)>; def HasDot4Insts : Predicate<"Subtarget->hasDot4Insts()">, - AssemblerPredicate<"FeatureDot4Insts">; + AssemblerPredicate<(all_of FeatureDot4Insts)>; def HasDot5Insts : Predicate<"Subtarget->hasDot5Insts()">, - AssemblerPredicate<"FeatureDot5Insts">; + AssemblerPredicate<(all_of FeatureDot5Insts)>; def HasDot6Insts : Predicate<"Subtarget->hasDot6Insts()">, - AssemblerPredicate<"FeatureDot6Insts">; + AssemblerPredicate<(all_of FeatureDot6Insts)>; def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">, - AssemblerPredicate<"FeatureMAIInsts">; + AssemblerPredicate<(all_of FeatureMAIInsts)>; def HasPkFmacF16Inst : Predicate<"Subtarget->hasPkFmacF16Inst()">, - AssemblerPredicate<"FeaturePkFmacF16Inst">; + AssemblerPredicate<(all_of FeaturePkFmacF16Inst)>; def HasAtomicFaddInsts : Predicate<"Subtarget->hasAtomicFaddInsts()">, - AssemblerPredicate<"FeatureAtomicFaddInsts">; + AssemblerPredicate<(all_of FeatureAtomicFaddInsts)>; def HasOffset3fBug : Predicate<"!Subtarget->hasOffset3fBug()">, - AssemblerPredicate<"FeatureOffset3fBug">; + AssemblerPredicate<(all_of FeatureOffset3fBug)>; def EnableLateCFGStructurize : Predicate< "EnableLateStructurizeCFG">; diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -7,11 +7,11 @@ //===----------------------------------------------------------------------===// def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">, - AssemblerPredicate <"FeatureWavefrontSize32">; + AssemblerPredicate <(all_of FeatureWavefrontSize32)>; def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">, - AssemblerPredicate <"FeatureWavefrontSize64">; + AssemblerPredicate <(all_of FeatureWavefrontSize64)>; -def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">; +def DisableInst : Predicate <"false">, AssemblerPredicate<(all_of FeatureDisable)>; class GCNPredicateControl : PredicateControl { Predicate SIAssemblerPredicate = isGFX6GFX7; diff --git a/llvm/lib/Target/ARM/ARMPredicates.td b/llvm/lib/Target/ARM/ARMPredicates.td --- a/llvm/lib/Target/ARM/ARMPredicates.td +++ b/llvm/lib/Target/ARM/ARMPredicates.td @@ -7,151 +7,151 @@ //===----------------------------------------------------------------------===// def HasV4T : Predicate<"Subtarget->hasV4TOps()">, - AssemblerPredicate<"HasV4TOps", "armv4t">; + AssemblerPredicate<(all_of HasV4TOps), "armv4t">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">, - AssemblerPredicate<"HasV5TOps", "armv5t">; + AssemblerPredicate<(all_of HasV5TOps), "armv5t">; def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, - AssemblerPredicate<"HasV5TEOps", "armv5te">; + AssemblerPredicate<(all_of HasV5TEOps), "armv5te">; def HasV6 : Predicate<"Subtarget->hasV6Ops()">, - AssemblerPredicate<"HasV6Ops", "armv6">; + AssemblerPredicate<(all_of HasV6Ops), "armv6">; def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; def HasV6M : Predicate<"Subtarget->hasV6MOps()">, - AssemblerPredicate<"HasV6MOps", + AssemblerPredicate<(all_of HasV6MOps), "armv6m or armv6t2">; def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, - AssemblerPredicate<"HasV8MBaselineOps", + AssemblerPredicate<(all_of HasV8MBaselineOps), "armv8m.base">; def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, - AssemblerPredicate<"HasV8MMainlineOps", + AssemblerPredicate<(all_of HasV8MMainlineOps), "armv8m.main">; def HasV8_1MMainline : Predicate<"Subtarget->hasV8_1MMainlineOps()">, - AssemblerPredicate<"HasV8_1MMainlineOps", + AssemblerPredicate<(all_of HasV8_1MMainlineOps), "armv8.1m.main">; def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">, - AssemblerPredicate<"HasMVEIntegerOps", + AssemblerPredicate<(all_of HasMVEIntegerOps), "mve">; def HasMVEFloat : Predicate<"Subtarget->hasMVEFloatOps()">, - AssemblerPredicate<"HasMVEFloatOps", + AssemblerPredicate<(all_of HasMVEFloatOps), "mve.fp">; def HasCDE : Predicate<"Subtarget->hasCDEOps()">, - AssemblerPredicate<"HasCDEOps", + AssemblerPredicate<(all_of HasCDEOps), "cde">; def HasFPRegs : Predicate<"Subtarget->hasFPRegs()">, - AssemblerPredicate<"FeatureFPRegs", + AssemblerPredicate<(all_of FeatureFPRegs), "fp registers">; def HasFPRegs16 : Predicate<"Subtarget->hasFPRegs16()">, - AssemblerPredicate<"FeatureFPRegs16", + AssemblerPredicate<(all_of FeatureFPRegs16), "16-bit fp registers">; def HasFPRegs64 : Predicate<"Subtarget->hasFPRegs64()">, - AssemblerPredicate<"FeatureFPRegs64", + AssemblerPredicate<(all_of FeatureFPRegs64), "64-bit fp registers">; def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">, - AssemblerPredicate<"FeatureFPRegs,HasV8_1MMainlineOps", + AssemblerPredicate<(all_of FeatureFPRegs, HasV8_1MMainlineOps), "armv8.1m.main with FP or MVE">; def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, - AssemblerPredicate<"HasV6T2Ops", "armv6t2">; + AssemblerPredicate<(all_of HasV6T2Ops), "armv6t2">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; def HasV6K : Predicate<"Subtarget->hasV6KOps()">, - AssemblerPredicate<"HasV6KOps", "armv6k">; + AssemblerPredicate<(all_of HasV6KOps), "armv6k">; def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; def HasV7 : Predicate<"Subtarget->hasV7Ops()">, - AssemblerPredicate<"HasV7Ops", "armv7">; + AssemblerPredicate<(all_of HasV7Ops), "armv7">; def HasV8 : Predicate<"Subtarget->hasV8Ops()">, - AssemblerPredicate<"HasV8Ops", "armv8">; + AssemblerPredicate<(all_of HasV8Ops), "armv8">; def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, - AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; + AssemblerPredicate<(all_of (not HasV8Ops)), "armv7 or earlier">; def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, - AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; + AssemblerPredicate<(all_of HasV8_1aOps), "armv8.1a">; def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, - AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; + AssemblerPredicate<(all_of HasV8_2aOps), "armv8.2a">; def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, - AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; + AssemblerPredicate<(all_of HasV8_3aOps), "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, - AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; + AssemblerPredicate<(all_of HasV8_4aOps), "armv8.4a">; def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, - AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; + AssemblerPredicate<(all_of HasV8_5aOps), "armv8.5a">; def NoVFP : Predicate<"!Subtarget->hasVFP2Base()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2Base()">, - AssemblerPredicate<"FeatureVFP2_SP", "VFP2">; + AssemblerPredicate<(all_of FeatureVFP2_SP), "VFP2">; def HasVFP3 : Predicate<"Subtarget->hasVFP3Base()">, - AssemblerPredicate<"FeatureVFP3_D16_SP", "VFP3">; + AssemblerPredicate<(all_of FeatureVFP3_D16_SP), "VFP3">; def HasVFP4 : Predicate<"Subtarget->hasVFP4Base()">, - AssemblerPredicate<"FeatureVFP4_D16_SP", "VFP4">; + AssemblerPredicate<(all_of FeatureVFP4_D16_SP), "VFP4">; def HasDPVFP : Predicate<"Subtarget->hasFP64()">, - AssemblerPredicate<"FeatureFP64", + AssemblerPredicate<(all_of FeatureFP64), "double precision VFP">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8Base()">, - AssemblerPredicate<"FeatureFPARMv8_D16_SP", "FPARMv8">; + AssemblerPredicate<(all_of FeatureFPARMv8_D16_SP), "FPARMv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, - AssemblerPredicate<"FeatureNEON", "NEON">; + AssemblerPredicate<(all_of FeatureNEON), "NEON">; def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, - AssemblerPredicate<"FeatureSHA2", "sha2">; + AssemblerPredicate<(all_of FeatureSHA2), "sha2">; def HasAES : Predicate<"Subtarget->hasAES()">, - AssemblerPredicate<"FeatureAES", "aes">; + AssemblerPredicate<(all_of FeatureAES), "aes">; def HasCrypto : Predicate<"Subtarget->hasCrypto()">, - AssemblerPredicate<"FeatureCrypto", "crypto">; + AssemblerPredicate<(all_of FeatureCrypto), "crypto">; def HasDotProd : Predicate<"Subtarget->hasDotProd()">, - AssemblerPredicate<"FeatureDotProd", "dotprod">; + AssemblerPredicate<(all_of FeatureDotProd), "dotprod">; def HasCRC : Predicate<"Subtarget->hasCRC()">, - AssemblerPredicate<"FeatureCRC", "crc">; + AssemblerPredicate<(all_of FeatureCRC), "crc">; def HasRAS : Predicate<"Subtarget->hasRAS()">, - AssemblerPredicate<"FeatureRAS", "ras">; + AssemblerPredicate<(all_of FeatureRAS), "ras">; def HasLOB : Predicate<"Subtarget->hasLOB()">, - AssemblerPredicate<"FeatureLOB", "lob">; + AssemblerPredicate<(all_of FeatureLOB), "lob">; def HasFP16 : Predicate<"Subtarget->hasFP16()">, - AssemblerPredicate<"FeatureFP16","half-float conversions">; + AssemblerPredicate<(all_of FeatureFP16),"half-float conversions">; def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, - AssemblerPredicate<"FeatureFullFP16","full half-float">; + AssemblerPredicate<(all_of FeatureFullFP16),"full half-float">; def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, - AssemblerPredicate<"FeatureFP16FML","full half-float fml">; + AssemblerPredicate<(all_of FeatureFP16FML),"full half-float fml">; def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, - AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; + AssemblerPredicate<(all_of FeatureHWDivThumb), "divide in THUMB">; def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, - AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; + AssemblerPredicate<(all_of FeatureHWDivARM), "divide in ARM">; def HasDSP : Predicate<"Subtarget->hasDSP()">, - AssemblerPredicate<"FeatureDSP", "dsp">; + AssemblerPredicate<(all_of FeatureDSP), "dsp">; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, - AssemblerPredicate<"FeatureDB", + AssemblerPredicate<(all_of FeatureDB), "data-barriers">; def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, - AssemblerPredicate<"FeatureDFB", + AssemblerPredicate<(all_of FeatureDFB), "full-data-barrier">; def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, - AssemblerPredicate<"FeatureV7Clrex", + AssemblerPredicate<(all_of FeatureV7Clrex), "v7 clrex">; def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, - AssemblerPredicate<"FeatureAcquireRelease", + AssemblerPredicate<(all_of FeatureAcquireRelease), "acquire/release">; def HasMP : Predicate<"Subtarget->hasMPExtension()">, - AssemblerPredicate<"FeatureMP", + AssemblerPredicate<(all_of FeatureMP), "mp-extensions">; def HasVirtualization: Predicate<"false">, - AssemblerPredicate<"FeatureVirtualization", + AssemblerPredicate<(all_of FeatureVirtualization), "virtualization-extensions">; def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, - AssemblerPredicate<"FeatureTrustZone", + AssemblerPredicate<(all_of FeatureTrustZone), "TrustZone">; def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, - AssemblerPredicate<"Feature8MSecExt", + AssemblerPredicate<(all_of Feature8MSecExt), "ARMv8-M Security Extensions">; def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def IsThumb : Predicate<"Subtarget->isThumb()">, - AssemblerPredicate<"ModeThumb", "thumb">; + AssemblerPredicate<(all_of ModeThumb), "thumb">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; def IsThumb2 : Predicate<"Subtarget->isThumb2()">, - AssemblerPredicate<"ModeThumb,FeatureThumb2", + AssemblerPredicate<(all_of ModeThumb, FeatureThumb2), "thumb2">; def IsMClass : Predicate<"Subtarget->isMClass()">, - AssemblerPredicate<"FeatureMClass", "armv*m">; + AssemblerPredicate<(all_of FeatureMClass), "armv*m">; def IsNotMClass : Predicate<"!Subtarget->isMClass()">, - AssemblerPredicate<"!FeatureMClass", + AssemblerPredicate<(all_of (not FeatureMClass)), "!armv*m">; def IsARM : Predicate<"!Subtarget->isThumb()">, - AssemblerPredicate<"!ModeThumb", "arm-mode">; + AssemblerPredicate<(all_of (not ModeThumb)), "arm-mode">; def IsMachO : Predicate<"Subtarget->isTargetMachO()">; def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; @@ -160,12 +160,12 @@ def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, - AssemblerPredicate<"FeatureNaClTrap", "NaCl">; + AssemblerPredicate<(all_of FeatureNaClTrap), "NaCl">; def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; def UseNegativeImmediates : Predicate<"false">, - AssemblerPredicate<"!FeatureNoNegativeImmediates", + AssemblerPredicate<(all_of (not FeatureNoNegativeImmediates)), "NegativeImmediates">; // FIXME: Eventually this will be just "hasV6T2Ops". @@ -209,4 +209,4 @@ // Armv8.5-A extensions def HasSB : Predicate<"Subtarget->hasSB()">, - AssemblerPredicate<"FeatureSB", "sb">; + AssemblerPredicate<(all_of FeatureSB), "sb">; diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -260,58 +260,58 @@ //===----------------------------------------------------------------------===// def HasSRAM : Predicate<"Subtarget->hasSRAM()">, - AssemblerPredicate<"FeatureSRAM">; + AssemblerPredicate<(all_of FeatureSRAM)>; def HasJMPCALL : Predicate<"Subtarget->hasJMPCALL()">, - AssemblerPredicate<"FeatureJMPCALL">; + AssemblerPredicate<(all_of FeatureJMPCALL)>; def HasIJMPCALL : Predicate<"Subtarget->hasIJMPCALL()">, - AssemblerPredicate<"FeatureIJMPCALL">; + AssemblerPredicate<(all_of FeatureIJMPCALL)>; def HasEIJMPCALL : Predicate<"Subtarget->hasEIJMPCALL()">, - AssemblerPredicate<"FeatureEIJMPCALL">; + AssemblerPredicate<(all_of FeatureEIJMPCALL)>; def HasADDSUBIW : Predicate<"Subtarget->hasADDSUBIW()">, - AssemblerPredicate<"FeatureADDSUBIW">; + AssemblerPredicate<(all_of FeatureADDSUBIW)>; def HasSmallStack : Predicate<"Subtarget->HasSmallStack()">, - AssemblerPredicate<"FeatureSmallStack">; + AssemblerPredicate<(all_of FeatureSmallStack)>; def HasMOVW : Predicate<"Subtarget->hasMOVW()">, - AssemblerPredicate<"FeatureMOVW">; + AssemblerPredicate<(all_of FeatureMOVW)>; def HasLPM : Predicate<"Subtarget->hasLPM()">, - AssemblerPredicate<"FeatureLPM">; + AssemblerPredicate<(all_of FeatureLPM)>; def HasLPMX : Predicate<"Subtarget->hasLPMX()">, - AssemblerPredicate<"FeatureLPMX">; + AssemblerPredicate<(all_of FeatureLPMX)>; def HasELPM : Predicate<"Subtarget->hasELPM()">, - AssemblerPredicate<"FeatureELPM">; + AssemblerPredicate<(all_of FeatureELPM)>; def HasELPMX : Predicate<"Subtarget->hasELPMX()">, - AssemblerPredicate<"FeatureELPMX">; + AssemblerPredicate<(all_of FeatureELPMX)>; def HasSPM : Predicate<"Subtarget->hasSPM()">, - AssemblerPredicate<"FeatureSPM">; + AssemblerPredicate<(all_of FeatureSPM)>; def HasSPMX : Predicate<"Subtarget->hasSPMX()">, - AssemblerPredicate<"FeatureSPMX">; + AssemblerPredicate<(all_of FeatureSPMX)>; def HasDES : Predicate<"Subtarget->hasDES()">, - AssemblerPredicate<"FeatureDES">; + AssemblerPredicate<(all_of FeatureDES)>; def SupportsRMW : Predicate<"Subtarget->supportsRMW()">, - AssemblerPredicate<"FeatureRMW">; + AssemblerPredicate<(all_of FeatureRMW)>; def SupportsMultiplication : Predicate<"Subtarget->supportsMultiplication()">, - AssemblerPredicate<"FeatureMultiplication">; + AssemblerPredicate<(all_of FeatureMultiplication)>; def HasBREAK : Predicate<"Subtarget->hasBREAK()">, - AssemblerPredicate<"FeatureBREAK">; + AssemblerPredicate<(all_of FeatureBREAK)>; def HasTinyEncoding : Predicate<"Subtarget->hasTinyEncoding()">, - AssemblerPredicate<"FeatureTinyEncoding">; + AssemblerPredicate<(all_of FeatureTinyEncoding)>; // AVR specific condition code. These correspond to AVR_*_COND in diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -92,30 +92,30 @@ def UseMEMOPS : Predicate<"HST->useMemops()">; def UseHVX64B : Predicate<"HST->useHVX64BOps()">, - AssemblerPredicate<"ExtensionHVX64B">; + AssemblerPredicate<(all_of ExtensionHVX64B)>; def UseHVX128B : Predicate<"HST->useHVX128BOps()">, - AssemblerPredicate<"ExtensionHVX128B">; + AssemblerPredicate<(all_of ExtensionHVX128B)>; def UseHVX : Predicate<"HST->useHVXOps()">, - AssemblerPredicate<"ExtensionHVXV60">; + AssemblerPredicate<(all_of ExtensionHVXV60)>; def UseHVXV60 : Predicate<"HST->useHVXV60Ops()">, - AssemblerPredicate<"ExtensionHVXV60">; + AssemblerPredicate<(all_of ExtensionHVXV60)>; def UseHVXV62 : Predicate<"HST->useHVXV62Ops()">, - AssemblerPredicate<"ExtensionHVXV62">; + AssemblerPredicate<(all_of ExtensionHVXV62)>; def UseHVXV65 : Predicate<"HST->useHVXV65Ops()">, - AssemblerPredicate<"ExtensionHVXV65">; + AssemblerPredicate<(all_of ExtensionHVXV65)>; def UseHVXV66 : Predicate<"HST->useHVXV66Ops()">, - AssemblerPredicate<"ExtensionHVXV66">; + AssemblerPredicate<(all_of ExtensionHVXV66)>; def UseHVXV67 : Predicate<"HST->useHVXV67Ops()">, - AssemblerPredicate<"ExtensionHVXV67">; + AssemblerPredicate<(all_of ExtensionHVXV67)>; def UseAudio : Predicate<"HST->useAudioOps()">, - AssemblerPredicate<"ExtensionAudio">; + AssemblerPredicate<(all_of ExtensionAudio)>; def UseZReg : Predicate<"HST->useZRegOps()">, - AssemblerPredicate<"ExtensionZReg">; + AssemblerPredicate<(all_of ExtensionZReg)>; def UseCompound : Predicate<"HST->useCompound()">; def HasPreV65 : Predicate<"HST->hasPreV65()">, - AssemblerPredicate<"FeaturePreV65">; + AssemblerPredicate<(all_of FeaturePreV65)>; def HasMemNoShuf : Predicate<"HST->hasMemNoShuf()">, - AssemblerPredicate<"FeatureMemNoShuf">; + AssemblerPredicate<(all_of FeatureMemNoShuf)>; def UseUnsafeMath : Predicate<"HST->useUnsafeMath()">; def NotOptTinyCore : Predicate<"!HST->isTinyCore() ||" "MF->getFunction().hasOptSize()"> { diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.td b/llvm/lib/Target/Hexagon/HexagonDepArch.td --- a/llvm/lib/Target/Hexagon/HexagonDepArch.td +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.td @@ -9,16 +9,16 @@ //===----------------------------------------------------------------------===// def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "Hexagon::ArchEnum::V5", "Enable Hexagon V5 architecture">; -def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<"ArchV5">; +def HasV5 : Predicate<"HST->hasV5Ops()">, AssemblerPredicate<(all_of ArchV5)>; def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "Hexagon::ArchEnum::V55", "Enable Hexagon V55 architecture">; -def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<"ArchV55">; +def HasV55 : Predicate<"HST->hasV55Ops()">, AssemblerPredicate<(all_of ArchV55)>; def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "Hexagon::ArchEnum::V60", "Enable Hexagon V60 architecture">; -def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<"ArchV60">; +def HasV60 : Predicate<"HST->hasV60Ops()">, AssemblerPredicate<(all_of ArchV60)>; def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "Hexagon::ArchEnum::V62", "Enable Hexagon V62 architecture">; -def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<"ArchV62">; +def HasV62 : Predicate<"HST->hasV62Ops()">, AssemblerPredicate<(all_of ArchV62)>; def ArchV65: SubtargetFeature<"v65", "HexagonArchVersion", "Hexagon::ArchEnum::V65", "Enable Hexagon V65 architecture">; -def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<"ArchV65">; +def HasV65 : Predicate<"HST->hasV65Ops()">, AssemblerPredicate<(all_of ArchV65)>; def ArchV66: SubtargetFeature<"v66", "HexagonArchVersion", "Hexagon::ArchEnum::V66", "Enable Hexagon V66 architecture">; -def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<"ArchV66">; +def HasV66 : Predicate<"HST->hasV66Ops()">, AssemblerPredicate<(all_of ArchV66)>; def ArchV67: SubtargetFeature<"v67", "HexagonArchVersion", "Hexagon::ArchEnum::V67", "Enable Hexagon V67 architecture">; -def HasV67 : Predicate<"HST->hasV67Ops()">, AssemblerPredicate<"ArchV67">; +def HasV67 : Predicate<"HST->hasV67Ops()">, AssemblerPredicate<(all_of ArchV67)>; diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -54,22 +54,6 @@ } //===----------------------------------------------------------------------===// -// Register File, Calling Conv, Instruction Descriptions -//===----------------------------------------------------------------------===// - -include "MipsRegisterInfo.td" -include "MipsSchedule.td" -include "MipsInstrInfo.td" -include "MipsCallingConv.td" -include "MipsRegisterBanks.td" - -// Avoid forward declaration issues. -include "MipsScheduleP5600.td" -include "MipsScheduleGeneric.td" - -def MipsInstrInfo : InstrInfo; - -//===----------------------------------------------------------------------===// // Mips Subtarget features // //===----------------------------------------------------------------------===// @@ -221,6 +205,23 @@ "UseIndirectJumpsHazard", "true", "Use indirect jump" " guards to prevent certain speculation based attacks">; + +//===----------------------------------------------------------------------===// +// Register File, Calling Conv, Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "MipsRegisterInfo.td" +include "MipsSchedule.td" +include "MipsInstrInfo.td" +include "MipsCallingConv.td" +include "MipsRegisterBanks.td" + +// Avoid forward declaration issues. +include "MipsScheduleP5600.td" +include "MipsScheduleGeneric.td" + +def MipsInstrInfo : InstrInfo; + //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td --- a/llvm/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/llvm/lib/Target/Mips/MipsDSPInstrFormats.td @@ -21,11 +21,11 @@ } def HasDSP : Predicate<"Subtarget->hasDSP()">, - AssemblerPredicate<"FeatureDSP">; + AssemblerPredicate<(all_of FeatureDSP)>; def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">, - AssemblerPredicate<"FeatureDSPR2">; + AssemblerPredicate<(all_of FeatureDSPR2)>; def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, - AssemblerPredicate<"FeatureDSPR3">; + AssemblerPredicate<(all_of FeatureDSPR3)>; class ISA_DSPR2 { list ASEPredicate = [HasDSPR2]; diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -63,15 +63,15 @@ //===----------------------------------------------------------------------===// def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, - AssemblerPredicate<"FeatureFP64Bit">; + AssemblerPredicate<(all_of FeatureFP64Bit)>; def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, - AssemblerPredicate<"!FeatureFP64Bit">; + AssemblerPredicate<(all_of (not FeatureFP64Bit))>; def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, - AssemblerPredicate<"FeatureSingleFloat">; + AssemblerPredicate<(all_of FeatureSingleFloat)>; def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, - AssemblerPredicate<"!FeatureSingleFloat">; + AssemblerPredicate<(all_of (not FeatureSingleFloat))>; def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, - AssemblerPredicate<"!FeatureSoftFloat">; + AssemblerPredicate<(all_of (not FeatureSoftFloat))>; //===----------------------------------------------------------------------===// // Mips FGR size adjectives. diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -156,69 +156,69 @@ // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// def HasMips2 : Predicate<"Subtarget->hasMips2()">, - AssemblerPredicate<"FeatureMips2">; + AssemblerPredicate<(all_of FeatureMips2)>; def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, - AssemblerPredicate<"FeatureMips3_32">; + AssemblerPredicate<(all_of FeatureMips3_32)>; def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, - AssemblerPredicate<"FeatureMips3_32r2">; + AssemblerPredicate<(all_of FeatureMips3_32r2)>; def HasMips3 : Predicate<"Subtarget->hasMips3()">, - AssemblerPredicate<"FeatureMips3">; + AssemblerPredicate<(all_of FeatureMips3)>; def NotMips3 : Predicate<"!Subtarget->hasMips3()">, - AssemblerPredicate<"!FeatureMips3">; + AssemblerPredicate<(all_of (not FeatureMips3))>; def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, - AssemblerPredicate<"FeatureMips4_32">; + AssemblerPredicate<(all_of FeatureMips4_32)>; def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, - AssemblerPredicate<"!FeatureMips4_32">; + AssemblerPredicate<(all_of (not FeatureMips4_32))>; def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, - AssemblerPredicate<"FeatureMips4_32r2">; + AssemblerPredicate<(all_of FeatureMips4_32r2)>; def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, - AssemblerPredicate<"FeatureMips5_32r2">; + AssemblerPredicate<(all_of FeatureMips5_32r2)>; def HasMips32 : Predicate<"Subtarget->hasMips32()">, - AssemblerPredicate<"FeatureMips32">; + AssemblerPredicate<(all_of FeatureMips32)>; def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, - AssemblerPredicate<"FeatureMips32r2">; + AssemblerPredicate<(all_of FeatureMips32r2)>; def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">, - AssemblerPredicate<"FeatureMips32r5">; + AssemblerPredicate<(all_of FeatureMips32r5)>; def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, - AssemblerPredicate<"FeatureMips32r6">; + AssemblerPredicate<(all_of FeatureMips32r6)>; def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, - AssemblerPredicate<"!FeatureMips32r6">; + AssemblerPredicate<(all_of (not FeatureMips32r6))>; def IsGP64bit : Predicate<"Subtarget->isGP64bit()">, - AssemblerPredicate<"FeatureGP64Bit">; + AssemblerPredicate<(all_of FeatureGP64Bit)>; def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, - AssemblerPredicate<"!FeatureGP64Bit">; + AssemblerPredicate<(all_of (not FeatureGP64Bit))>; def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">, - AssemblerPredicate<"FeaturePTR64Bit">; + AssemblerPredicate<(all_of FeaturePTR64Bit)>; def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">, - AssemblerPredicate<"!FeaturePTR64Bit">; + AssemblerPredicate<(all_of (not FeaturePTR64Bit))>; def HasMips64 : Predicate<"Subtarget->hasMips64()">, - AssemblerPredicate<"FeatureMips64">; + AssemblerPredicate<(all_of FeatureMips64)>; def NotMips64 : Predicate<"!Subtarget->hasMips64()">, - AssemblerPredicate<"!FeatureMips64">; + AssemblerPredicate<(all_of (not FeatureMips64))>; def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, - AssemblerPredicate<"FeatureMips64r2">; + AssemblerPredicate<(all_of FeatureMips64r2)>; def HasMips64r5 : Predicate<"Subtarget->hasMips64r5()">, - AssemblerPredicate<"FeatureMips64r5">; + AssemblerPredicate<(all_of FeatureMips64r5)>; def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, - AssemblerPredicate<"FeatureMips64r6">; + AssemblerPredicate<(all_of FeatureMips64r6)>; def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, - AssemblerPredicate<"!FeatureMips64r6">; + AssemblerPredicate<(all_of (not FeatureMips64r6))>; def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, - AssemblerPredicate<"FeatureMips16">; + AssemblerPredicate<(all_of FeatureMips16)>; def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">, - AssemblerPredicate<"!FeatureMips16">; + AssemblerPredicate<(all_of (not FeatureMips16))>; def HasCnMips : Predicate<"Subtarget->hasCnMips()">, - AssemblerPredicate<"FeatureCnMips">; + AssemblerPredicate<(all_of FeatureCnMips)>; def NotCnMips : Predicate<"!Subtarget->hasCnMips()">, - AssemblerPredicate<"!FeatureCnMips">; + AssemblerPredicate<(all_of (not FeatureCnMips))>; def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">, - AssemblerPredicate<"FeatureCnMipsP">; + AssemblerPredicate<(all_of FeatureCnMipsP)>; def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">, - AssemblerPredicate<"!FeatureCnMipsP">; + AssemblerPredicate<(all_of (not FeatureCnMipsP))>; def IsSym32 : Predicate<"Subtarget->hasSym32()">, - AssemblerPredicate<"FeatureSym32">; + AssemblerPredicate<(all_of FeatureSym32)>; def IsSym64 : Predicate<"!Subtarget->hasSym32()">, - AssemblerPredicate<"!FeatureSym32">; + AssemblerPredicate<(all_of (not FeatureSym32))>; def IsN64 : Predicate<"Subtarget->isABI_N64()">; def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">; def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; @@ -227,34 +227,34 @@ def UseAbs : Predicate<"Subtarget->inAbs2008Mode() ||" "TM.Options.NoNaNsFPMath">; def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, - AssemblerPredicate<"!FeatureMips16">; + AssemblerPredicate<(all_of (not FeatureMips16))>; def NotDSP : Predicate<"!Subtarget->hasDSP()">; def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, - AssemblerPredicate<"FeatureMicroMips">; + AssemblerPredicate<(all_of FeatureMicroMips)>; def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, - AssemblerPredicate<"!FeatureMicroMips">; + AssemblerPredicate<(all_of (not FeatureMicroMips))>; def IsLE : Predicate<"Subtarget->isLittle()">; def IsBE : Predicate<"!Subtarget->isLittle()">; def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; -def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; +def UseTCCInDIV : AssemblerPredicate<(all_of FeatureUseTCCInDIV)>; def HasEVA : Predicate<"Subtarget->hasEVA()">, - AssemblerPredicate<"FeatureEVA">; + AssemblerPredicate<(all_of FeatureEVA)>; def HasMSA : Predicate<"Subtarget->hasMSA()">, - AssemblerPredicate<"FeatureMSA">; + AssemblerPredicate<(all_of FeatureMSA)>; def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">, - AssemblerPredicate<"!FeatureMadd4">; + AssemblerPredicate<(all_of (not FeatureMadd4))>; def HasMT : Predicate<"Subtarget->hasMT()">, - AssemblerPredicate<"FeatureMT">; + AssemblerPredicate<(all_of FeatureMT)>; def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">, - AssemblerPredicate<"FeatureUseIndirectJumpsHazard">; + AssemblerPredicate<(all_of FeatureUseIndirectJumpsHazard)>; def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">, - AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">; + AssemblerPredicate<(all_of (not FeatureUseIndirectJumpsHazard))>; def HasCRC : Predicate<"Subtarget->hasCRC()">, - AssemblerPredicate<"FeatureCRC">; + AssemblerPredicate<(all_of FeatureCRC)>; def HasVirt : Predicate<"Subtarget->hasVirt()">, - AssemblerPredicate<"FeatureVirt">; + AssemblerPredicate<(all_of FeatureVirt)>; def HasGINV : Predicate<"Subtarget->hasGINV()">, - AssemblerPredicate<"FeatureGINV">; + AssemblerPredicate<(all_of FeatureGINV)>; // TODO: Add support for FPOpFusion::Standard def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion ==" " FPOpFusion::Fast">; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -16,21 +16,21 @@ : SubtargetFeature<"m", "HasStdExtM", "true", "'M' (Integer Multiplication and Division)">; def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, - AssemblerPredicate<"FeatureStdExtM", + AssemblerPredicate<(all_of FeatureStdExtM), "'M' (Integer Multiplication and Division)">; def FeatureStdExtA : SubtargetFeature<"a", "HasStdExtA", "true", "'A' (Atomic Instructions)">; def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, - AssemblerPredicate<"FeatureStdExtA", + AssemblerPredicate<(all_of FeatureStdExtA), "'A' (Atomic Instructions)">; def FeatureStdExtF : SubtargetFeature<"f", "HasStdExtF", "true", "'F' (Single-Precision Floating-Point)">; def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, - AssemblerPredicate<"FeatureStdExtF", + AssemblerPredicate<(all_of FeatureStdExtF), "'F' (Single-Precision Floating-Point)">; def FeatureStdExtD @@ -38,30 +38,30 @@ "'D' (Double-Precision Floating-Point)", [FeatureStdExtF]>; def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, - AssemblerPredicate<"FeatureStdExtD", + AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; def FeatureStdExtC : SubtargetFeature<"c", "HasStdExtC", "true", "'C' (Compressed Instructions)">; def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, - AssemblerPredicate<"FeatureStdExtC", + AssemblerPredicate<(all_of FeatureStdExtC), "'C' (Compressed Instructions)">; def FeatureRVCHints : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", "Enable RVC Hint Instructions.">; def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, - AssemblerPredicate<"FeatureRVCHints", + AssemblerPredicate<(all_of FeatureRVCHints), "RVC Hint Instructions">; def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, - AssemblerPredicate<"Feature64Bit", + AssemblerPredicate<(all_of Feature64Bit), "RV64I Base Instruction Set">; def IsRV32 : Predicate<"!Subtarget->is64Bit()">, - AssemblerPredicate<"!Feature64Bit", + AssemblerPredicate<(all_of (not Feature64Bit)), "RV32I Base Instruction Set">; def RV64 : HwMode<"+64bit">; @@ -71,7 +71,7 @@ : SubtargetFeature<"e", "IsRV32E", "true", "Implements RV32E (provides 16 rather than 32 GPRs)">; def IsRV32E : Predicate<"Subtarget->isRV32E()">, - AssemblerPredicate<"FeatureRV32E">; + AssemblerPredicate<(all_of FeatureRV32E)>; def FeatureRelax : SubtargetFeature<"relax", "EnableLinkerRelax", "true", diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -27,12 +27,12 @@ def Is64Bit : Predicate<"Subtarget->is64Bit()">; def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">, - AssemblerPredicate<"FeatureSoftMulDiv">; + AssemblerPredicate<(all_of FeatureSoftMulDiv)>; // HasV9 - This predicate is true when the target processor supports V9 // instructions. Note that the machine may be running in 32-bit mode. def HasV9 : Predicate<"Subtarget->isV9()">, - AssemblerPredicate<"FeatureV9">; + AssemblerPredicate<(all_of FeatureV9)>; // HasNoV9 - This predicate is true when the target doesn't have V9 // instructions. Use of this is just a hack for the isel not having proper @@ -41,11 +41,11 @@ // HasVIS - This is true when the target processor has VIS extensions. def HasVIS : Predicate<"Subtarget->isVIS()">, - AssemblerPredicate<"FeatureVIS">; + AssemblerPredicate<(all_of FeatureVIS)>; def HasVIS2 : Predicate<"Subtarget->isVIS2()">, - AssemblerPredicate<"FeatureVIS2">; + AssemblerPredicate<(all_of FeatureVIS2)>; def HasVIS3 : Predicate<"Subtarget->isVIS3()">, - AssemblerPredicate<"FeatureVIS3">; + AssemblerPredicate<(all_of FeatureVIS3)>; // HasHardQuad - This is true when the target processor supports quad floating // point instructions. @@ -58,7 +58,7 @@ // HasPWRPSR - This is true when the target processor supports partial // writes to the PSR register that only affects the ET field. def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">, - AssemblerPredicate<"FeaturePWRPSR">; + AssemblerPredicate<(all_of FeaturePWRPSR)>; // HasUMAC_SMAC - This is true when the target processor supports the // UMAC and SMAC instructions diff --git a/llvm/lib/Target/SystemZ/SystemZFeatures.td b/llvm/lib/Target/SystemZ/SystemZFeatures.td --- a/llvm/lib/Target/SystemZ/SystemZFeatures.td +++ b/llvm/lib/Target/SystemZ/SystemZFeatures.td @@ -10,9 +10,9 @@ // //===----------------------------------------------------------------------===// -class SystemZFeature +class SystemZFeature : Predicate<"Subtarget->has"##intname##"()">, - AssemblerPredicate<"Feature"##intname, extname>, + AssemblerPredicate, SubtargetFeature; class SystemZMissingFeature @@ -28,7 +28,7 @@ // This feature is added as a subtarget feature whenever the function is // compiled to use soft-float. def FeatureSoftFloat : SystemZFeature< - "soft-float", "SoftFloat", + "soft-float", "SoftFloat", (all_of FeatureSoftFloat), "Use software emulation for floating point" >; @@ -39,54 +39,54 @@ //===----------------------------------------------------------------------===// def FeatureDistinctOps : SystemZFeature< - "distinct-ops", "DistinctOps", + "distinct-ops", "DistinctOps", (all_of FeatureDistinctOps), "Assume that the distinct-operands facility is installed" >; def FeatureFastSerialization : SystemZFeature< - "fast-serialization", "FastSerialization", + "fast-serialization", "FastSerialization", (all_of FeatureFastSerialization), "Assume that the fast-serialization facility is installed" >; def FeatureFPExtension : SystemZFeature< - "fp-extension", "FPExtension", + "fp-extension", "FPExtension", (all_of FeatureFPExtension), "Assume that the floating-point extension facility is installed" >; def FeatureHighWord : SystemZFeature< - "high-word", "HighWord", + "high-word", "HighWord", (all_of FeatureHighWord), "Assume that the high-word facility is installed" >; def FeatureInterlockedAccess1 : SystemZFeature< - "interlocked-access1", "InterlockedAccess1", + "interlocked-access1", "InterlockedAccess1", (all_of FeatureInterlockedAccess1), "Assume that interlocked-access facility 1 is installed" >; def FeatureNoInterlockedAccess1 : SystemZMissingFeature<"InterlockedAccess1">; def FeatureLoadStoreOnCond : SystemZFeature< - "load-store-on-cond", "LoadStoreOnCond", + "load-store-on-cond", "LoadStoreOnCond", (all_of FeatureLoadStoreOnCond), "Assume that the load/store-on-condition facility is installed" >; def FeatureNoLoadStoreOnCond : SystemZMissingFeature<"LoadStoreOnCond">; def FeaturePopulationCount : SystemZFeature< - "population-count", "PopulationCount", + "population-count", "PopulationCount", (all_of FeaturePopulationCount), "Assume that the population-count facility is installed" >; def FeatureMessageSecurityAssist3 : SystemZFeature< - "message-security-assist-extension3", "MessageSecurityAssist3", + "message-security-assist-extension3", "MessageSecurityAssist3", (all_of FeatureMessageSecurityAssist3), "Assume that the message-security-assist extension facility 3 is installed" >; def FeatureMessageSecurityAssist4 : SystemZFeature< - "message-security-assist-extension4", "MessageSecurityAssist4", + "message-security-assist-extension4", "MessageSecurityAssist4", (all_of FeatureMessageSecurityAssist4), "Assume that the message-security-assist extension facility 4 is installed" >; def FeatureResetReferenceBitsMultiple : SystemZFeature< - "reset-reference-bits-multiple", "ResetReferenceBitsMultiple", + "reset-reference-bits-multiple", "ResetReferenceBitsMultiple", (all_of FeatureResetReferenceBitsMultiple), "Assume that the reset-reference-bits-multiple facility is installed" >; @@ -110,37 +110,37 @@ //===----------------------------------------------------------------------===// def FeatureExecutionHint : SystemZFeature< - "execution-hint", "ExecutionHint", + "execution-hint", "ExecutionHint", (all_of FeatureExecutionHint), "Assume that the execution-hint facility is installed" >; def FeatureLoadAndTrap : SystemZFeature< - "load-and-trap", "LoadAndTrap", + "load-and-trap", "LoadAndTrap", (all_of FeatureLoadAndTrap), "Assume that the load-and-trap facility is installed" >; def FeatureMiscellaneousExtensions : SystemZFeature< - "miscellaneous-extensions", "MiscellaneousExtensions", + "miscellaneous-extensions", "MiscellaneousExtensions", (all_of FeatureMiscellaneousExtensions), "Assume that the miscellaneous-extensions facility is installed" >; def FeatureProcessorAssist : SystemZFeature< - "processor-assist", "ProcessorAssist", + "processor-assist", "ProcessorAssist", (all_of FeatureProcessorAssist), "Assume that the processor-assist facility is installed" >; def FeatureTransactionalExecution : SystemZFeature< - "transactional-execution", "TransactionalExecution", + "transactional-execution", "TransactionalExecution", (all_of FeatureTransactionalExecution), "Assume that the transactional-execution facility is installed" >; def FeatureDFPZonedConversion : SystemZFeature< - "dfp-zoned-conversion", "DFPZonedConversion", + "dfp-zoned-conversion", "DFPZonedConversion", (all_of FeatureDFPZonedConversion), "Assume that the DFP zoned-conversion facility is installed" >; def FeatureEnhancedDAT2 : SystemZFeature< - "enhanced-dat-2", "EnhancedDAT2", + "enhanced-dat-2", "EnhancedDAT2", (all_of FeatureEnhancedDAT2), "Assume that the enhanced-DAT facility 2 is installed" >; @@ -161,27 +161,27 @@ //===----------------------------------------------------------------------===// def FeatureLoadAndZeroRightmostByte : SystemZFeature< - "load-and-zero-rightmost-byte", "LoadAndZeroRightmostByte", + "load-and-zero-rightmost-byte", "LoadAndZeroRightmostByte", (all_of FeatureLoadAndZeroRightmostByte), "Assume that the load-and-zero-rightmost-byte facility is installed" >; def FeatureLoadStoreOnCond2 : SystemZFeature< - "load-store-on-cond-2", "LoadStoreOnCond2", + "load-store-on-cond-2", "LoadStoreOnCond2", (all_of FeatureLoadStoreOnCond2), "Assume that the load/store-on-condition facility 2 is installed" >; def FeatureMessageSecurityAssist5 : SystemZFeature< - "message-security-assist-extension5", "MessageSecurityAssist5", + "message-security-assist-extension5", "MessageSecurityAssist5", (all_of FeatureMessageSecurityAssist5), "Assume that the message-security-assist extension facility 5 is installed" >; def FeatureDFPPackedConversion : SystemZFeature< - "dfp-packed-conversion", "DFPPackedConversion", + "dfp-packed-conversion", "DFPPackedConversion", (all_of FeatureDFPPackedConversion), "Assume that the DFP packed-conversion facility is installed" >; def FeatureVector : SystemZFeature< - "vector", "Vector", + "vector", "Vector", (all_of FeatureVector), "Assume that the vectory facility is installed" >; def FeatureNoVector : SystemZMissingFeature<"Vector">; @@ -201,38 +201,38 @@ //===----------------------------------------------------------------------===// def FeatureMiscellaneousExtensions2 : SystemZFeature< - "miscellaneous-extensions-2", "MiscellaneousExtensions2", + "miscellaneous-extensions-2", "MiscellaneousExtensions2", (all_of FeatureMiscellaneousExtensions2), "Assume that the miscellaneous-extensions facility 2 is installed" >; def FeatureGuardedStorage : SystemZFeature< - "guarded-storage", "GuardedStorage", + "guarded-storage", "GuardedStorage", (all_of FeatureGuardedStorage), "Assume that the guarded-storage facility is installed" >; def FeatureMessageSecurityAssist7 : SystemZFeature< - "message-security-assist-extension7", "MessageSecurityAssist7", + "message-security-assist-extension7", "MessageSecurityAssist7", (all_of FeatureMessageSecurityAssist7), "Assume that the message-security-assist extension facility 7 is installed" >; def FeatureMessageSecurityAssist8 : SystemZFeature< - "message-security-assist-extension8", "MessageSecurityAssist8", + "message-security-assist-extension8", "MessageSecurityAssist8", (all_of FeatureMessageSecurityAssist8), "Assume that the message-security-assist extension facility 8 is installed" >; def FeatureVectorEnhancements1 : SystemZFeature< - "vector-enhancements-1", "VectorEnhancements1", + "vector-enhancements-1", "VectorEnhancements1", (all_of FeatureVectorEnhancements1), "Assume that the vector enhancements facility 1 is installed" >; def FeatureNoVectorEnhancements1 : SystemZMissingFeature<"VectorEnhancements1">; def FeatureVectorPackedDecimal : SystemZFeature< - "vector-packed-decimal", "VectorPackedDecimal", + "vector-packed-decimal", "VectorPackedDecimal", (all_of FeatureVectorPackedDecimal), "Assume that the vector packed decimal facility is installed" >; def FeatureInsertReferenceBitsMultiple : SystemZFeature< - "insert-reference-bits-multiple", "InsertReferenceBitsMultiple", + "insert-reference-bits-multiple", "InsertReferenceBitsMultiple", (all_of FeatureInsertReferenceBitsMultiple), "Assume that the insert-reference-bits-multiple facility is installed" >; @@ -253,32 +253,32 @@ //===----------------------------------------------------------------------===// def FeatureMiscellaneousExtensions3 : SystemZFeature< - "miscellaneous-extensions-3", "MiscellaneousExtensions3", + "miscellaneous-extensions-3", "MiscellaneousExtensions3", (all_of FeatureMiscellaneousExtensions3), "Assume that the miscellaneous-extensions facility 3 is installed" >; def FeatureMessageSecurityAssist9 : SystemZFeature< - "message-security-assist-extension9", "MessageSecurityAssist9", + "message-security-assist-extension9", "MessageSecurityAssist9", (all_of FeatureMessageSecurityAssist9), "Assume that the message-security-assist extension facility 9 is installed" >; def FeatureVectorEnhancements2 : SystemZFeature< - "vector-enhancements-2", "VectorEnhancements2", + "vector-enhancements-2", "VectorEnhancements2", (all_of FeatureVectorEnhancements2), "Assume that the vector enhancements facility 2 is installed" >; def FeatureVectorPackedDecimalEnhancement : SystemZFeature< - "vector-packed-decimal-enhancement", "VectorPackedDecimalEnhancement", + "vector-packed-decimal-enhancement", "VectorPackedDecimalEnhancement", (all_of FeatureVectorPackedDecimalEnhancement), "Assume that the vector packed decimal enhancement facility is installed" >; def FeatureEnhancedSort : SystemZFeature< - "enhanced-sort", "EnhancedSort", + "enhanced-sort", "EnhancedSort", (all_of FeatureEnhancedSort), "Assume that the enhanced-sort facility is installed" >; def FeatureDeflateConversion : SystemZFeature< - "deflate-conversion", "DeflateConversion", + "deflate-conversion", "DeflateConversion", (all_of FeatureDeflateConversion), "Assume that the deflate-conversion facility is installed" >; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -24,47 +24,47 @@ def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">, - AssemblerPredicate<"FeatureSIMD128", "simd128">; + AssemblerPredicate<(all_of FeatureSIMD128), "simd128">; def HasUnimplementedSIMD128 : Predicate<"Subtarget->hasUnimplementedSIMD128()">, - AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">; + AssemblerPredicate<(all_of FeatureUnimplementedSIMD128), "unimplemented-simd128">; def HasAtomics : Predicate<"Subtarget->hasAtomics()">, - AssemblerPredicate<"FeatureAtomics", "atomics">; + AssemblerPredicate<(all_of FeatureAtomics), "atomics">; def HasMultivalue : Predicate<"Subtarget->hasMultivalue()">, - AssemblerPredicate<"FeatureMultivalue", "multivalue">; + AssemblerPredicate<(all_of FeatureMultivalue), "multivalue">; def HasNontrappingFPToInt : Predicate<"Subtarget->hasNontrappingFPToInt()">, - AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">; + AssemblerPredicate<(all_of FeatureNontrappingFPToInt), "nontrapping-fptoint">; def NotHasNontrappingFPToInt : Predicate<"!Subtarget->hasNontrappingFPToInt()">, - AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">; + AssemblerPredicate<(all_of (not FeatureNontrappingFPToInt)), "nontrapping-fptoint">; def HasSignExt : Predicate<"Subtarget->hasSignExt()">, - AssemblerPredicate<"FeatureSignExt", "sign-ext">; + AssemblerPredicate<(all_of FeatureSignExt), "sign-ext">; def HasTailCall : Predicate<"Subtarget->hasTailCall()">, - AssemblerPredicate<"FeatureTailCall", "tail-call">; + AssemblerPredicate<(all_of FeatureTailCall), "tail-call">; def HasExceptionHandling : Predicate<"Subtarget->hasExceptionHandling()">, - AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">; + AssemblerPredicate<(all_of FeatureExceptionHandling), "exception-handling">; def HasBulkMemory : Predicate<"Subtarget->hasBulkMemory()">, - AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">; + AssemblerPredicate<(all_of FeatureBulkMemory), "bulk-memory">; def HasReferenceTypes : Predicate<"Subtarget->hasReferenceTypes()">, - AssemblerPredicate<"FeatureReferenceTypes", "reference-types">; + AssemblerPredicate<(all_of FeatureReferenceTypes), "reference-types">; //===----------------------------------------------------------------------===// // WebAssembly-specific DAG Node Types. diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -956,17 +956,17 @@ def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, - AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; + AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">; def In64BitMode : Predicate<"Subtarget->is64Bit()">, - AssemblerPredicate<"Mode64Bit", "64-bit mode">; + AssemblerPredicate<(all_of Mode64Bit), "64-bit mode">; def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; def In16BitMode : Predicate<"Subtarget->is16Bit()">, - AssemblerPredicate<"Mode16Bit", "16-bit mode">; + AssemblerPredicate<(all_of Mode16Bit), "16-bit mode">; def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, - AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; + AssemblerPredicate<(all_of (not Mode16Bit)), "Not 16-bit mode">; def In32BitMode : Predicate<"Subtarget->is32Bit()">, - AssemblerPredicate<"Mode32Bit", "32-bit mode">; + AssemblerPredicate<(all_of Mode32Bit), "32-bit mode">; def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" diff --git a/llvm/test/TableGen/AsmPredicateCombining.td b/llvm/test/TableGen/AsmPredicateCombining.td new file mode 100644 --- /dev/null +++ b/llvm/test/TableGen/AsmPredicateCombining.td @@ -0,0 +1,104 @@ +// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \ +// RUN: FileCheck --check-prefix=DISASS %s +// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \ +// RUN: FileCheck --check-prefix=MATCHER %s +// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \ +// RUN: FileCheck --check-prefix=WRITER %s + +// Check that combining conditions in AssemblerPredicate generates the correct +// output when using both the (all_of) AND operator, and the (any_of) OR +// operator. + +include "llvm/Target/Target.td" + +def archInstrInfo : InstrInfo { } +def archAsmWriter : AsmWriter { + int PassSubtarget = 1; +} + +def arch : Target { + let InstructionSet = archInstrInfo; + let AssemblyWriters = [archAsmWriter]; +} + +let Namespace = "arch" in { + def R0 : Register<"r0">; + def R1 : Register<"r1">; + def R2 : Register<"r2">; + def R3 : Register<"r3">; + def R4 : Register<"r4">; +} +def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>; + +class TestInsn Preds> : Instruction { + let Size = 2; + let OutOperandList = (outs); + let InOperandList = (ins Regs:$r); + field bits<16> Inst; + let Inst = Opc; + let AsmString = NAME # " $r"; + field bits<16> SoftFail = 0; + let Predicates = Preds; +} + + +def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">; +def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">; +def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">; +def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">; +def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">; + +def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>; +def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>; +def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>; +// MATCHER: if (FB[arch::AsmCond1]) +// MATCHER-NEXT: Features.set(Feature_AsmPred1Bit); +// MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b]) +// MATCHER-NEXT: Features.set(Feature_AsmPred2Bit); +// MATCHER-NEXT: if ((FB[arch::AsmCond3a] || FB[arch::AsmCond3b])) +// MATCHER-NEXT: Features.set(Feature_AsmPred3Bit); + +def insn1 : TestInsn<1, [AsmPred1]>; +// DISASS: return (Bits[arch::AsmCond1]); + +def insn2 : TestInsn<2, [AsmPred2]>; +// DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]) + +def insn3 : TestInsn<3, [AsmPred3]>; +// DISASS: return ((Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])) + +def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>; +// DISASS: return (Bits[arch::AsmCond1] && Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]) + +def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>; +// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])) + +def insn6 : TestInsn<6, []>; +def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; } +// WRITER: // (insn6 R0) +// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1}, +def : InstAlias<"alias2", (insn6 R1)> { let Predicates = [AsmPred2]; } +// WRITER: // (insn6 R1) +// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R1}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b}, +def : InstAlias<"alias3", (insn6 R2)> { let Predicates = [AsmPred3]; } +// WRITER: // (insn6 R2) +// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R2}, +// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a}, +// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b}, +// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0}, +def : InstAlias<"alias4", (insn6 R3)> { let Predicates = [AsmPred1, AsmPred2]; } +// WRITER: // (insn6 R3) +// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R3}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b}, +def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; } +// WRITER: // (insn6 R4) +// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4}, +// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1}, +// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a}, +// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b}, +// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0}, diff --git a/llvm/test/TableGen/AsmPredicateCombiningRISCV.td b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td new file mode 100644 --- /dev/null +++ b/llvm/test/TableGen/AsmPredicateCombiningRISCV.td @@ -0,0 +1,100 @@ +// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \ +// RUN: FileCheck --check-prefix=COMPRESS %s + +// Check that combining conditions in AssemblerPredicate generates the correct +// output when using both the (all_of) AND operator, and the (any_of) OR +// operator in the RISC-V specific instruction compressor. + +include "llvm/Target/Target.td" + +def archInstrInfo : InstrInfo { } +def archAsmWriter : AsmWriter { + int PassSubtarget = 1; +} + +def arch : Target { + let InstructionSet = archInstrInfo; + let AssemblyWriters = [archAsmWriter]; +} + +let Namespace = "arch" in { + def R0 : Register<"r0">; +} +def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>; + +class RVInst Preds> : Instruction { + let Size = 4; + let OutOperandList = (outs); + let InOperandList = (ins Regs:$r); + field bits<32> Inst; + let Inst = Opc; + let AsmString = NAME # " $r"; + field bits<32> SoftFail = 0; + let Predicates = Preds; +} +class RVInst16 Preds> : Instruction { + let Size = 2; + let OutOperandList = (outs); + let InOperandList = (ins Regs:$r); + field bits<16> Inst; + let Inst = Opc; + let AsmString = NAME # " $r"; + field bits<16> SoftFail = 0; + let Predicates = Preds; +} + +def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">; +def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">; +def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">; +def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">; +def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">; + +def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>; +def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>; +def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>; + +def BigInst : RVInst<1, [AsmPred1]>; + +class CompressPat predicates> { + dag Input = input; + dag Output = output; + list Predicates = predicates; +} + +// COMPRESS-LABEL: static bool compressInst +// COMPRESS: case arch::BigInst +def SmallInst1 : RVInst16<1, []>; +def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>; +// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && +// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: // SmallInst1 $r + +def SmallInst2 : RVInst16<2, []>; +def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>; +// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] && +// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && +// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: // SmallInst2 $r + +def SmallInst3 : RVInst16<2, []>; +def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>; +// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && +// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: // SmallInst3 $r + +def SmallInst4 : RVInst16<2, []>; +def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>; +// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && +// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] && +// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && +// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: // SmallInst4 $r + +def SmallInst5 : RVInst16<2, []>; +def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>; +// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && +// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && +// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { +// COMPRESS-NEXT: // SmallInst5 $r + +// COMPRESS-LABEL: static bool uncompressInst diff --git a/llvm/test/TableGen/AsmPredicateCondsEmission.td b/llvm/test/TableGen/AsmPredicateCondsEmission.td --- a/llvm/test/TableGen/AsmPredicateCondsEmission.td +++ b/llvm/test/TableGen/AsmPredicateCondsEmission.td @@ -12,9 +12,10 @@ let InstructionSet = archInstrInfo; } +def AssemblerCondition2 : SubtargetFeature<"cond2", "cond2", "true", "">; def Pred1 : Predicate<"Condition1">; def Pred2 : Predicate<"Condition2">, - AssemblerPredicate<"AssemblerCondition2">; + AssemblerPredicate<(all_of AssemblerCondition2)>; def foo : Instruction { let Size = 2; diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp --- a/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -941,21 +941,35 @@ for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) { Record *R = *I; - StringRef AsmCondString = R->getValueAsString("AssemblerCondString"); - - // AsmCondString has syntax [!]F(,[!]F)* - SmallVector Ops; - SplitString(AsmCondString, Ops, ","); - assert(!Ops.empty() && "AssemblerCondString cannot be empty"); - - for (StringRef Op : Ops) { - assert(!Op.empty() && "Empty operator"); - bool IsNeg = Op[0] == '!'; - StringRef Feature = Op.drop_front(IsNeg ? 1 : 0); - IAP.addCond( - std::string(formatv("AliasPatternCond::K_{0}Feature, {1}::{2}", - IsNeg ? "Neg" : "", Namespace, Feature))); + const DagInit *D = R->getValueAsDag("AssemblerCondDag"); + std::string CombineType = D->getOperator()->getAsString(); + if (CombineType != "any_of" && CombineType != "all_of") + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + if (D->getNumArgs() == 0) + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + bool IsOr = CombineType == "any_of"; + + for (auto *Arg : D->getArgs()) { + bool IsNeg = false; + if (auto *NotArg = dyn_cast(Arg)) { + if (NotArg->getOperator()->getAsString() != "not" || + NotArg->getNumArgs() != 1) + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + Arg = NotArg->getArg(0); + IsNeg = true; + } + if (!isa(Arg) || + !cast(Arg)->getDef()->isSubClassOf("SubtargetFeature")) + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + + IAP.addCond(std::string(formatv( + "AliasPatternCond::K_{0}{1}Feature, {2}::{3}", IsOr ? "Or" : "", + IsNeg ? "Neg" : "", Namespace, Arg->getAsString()))); } + // If an AssemblerPredicate with ors is used, note end of list should + // these be combined. + if (IsOr) + IAP.addCond("AliasPatternCond::K_EndOrFeatures, 0"); } IAPrinterMap[Aliases.first].push_back(std::move(IAP)); diff --git a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp --- a/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -1182,15 +1182,6 @@ return (unsigned)(P - Decoders.begin()); } -static void emitSinglePredicateMatch(raw_ostream &o, StringRef str, - const std::string &PredicateNamespace) { - if (str[0] == '!') - o << "!Bits[" << PredicateNamespace << "::" - << str.slice(1,str.size()) << "]"; - else - o << "Bits[" << PredicateNamespace << "::" << str << "]"; -} - bool FilterChooser::emitPredicateMatch(raw_ostream &o, unsigned &Indentation, unsigned Opc) const { ListInit *Predicates = @@ -1201,21 +1192,50 @@ if (!Pred->getValue("AssemblerMatcherPredicate")) continue; - StringRef P = Pred->getValueAsString("AssemblerCondString"); - - if (P.empty()) + if (!dyn_cast(Pred->getValue("AssemblerCondDag")->getValue())) continue; + const DagInit *D = Pred->getValueAsDag("AssemblerCondDag"); + std::string CombineType = D->getOperator()->getAsString(); + if (CombineType != "any_of" && CombineType != "all_of") + PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!"); + if (D->getNumArgs() == 0) + PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!"); + bool IsOr = CombineType == "any_of"; + if (!IsFirstEmission) o << " && "; - std::pair pairs = P.split(','); - while (!pairs.second.empty()) { - emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace); - o << " && "; - pairs = pairs.second.split(','); + if (IsOr) + o << "("; + + bool First = true; + for (auto *Arg : D->getArgs()) { + if (!First) { + if (IsOr) + o << " || "; + else + o << " && "; + } + if (auto *NotArg = dyn_cast(Arg)) { + if (NotArg->getOperator()->getAsString() != "not" || + NotArg->getNumArgs() != 1) + PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!"); + Arg = NotArg->getArg(0); + o << "!"; + } + if (!isa(Arg) || + !cast(Arg)->getDef()->isSubClassOf("SubtargetFeature")) + PrintFatalError(Pred->getLoc(), "Invalid AssemblerCondDag!"); + o << "Bits[" << Emitter->PredicateNamespace << "::" << Arg->getAsString() + << "]"; + + First = false; } - emitSinglePredicateMatch(o, pairs.first, Emitter->PredicateNamespace); + + if (IsOr) + o << ")"; + IsFirstEmission = false; } return !Predicates->empty(); @@ -1229,12 +1249,8 @@ if (!Pred->getValue("AssemblerMatcherPredicate")) continue; - StringRef P = Pred->getValueAsString("AssemblerCondString"); - - if (P.empty()) - continue; - - return true; + if (dyn_cast(Pred->getValue("AssemblerCondDag")->getValue())) + return true; } return false; } diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp --- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp +++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp @@ -474,19 +474,40 @@ SourceOperandMap, DestOperandMap)); } -static void getReqFeatures(std::set &FeaturesSet, - const std::vector &ReqFeatures) { +static void +getReqFeatures(std::set> &FeaturesSet, + std::set>> &AnyOfFeatureSets, + const std::vector &ReqFeatures) { for (auto &R : ReqFeatures) { - StringRef AsmCondString = R->getValueAsString("AssemblerCondString"); - - // AsmCondString has syntax [!]F(,[!]F)* - SmallVector Ops; - SplitString(AsmCondString, Ops, ","); - assert(!Ops.empty() && "AssemblerCondString cannot be empty"); - for (auto &Op : Ops) { - assert(!Op.empty() && "Empty operator"); - FeaturesSet.insert(Op); + const DagInit *D = R->getValueAsDag("AssemblerCondDag"); + std::string CombineType = D->getOperator()->getAsString(); + if (CombineType != "any_of" && CombineType != "all_of") + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + if (D->getNumArgs() == 0) + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + bool IsOr = CombineType == "any_of"; + std::set> AnyOfSet; + + for (auto *Arg : D->getArgs()) { + bool IsNot = false; + if (auto *NotArg = dyn_cast(Arg)) { + if (NotArg->getOperator()->getAsString() != "not" || + NotArg->getNumArgs() != 1) + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + Arg = NotArg->getArg(0); + IsNot = true; + } + if (!isa(Arg) || + !cast(Arg)->getDef()->isSubClassOf("SubtargetFeature")) + PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); + if (IsOr) + AnyOfSet.insert({IsNot, cast(Arg)->getDef()->getName()}); + else + FeaturesSet.insert({IsNot, cast(Arg)->getDef()->getName()}); } + + if (IsOr) + AnyOfFeatureSets.insert(AnyOfSet); } } @@ -651,9 +672,10 @@ CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n"; } - std::set FeaturesSet; + std::set> FeaturesSet; + std::set>> AnyOfFeatureSets; // Add CompressPat required features. - getReqFeatures(FeaturesSet, CompressPat.PatReqFeatures); + getReqFeatures(FeaturesSet, AnyOfFeatureSets, CompressPat.PatReqFeatures); // Add Dest instruction required features. std::vector ReqFeatures; @@ -661,19 +683,28 @@ copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) { return R->getValueAsBit("AssemblerMatcherPredicate"); }); - getReqFeatures(FeaturesSet, ReqFeatures); + getReqFeatures(FeaturesSet, AnyOfFeatureSets, ReqFeatures); // Emit checks for all required features. for (auto &Op : FeaturesSet) { - if (Op[0] == '!') - CondStream.indent(6) << ("!STI.getFeatureBits()[" + Namespace + - "::" + Op.substr(1) + "]") - .str() + - " &&\n"; - else - CondStream.indent(6) - << ("STI.getFeatureBits()[" + Namespace + "::" + Op + "]").str() + - " &&\n"; + StringRef Not = Op.first ? "!" : ""; + CondStream.indent(6) + << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second + "]").str() + + " &&\n"; + } + + // Emit checks for all required feature groups. + for (auto &Set : AnyOfFeatureSets) { + CondStream.indent(6) << "("; + for (auto &Op : Set) { + bool isLast = &Op == &*Set.rbegin(); + StringRef Not = Op.first ? "!" : ""; + CondStream << Not << ("STI.getFeatureBits()[" + Namespace + "::" + Op.second + + "]").str(); + if (!isLast) + CondStream << " || "; + } + CondStream << ") &&\n"; } // Start Source Inst operands validation. diff --git a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp b/llvm/utils/TableGen/SubtargetFeatureInfo.cpp --- a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp +++ b/llvm/utils/TableGen/SubtargetFeatureInfo.cpp @@ -119,33 +119,43 @@ const SubtargetFeatureInfo &SFI = SF.second; OS << " if ("; - std::string CondStorage = - std::string(SFI.TheDef->getValueAsString("AssemblerCondString")); - StringRef Conds = CondStorage; - std::pair Comma = Conds.split(','); - bool First = true; - do { - if (!First) - OS << " && "; - - bool Neg = false; - StringRef Cond = Comma.first; - if (Cond[0] == '!') { - Neg = true; - Cond = Cond.substr(1); - } + const DagInit *D = SFI.TheDef->getValueAsDag("AssemblerCondDag"); + std::string CombineType = D->getOperator()->getAsString(); + if (CombineType != "any_of" && CombineType != "all_of") + PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!"); + if (D->getNumArgs() == 0) + PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!"); + bool IsOr = CombineType == "any_of"; + + if (IsOr) OS << "("; - if (Neg) - OS << "!"; - OS << "FB[" << TargetName << "::" << Cond << "])"; - if (Comma.second.empty()) - break; + bool First = true; + for (auto *Arg : D->getArgs()) { + if (!First) { + if (IsOr) + OS << " || "; + else + OS << " && "; + } + if (auto *NotArg = dyn_cast(Arg)) { + if (NotArg->getOperator()->getAsString() != "not" || + NotArg->getNumArgs() != 1) + PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!"); + Arg = NotArg->getArg(0); + OS << "!"; + } + if (!isa(Arg) || + !cast(Arg)->getDef()->isSubClassOf("SubtargetFeature")) + PrintFatalError(SFI.TheDef->getLoc(), "Invalid AssemblerCondDag!"); + OS << "FB[" << TargetName << "::" << Arg->getAsString() << "]"; First = false; - Comma = Comma.second.split(','); - } while (true); + } + + if (IsOr) + OS << ")"; OS << ")\n"; OS << " Features.set(" << SFI.getEnumBitName() << ");\n";