Index: llvm/include/llvm/CodeGen/TargetInstrInfo.h =================================================================== --- llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -1306,6 +1306,16 @@ /// Returns true if the instruction is already predicated. virtual bool isPredicated(const MachineInstr &MI) const { return false; } + /// Returns the name for the specified condition code + virtual const char *getPredicateByName(int CC) const {return nullptr; }; + + // Returns a MIRPrinter comment for this machine operand. + virtual const char *createMIROperandComment(const MachineInstr &MI, + const MachineOperand &Op, + unsigned OpIdx) const { + return nullptr; + }; + /// Returns true if the instruction is a /// terminator instruction that has not been predicated. virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const; Index: llvm/lib/CodeGen/MIRParser/MILexer.cpp =================================================================== --- llvm/lib/CodeGen/MIRParser/MILexer.cpp +++ llvm/lib/CodeGen/MIRParser/MILexer.cpp @@ -104,6 +104,19 @@ return C; } +/// Machine operands can have comments, enclosed between '[' and ']'. +/// This eats up all tokens, including the brackets. +static Cursor skipMachineOperandComment(Cursor C) { + if (C.peek() != '[') + return C; + + while (C.peek() != ']') + C.advance(); + + C.advance(); + return C; +} + /// Return true if the given character satisfies the following regular /// expression: [-a-zA-Z$._0-9] static bool isIdentifierChar(char C) { @@ -691,6 +704,8 @@ return C.remaining(); } + C = skipMachineOperandComment(C); + if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback)) return R.remaining(); if (Cursor R = maybeLexIdentifier(C, Token)) Index: llvm/lib/CodeGen/MIRPrinter.cpp =================================================================== --- llvm/lib/CodeGen/MIRPrinter.cpp +++ llvm/lib/CodeGen/MIRPrinter.cpp @@ -162,8 +162,9 @@ void print(const MachineInstr &MI); void printStackObjectReference(int FrameIndex); void print(const MachineInstr &MI, unsigned OpIdx, - const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies, - LLT TypeToPrint, bool PrintDef = true); + const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, + bool ShouldPrintRegisterTies, LLT TypeToPrint, + bool PrintDef = true); }; } // end namespace llvm @@ -721,7 +722,7 @@ ++I) { if (I) OS << ", "; - print(MI, I, TRI, ShouldPrintRegisterTies, + print(MI, I, TRI, TII, ShouldPrintRegisterTies, MI.getTypeToPrint(I, PrintedTypes, MRI), /*PrintDef=*/false); } @@ -763,7 +764,7 @@ for (; I < E; ++I) { if (NeedComma) OS << ", "; - print(MI, I, TRI, ShouldPrintRegisterTies, + print(MI, I, TRI, TII, ShouldPrintRegisterTies, MI.getTypeToPrint(I, PrintedTypes, MRI)); NeedComma = true; } @@ -822,11 +823,18 @@ Operand.Name); } +static std::string formatOperandComment(const char *C) { + return std::string(" [" + std::string(C) + "]"); +} + void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo *TRI, + const TargetInstrInfo *TII, bool ShouldPrintRegisterTies, LLT TypeToPrint, bool PrintDef) { const MachineOperand &Op = MI.getOperand(OpIdx); + const char *MOComment = TII->createMIROperandComment(MI, Op, OpIdx); + switch (Op.getType()) { case MachineOperand::MO_Immediate: if (MI.isOperandSubregIdx(OpIdx)) { @@ -858,6 +866,8 @@ const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo(); Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false, ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII); + if (MOComment) + OS << formatOperandComment(MOComment); break; } case MachineOperand::MO_FrameIndex: Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -146,6 +146,12 @@ // Predication support. bool isPredicated(const MachineInstr &MI) const override; + // MIR (printing) helpers + const char *getPredicateByName(int CC) const override; + const char *createMIROperandComment(const MachineInstr &MI, + const MachineOperand &Op, + unsigned OpIdx) const override; + ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { int PIdx = MI.findFirstPredOperandIdx(); return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm() Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -495,6 +495,44 @@ return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL; } +const char *ARMBaseInstrInfo::getPredicateByName(int CC) const { + switch (CC) { + case 0: return "equal"; + case 1: return "notequal"; + case 2: return "highersame"; + case 3: return "lower"; + case 4: return "minus"; + case 5: return "plus"; + case 6: return "overflow"; + case 7: return "nooverflow"; + case 8: return "higher"; + case 9: return "lowersame"; + case 10: return "greaterequal"; + case 11: return "less"; + case 12: return "greater"; + case 13: return "lessequal"; + case 14: return "always"; + default: + llvm_unreachable("unexpected condition code"); + } +} + +const char *ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI, + const MachineOperand &Op, + unsigned OpIdx) const { + // Only support immediates for now + if (Op.getType() != MachineOperand::MO_Immediate) + return nullptr; + + // And print its corresponding condition code if the immediate is a predicate + int FirstPredOp = MI.findFirstPredOperandIdx(); + if (FirstPredOp != (int) OpIdx) + return nullptr; + if (const char *PredName = getPredicateByName(Op.getImm())) + return PredName; + return nullptr; +} + bool ARMBaseInstrInfo::PredicateInstruction( MachineInstr &MI, ArrayRef Pred) const { unsigned Opc = MI.getOpcode(); Index: llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir =================================================================== --- llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple thumbv7 -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s --- | ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' @@ -117,6 +118,38 @@ - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr', callee-saved-restored: false } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7', callee-saved-restored: true } body: | + ; CHECK-LABEL: name: f + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: liveins: $r0, $r1, $r2, $r3, $lr, $r7 + ; CHECK: DBG_VALUE $r0, $noreg, !22, !DIExpression(), debug-location !26 + ; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26 + ; CHECK: DBG_VALUE $r2, $noreg, !24, !DIExpression(), debug-location !26 + ; CHECK: DBG_VALUE $r3, $noreg, !25, !DIExpression(), debug-location !26 + ; CHECK: t2CMPri $r3, 4, 14 [always], $noreg, implicit-def $cpsr, debug-location !29 + ; CHECK: t2Bcc %bb.2, 2 [highersame], killed $cpsr + ; CHECK: bb.1: + ; CHECK: liveins: $lr, $r7 + ; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26 + ; CHECK: $r0 = t2MOVi -1, 14 [always], $noreg, $noreg + ; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0, debug-location !32 + ; CHECK: bb.2.if.end: + ; CHECK: liveins: $r0, $r2, $r3, $r7, $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: DBG_VALUE $r0, $noreg, !22, !DIExpression(), debug-location !26 + ; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26 + ; CHECK: DBG_VALUE $r2, $noreg, !24, !DIExpression(), debug-location !26 + ; CHECK: DBG_VALUE $r3, $noreg, !25, !DIExpression(), debug-location !26 + ; CHECK: $r1 = COPY killed $r2, debug-location !30 + ; CHECK: DBG_VALUE $r1, $noreg, !23, !DIExpression(), debug-location !26 + ; CHECK: $r2 = COPY killed $r3, debug-location !30 + ; CHECK: tBL 14 [always], $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp, debug-location !30 + ; CHECK: $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r7, def $pc, implicit $r0 bb.0.entry: liveins: $r0, $r1, $r2, $r3, $lr, $r7 @@ -154,6 +187,5 @@ $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr tBX_RET 14, $noreg, implicit $r0, debug-location !34 # Verify that the DBG_VALUE is ignored. -# CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll +++ llvm/test/CodeGen/ARM/GlobalISel/arm-call-lowering.ll @@ -9,12 +9,12 @@ ; V5T: %[[FPTR:[0-9]+]]:gpr(p0) = COPY $r0 ; V4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0 ; NOV4T: %[[FPTR:[0-9]+]]:tgpr(p0) = COPY $r0 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp -; THUMB: tBLXr 14, $noreg, %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp +; THUMB: tBLXr 14 [always], $noreg, %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; V5T: BLX %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; V4T: BX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp ; NOV4T: BMOVPCRX_CALL %[[FPTR]](p0), csr_aapcs, implicit-def $lr, implicit $sp -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp entry: notail call arm_aapcscc void %fptr() ret void @@ -24,10 +24,10 @@ define arm_aapcscc void @test_direct_call() { ; CHECK-LABEL: name: test_direct_call -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp -; THUMB: tBL 14, $noreg, @call_target, csr_aapcs, implicit-def $lr, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp +; THUMB: tBL 14 [always], $noreg, @call_target, csr_aapcs, implicit-def $lr, implicit $sp ; ARM: BL @call_target, csr_aapcs, implicit-def $lr, implicit $sp -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp entry: notail call arm_aapcscc void @call_target() ret void Index: llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-cmp.mir @@ -69,12 +69,12 @@ ; CHECK-LABEL: name: test_icmp_eq_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 [equal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1 @@ -99,12 +99,12 @@ ; CHECK-LABEL: name: test_icmp_ne_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1 [notequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ne), %0(s32), %1 @@ -129,12 +129,12 @@ ; CHECK-LABEL: name: test_icmp_ugt_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8 [higher], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1 @@ -159,12 +159,12 @@ ; CHECK-LABEL: name: test_icmp_uge_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 2 [highersame], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(uge), %0(s32), %1 @@ -189,12 +189,12 @@ ; CHECK-LABEL: name: test_icmp_ult_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 3 [lower], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ult), %0(s32), %1 @@ -219,12 +219,12 @@ ; CHECK-LABEL: name: test_icmp_ule_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9 [lowersame], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ule), %0(s32), %1 @@ -249,12 +249,12 @@ ; CHECK-LABEL: name: test_icmp_sgt_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 [greater], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 @@ -279,12 +279,12 @@ ; CHECK-LABEL: name: test_icmp_sge_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10 [greaterequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(sge), %0(s32), %1 @@ -309,12 +309,12 @@ ; CHECK-LABEL: name: test_icmp_slt_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11 [less], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(slt), %0(s32), %1 @@ -339,12 +339,12 @@ ; CHECK-LABEL: name: test_icmp_sle_s32 ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13 [lessequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(sle), %0(s32), %1 @@ -367,10 +367,10 @@ liveins: $s0, $s1 ; CHECK-LABEL: name: test_fcmp_true_s32 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(true), %0(s32), %1 @@ -393,10 +393,10 @@ liveins: $s0, $s1 ; CHECK-LABEL: name: test_fcmp_false_s32 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(false), %0(s32), %1 @@ -421,13 +421,13 @@ ; CHECK-LABEL: name: test_fcmp_oeq_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 [equal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(oeq), %0(s32), %1 @@ -452,13 +452,13 @@ ; CHECK-LABEL: name: test_fcmp_ogt_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 [greater], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ogt), %0(s32), %1 @@ -483,13 +483,13 @@ ; CHECK-LABEL: name: test_fcmp_oge_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10 [greaterequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(oge), %0(s32), %1 @@ -514,13 +514,13 @@ ; CHECK-LABEL: name: test_fcmp_olt_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4 [minus], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(olt), %0(s32), %1 @@ -545,13 +545,13 @@ ; CHECK-LABEL: name: test_fcmp_ole_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9 [lowersame], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ole), %0(s32), %1 @@ -576,13 +576,13 @@ ; CHECK-LABEL: name: test_fcmp_ord_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7 [nooverflow], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ord), %0(s32), %1 @@ -607,13 +607,13 @@ ; CHECK-LABEL: name: test_fcmp_ugt_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8 [higher], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ugt), %0(s32), %1 @@ -638,13 +638,13 @@ ; CHECK-LABEL: name: test_fcmp_uge_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5 [plus], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(uge), %0(s32), %1 @@ -669,13 +669,13 @@ ; CHECK-LABEL: name: test_fcmp_ult_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11 [less], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ult), %0(s32), %1 @@ -700,13 +700,13 @@ ; CHECK-LABEL: name: test_fcmp_ule_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13 [lessequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ule), %0(s32), %1 @@ -731,13 +731,13 @@ ; CHECK-LABEL: name: test_fcmp_une_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1 [notequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(une), %0(s32), %1 @@ -762,13 +762,13 @@ ; CHECK-LABEL: name: test_fcmp_uno_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6 [overflow], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(uno), %0(s32), %1 @@ -793,16 +793,16 @@ ; CHECK-LABEL: name: test_fcmp_one_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 [greater], $cpsr + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4 [minus], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(one), %0(s32), %1 @@ -827,16 +827,16 @@ ; CHECK-LABEL: name: test_fcmp_ueq_s32 ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr - ; CHECK: VCMPS [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 [equal], $cpsr + ; CHECK: VCMPS [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6 [overflow], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s1) = G_FCMP floatpred(ueq), %0(s32), %1 @@ -859,10 +859,10 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: test_fcmp_true_s64 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14, $noreg, $noreg - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(true), %0(s64), %1 @@ -885,10 +885,10 @@ liveins: $d0, $d1 ; CHECK-LABEL: name: test_fcmp_false_s64 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(false), %0(s64), %1 @@ -913,13 +913,13 @@ ; CHECK-LABEL: name: test_fcmp_oeq_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 [equal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(oeq), %0(s64), %1 @@ -944,13 +944,13 @@ ; CHECK-LABEL: name: test_fcmp_ogt_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 [greater], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ogt), %0(s64), %1 @@ -975,13 +975,13 @@ ; CHECK-LABEL: name: test_fcmp_oge_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 10 [greaterequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(oge), %0(s64), %1 @@ -1006,13 +1006,13 @@ ; CHECK-LABEL: name: test_fcmp_olt_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 4 [minus], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(olt), %0(s64), %1 @@ -1037,13 +1037,13 @@ ; CHECK-LABEL: name: test_fcmp_ole_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 9 [lowersame], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ole), %0(s64), %1 @@ -1068,13 +1068,13 @@ ; CHECK-LABEL: name: test_fcmp_ord_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 7 [nooverflow], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ord), %0(s64), %1 @@ -1099,13 +1099,13 @@ ; CHECK-LABEL: name: test_fcmp_ugt_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 8 [higher], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1 @@ -1130,13 +1130,13 @@ ; CHECK-LABEL: name: test_fcmp_uge_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 5 [plus], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(uge), %0(s64), %1 @@ -1161,13 +1161,13 @@ ; CHECK-LABEL: name: test_fcmp_ult_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 11 [less], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ult), %0(s64), %1 @@ -1192,13 +1192,13 @@ ; CHECK-LABEL: name: test_fcmp_ule_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 13 [lessequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ule), %0(s64), %1 @@ -1223,13 +1223,13 @@ ; CHECK-LABEL: name: test_fcmp_une_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 1 [notequal], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(une), %0(s64), %1 @@ -1254,13 +1254,13 @@ ; CHECK-LABEL: name: test_fcmp_uno_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 6 [overflow], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(uno), %0(s64), %1 @@ -1285,16 +1285,16 @@ ; CHECK-LABEL: name: test_fcmp_one_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12, $cpsr - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 12 [greater], $cpsr + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 4 [minus], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(one), %0(s64), %1 @@ -1319,16 +1319,16 @@ ; CHECK-LABEL: name: test_fcmp_ueq_s64 ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 - ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0, $cpsr - ; CHECK: VCMPD [[COPY]], [[COPY1]], 14, $noreg, implicit-def $fpscr_nzcv - ; CHECK: FMSTAT 14, $noreg, implicit-def $cpsr, implicit $fpscr_nzcv - ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14, $noreg, $noreg + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi:%[0-9]+]]:gpr = MOVCCi [[MOVi]], 1, 0 [equal], $cpsr + ; CHECK: VCMPD [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $fpscr_nzcv + ; CHECK: FMSTAT 14 [always], $noreg, implicit-def $cpsr, implicit $fpscr_nzcv + ; CHECK: [[MOVCCi1:%[0-9]+]]:gpr = MOVCCi [[MOVCCi]], 1, 6 [overflow], $cpsr + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[MOVCCi1]], 1, 14 [always], $noreg, $noreg ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s1) = G_FCMP floatpred(ueq), %0(s64), %1 Index: llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_mla() #0 { ret void } @@ -40,11 +41,9 @@ ... --- name: test_mla -# CHECK-LABEL: name: test_mla legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -55,30 +54,29 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_mla + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2 + ; CHECK: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY]], [[COPY1]], [[COPY2]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MLA]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 - ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mla_commutative -# CHECK-LABEL: name: test_mla_commutative legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -89,30 +87,29 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_mla_commutative + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2 + ; CHECK: [[MLA:%[0-9]+]]:gprnopc = MLA [[COPY]], [[COPY1]], [[COPY2]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MLA]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 - ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %2, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mla_v5 -# CHECK-LABEL: name: test_mla_v5 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -123,30 +120,29 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_mla_v5 + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY $r2 + ; CHECK: early-clobber %4:gprnopc = MLAv5 [[COPY]], [[COPY1]], [[COPY2]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY %4 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 - ; CHECK: [[VREGZ:%[0-9]+]]:gprnopc = COPY $r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MLAv5 [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mls -# CHECK-LABEL: name: test_mls legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -157,30 +153,29 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_mls + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2 + ; CHECK: [[MLS:%[0-9]+]]:gpr = MLS [[COPY]], [[COPY1]], [[COPY2]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[MLS]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_SUB %2, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = MLS [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_no_mls -# CHECK-LABEL: name: test_no_mls legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -191,31 +186,30 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_no_mls + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2 + ; CHECK: early-clobber %3:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY2]], %3, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[SUBrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 - ; CHECK: [[VREGZ:%[0-9]+]]:gpr = COPY $r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_SUB %2, %3 - ; CHECK: [[VREGM:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg - ; CHECK: [[VREGR:%[0-9]+]]:gpr = SUBrr [[VREGZ]], [[VREGM]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bicrr -# CHECK-LABEL: name: test_bicrr legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -226,29 +220,28 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_bicrr + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[BICrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bicrr_commutative -# CHECK-LABEL: name: test_bicrr_commutative legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -259,29 +252,28 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_bicrr_commutative + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[BICrr:%[0-9]+]]:gpr = BICrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[BICrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %3, %0 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bicri -# CHECK-LABEL: name: test_bicri legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -292,8 +284,12 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_bicri + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[BICri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 ; This test and the following ones are a bit contrived, since they use a ; G_XOR that can be constant-folded. They exist mostly to validate the @@ -305,21 +301,16 @@ %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bicri_commutative_xor -# CHECK-LABEL: name: test_bicri_commutative_xor legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -330,29 +321,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_bicri_commutative_xor + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[BICri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %2, %1 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bicri_commutative_and -# CHECK-LABEL: name: test_bicri_commutative_and legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -363,29 +353,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_bicri_commutative_and + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[BICri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %3, %0 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bicri_commutative_both -# CHECK-LABEL: name: test_bicri_commutative_both legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -396,29 +385,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_bicri_commutative_both + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[BICri:%[0-9]+]]:gpr = BICri [[COPY]], 192, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[BICri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 192 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %2, %1 %4(s32) = G_AND %3, %0 - ; CHECK: [[VREGR:%[0-9]+]]:gpr = BICri [[VREGX]], 192, 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_movti16_0xffff -# CHECK-LABEL: name: test_movti16_0xffff legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -427,27 +415,26 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_movti16_0xffff + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[MOVTi16_:%[0-9]+]]:gprnopc = MOVTi16 [[COPY]], 65535, 14 [always], $noreg + ; CHECK: $r0 = COPY [[MOVTi16_]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 4294901760 ; 0xFFFF0000 %2(s32) = G_OR %0, %1 - ; CHECK: [[VREGR:%[0-9]+]]:gprnopc = MOVTi16 [[VREGX]], 65535, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_vnmuls -# CHECK-LABEL: name: test_vnmuls legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -457,28 +444,27 @@ bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_vnmuls + ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $s0 = COPY [[VNMULS]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FMUL %0, %1 %3(s32) = G_FNEG %2 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg $s0 = COPY %3(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 ... --- name: test_vnmuls_reassociate -# CHECK-LABEL: name: test_vnmuls_reassociate legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -488,28 +474,27 @@ bb.0: liveins: $s0, $s1 + ; CHECK-LABEL: name: test_vnmuls_reassociate + ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $s0 = COPY [[VNMULS]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FNEG %0 %3(s32) = G_FMUL %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VNMULS [[VREGX]], [[VREGY]], 14, $noreg $s0 = COPY %3(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 ... --- name: test_vnmuld -# CHECK-LABEL: name: test_vnmuld legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -519,28 +504,27 @@ bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_vnmuld + ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $d0 = COPY [[VNMULD]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FMUL %0, %1 %3(s64) = G_FNEG %2 - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VNMULD [[VREGX]], [[VREGY]], 14, $noreg $d0 = COPY %3(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 ... --- name: test_vfnmas -# CHECK-LABEL: name: test_vfnmas legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -551,30 +535,29 @@ bb.0: liveins: $s0, $s1, $s2 + ; CHECK-LABEL: name: test_vfnmas + ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 + ; CHECK: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $s0 = COPY [[VFNMAS]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = COPY $s2 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1 - ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2 %3(s32) = G_FMA %0, %1, %2 %4(s32) = G_FNEG %3 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg $s0 = COPY %4(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 ... --- name: test_vfnmad -# CHECK-LABEL: name: test_vfnmad legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -586,31 +569,30 @@ bb.0: liveins: $d0, $d1, $d2 + ; CHECK-LABEL: name: test_vfnmad + ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $d0 = COPY [[VFNMAD]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s64) = COPY $d2 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1 - ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 %3(s64) = G_FNEG %0 %4(s64) = G_FNEG %2 %5(s64) = G_FMA %3, %1, %4 - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFNMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg $d0 = COPY %5(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 ... --- name: test_vfmss -# CHECK-LABEL: name: test_vfmss legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -621,30 +603,29 @@ bb.0: liveins: $s0, $s1, $s2 + ; CHECK-LABEL: name: test_vfmss + ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 + ; CHECK: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $s0 = COPY [[VFMSS]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = COPY $s2 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1 - ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2 %3(s32) = G_FNEG %0 %4(s32) = G_FMA %3, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg $s0 = COPY %4(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 ... --- name: test_vfmsd -# CHECK-LABEL: name: test_vfmsd legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -655,30 +636,29 @@ bb.0: liveins: $d0, $d1, $d2 + ; CHECK-LABEL: name: test_vfmsd + ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $d0 = COPY [[VFMSD]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 %0(s64) = COPY $d0 %1(s64) = COPY $d1 %2(s64) = COPY $d2 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:dpr = COPY $d0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:dpr = COPY $d1 - ; CHECK-DAG: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 %3(s64) = G_FNEG %1 %4(s64) = G_FMA %0, %3, %2 - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMSD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg $d0 = COPY %4(s64) - ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 ... --- name: test_vfnmss -# CHECK-LABEL: name: test_vfnmss legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -689,30 +669,29 @@ bb.0: liveins: $s0, $s1, $s2 + ; CHECK-LABEL: name: test_vfnmss + ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 + ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1 + ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2 + ; CHECK: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $s0 = COPY [[VFNMSS]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 %0(s32) = COPY $s0 %1(s32) = COPY $s1 %2(s32) = COPY $s2 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:spr = COPY $s0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:spr = COPY $s1 - ; CHECK-DAG: [[VREGZ:%[0-9]+]]:spr = COPY $s2 %3(s32) = G_FNEG %2 %4(s32) = G_FMA %0, %1, %3 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VFNMSS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg $s0 = COPY %4(s32) - ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 ... --- name: test_bfc -# CHECK-LABEL: name: test_bfc legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -721,25 +700,24 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_bfc + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[BFC:%[0-9]+]]:gpr = BFC [[COPY]], -65529, 14 [always], $noreg + ; CHECK: $r0 = COPY [[BFC]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007 %2(s32) = G_AND %0, %1 - ; CHECK: [[RS:%[0-9]+]]:gpr = COPY $r0 - ; CHECK: [[RD:%[0-9]+]]:gpr = BFC [[RS]], -65529, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[RD]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_no_bfc_bad_mask -# CHECK-LABEL: name: test_no_bfc_bad_mask legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -748,15 +726,16 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_no_bfc_bad_mask + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 6, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = G_CONSTANT i32 6 ; 0x00000006 %2(s32) = G_AND %0, %1 - ; CHECK: [[RS:%[0-9]+]]:gpr = COPY $r0 - ; CHECK-NOT: BFC $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[RD]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple arm-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_trunc_and_zext_s1_to_s32() { ret void } @@ -67,11 +68,9 @@ ... --- name: test_trunc_and_zext_s1_to_s32 -# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -80,27 +79,26 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) %2(s32) = G_ZEXT %1(s1) - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_sext_s1_to_s32 -# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -109,28 +107,27 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 [always], $noreg, $noreg + ; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[RSBri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) %2(s32) = G_SEXT %1(s1) - ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_sext_s8_to_s32 -# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -139,28 +136,27 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY [[COPY]] + ; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY1]], 0, 14 [always], $noreg + ; CHECK: $r0 = COPY [[SXTB]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s8) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] %2(s32) = G_SEXT %1(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_zext_s16_to_s32 -# CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -169,28 +165,27 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY [[COPY]] + ; CHECK: [[UXTH:%[0-9]+]]:gprnopc = UXTH [[COPY1]], 0, 14 [always], $noreg + ; CHECK: $r0 = COPY [[UXTH]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s16) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] %2(s32) = G_ZEXT %1(s16) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTH [[VREGTRUNC]], 0, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_anyext_s8_to_s32 -# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -199,26 +194,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s8) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s8) $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREG]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_anyext_s16_to_s32 -# CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -227,26 +221,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s16) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s16) $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREG]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_zext_s1_to_s16 -# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -257,30 +250,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: STRH [[ANDri]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s16) = G_ZEXT %2(s1) - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_sext_s1_to_s16 -# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -291,31 +284,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[ANDri]], 0, 14 [always], $noreg, $noreg + ; CHECK: STRH [[RSBri]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s16) = G_SEXT %2(s1) - ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg - ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, $noreg, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_anyext_s1_to_s16 -# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -326,29 +319,29 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s16) = G_ANYEXT %2(s1) G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_zext_s8_to_s16 -# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -359,31 +352,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]] + ; CHECK: [[UXTB:%[0-9]+]]:gprnopc = UXTB [[COPY2]], 0, 14 [always], $noreg + ; CHECK: STRH [[UXTB]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s8) = G_TRUNC %1(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] %3(s16) = G_ZEXT %2(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = UXTB [[VREGTRUNC]], 0, 14, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_sext_s8_to_s16 -# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -394,31 +387,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]] + ; CHECK: [[SXTB:%[0-9]+]]:gprnopc = SXTB [[COPY2]], 0, 14 [always], $noreg + ; CHECK: STRH [[SXTB]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s8) = G_TRUNC %1(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]] %3(s16) = G_SEXT %2(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = SXTB [[VREGTRUNC]], 0, 14, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[VREGEXT]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_anyext_s8_to_s16 -# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -429,29 +422,29 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s8) = G_TRUNC %1(s32) %3(s16) = G_ANYEXT %2(s8) G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[VREG]], [[PTR]], $noreg, 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_zext_s1_to_s8 -# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -462,30 +455,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[ANDri:%[0-9]+]]:gprnopc = ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: STRBi12 [[ANDri]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s8) = G_ZEXT %2(s1) - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = ANDri [[VREG]], 1, 14, $noreg, $noreg G_STORE %3(s8), %0(p0) :: (store 1) - ; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_sext_s1_to_s8 -# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -496,31 +489,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: [[RSBri:%[0-9]+]]:gprnopc = RSBri [[ANDri]], 0, 14 [always], $noreg, $noreg + ; CHECK: STRBi12 [[RSBri]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s8) = G_SEXT %2(s1) - ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg - ; CHECK: [[VREGEXT:%[0-9]+]]:gprnopc = RSBri [[VREGAND]], 0, 14, $noreg, $noreg G_STORE %3(s8), %0(p0) :: (store 1) - ; CHECK: STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_anyext_s1_to_s8 -# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -531,30 +524,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]] + ; CHECK: STRBi12 [[COPY2]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s8) = G_ANYEXT %2(s1) G_STORE %3(s8), %0(p0) :: (store 1) - ; CHECK: [[RVREG:%[0-9]+]]:gprnopc = COPY [[VREG]] - ; CHECK: STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_add_s32 -# CHECK-LABEL: name: test_add_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -563,28 +556,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_add_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[ADDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_add_fold_imm_s32 -# CHECK-LABEL: name: test_add_fold_imm_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -593,26 +585,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_add_fold_imm_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri [[COPY]], 255, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[ADDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 255 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDri [[VREGX]], 255, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_add_no_fold_imm_s32 -# CHECK-LABEL: name: test_add_no_fold_imm_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -621,28 +612,27 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_add_no_fold_imm_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[MOVi16_:%[0-9]+]]:gpr = MOVi16 65535, 14 [always], $noreg + ; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[MOVi16_]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[ADDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 65535 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = MOVi16 65535, 14, $noreg %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:gpr = ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sub_s32 -# CHECK-LABEL: name: test_sub_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -651,28 +641,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_sub_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[SUBrr:%[0-9]+]]:gpr = SUBrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[SUBrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_SUB %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sub_imm_s32 -# CHECK-LABEL: name: test_sub_imm_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -681,26 +670,25 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_sub_imm_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[SUBri:%[0-9]+]]:gpr = SUBri [[COPY]], 17, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[SUBri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 17 %2(s32) = G_SUB %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SUBri [[VREGX]], 17, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sub_rev_imm_s32 -# CHECK-LABEL: name: test_sub_rev_imm_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -709,26 +697,25 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_sub_rev_imm_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[RSBri:%[0-9]+]]:gpr = RSBri [[COPY]], 17, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[RSBri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 17 %2(s32) = G_SUB %1, %0 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = RSBri [[VREGX]], 17, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mul_s32 -# CHECK-LABEL: name: test_mul_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -737,28 +724,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_mul_s32 + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 + ; CHECK: [[MUL:%[0-9]+]]:gprnopc = MUL [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MUL]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 %2(s32) = G_MUL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MUL [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mulv5_s32 -# CHECK-LABEL: name: test_mulv5_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -767,28 +753,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_mulv5_s32 + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r1 + ; CHECK: early-clobber %2:gprnopc = MULv5 [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gprnopc = COPY $r1 %2(s32) = G_MUL %0, %1 - ; CHECK: early-clobber [[VREGRES:%[0-9]+]]:gprnopc = MULv5 [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sdiv_s32 -# CHECK-LABEL: name: test_sdiv_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -797,28 +782,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_sdiv_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[SDIV:%[0-9]+]]:gpr = SDIV [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[SDIV]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_SDIV %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = SDIV [[VREGX]], [[VREGY]], 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_udiv_s32 -# CHECK-LABEL: name: test_udiv_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -827,28 +811,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_udiv_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[UDIV:%[0-9]+]]:gpr = UDIV [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[UDIV]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_UDIV %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gpr = UDIV [[VREGX]], [[VREGY]], 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_lshr_s32 -# CHECK-LABEL: name: test_lshr_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -857,28 +840,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_lshr_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 3, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MOVsr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_LSHR %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 3, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_ashr_s32 -# CHECK-LABEL: name: test_ashr_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -887,28 +869,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_ashr_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MOVsr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_ASHR %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 1, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_shl_s32 -# CHECK-LABEL: name: test_shl_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -917,28 +898,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_shl_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[MOVsr:%[0-9]+]]:gprnopc = MOVsr [[COPY]], [[COPY1]], 2, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MOVsr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = G_SHL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = MOVsr [[VREGX]], [[VREGY]], 2, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_load_from_stack -# CHECK-LABEL: name: test_load_from_stack legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -949,43 +929,40 @@ - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } -# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 -# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 body: | bb.0: liveins: $r0, $r1, $r2, $r3 + ; CHECK-LABEL: name: test_load_from_stack + ; CHECK: [[ADDri:%[0-9]+]]:gpr = ADDri %fixed-stack.0, 0, 14 [always], $noreg, $noreg + ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[ADDri]], 0, 14 [always], $noreg :: (load 4) + ; CHECK: $r0 = COPY [[LDRi12_]] + ; CHECK: [[ADDri1:%[0-9]+]]:gpr = ADDri %fixed-stack.2, 0, 14 [always], $noreg, $noreg + ; CHECK: [[LDRBi12_:%[0-9]+]]:gprnopc = LDRBi12 [[ADDri1]], 0, 14 [always], $noreg :: (load 1) + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[LDRBi12_]] + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = G_FRAME_INDEX %fixed-stack.2 - ; CHECK: [[FI32VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg %1(s32) = G_LOAD %0(p0) :: (load 4) - ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = LDRi12 [[FI32VREG]], 0, 14, $noreg $r0 = COPY %1 - ; CHECK: $r0 = COPY [[LD32VREG]] %2(p0) = G_FRAME_INDEX %fixed-stack.0 - ; CHECK: [[FI1VREG:%[0-9]+]]:gpr = ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg %3(s1) = G_LOAD %2(p0) :: (load 1) - ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = LDRBi12 [[FI1VREG]], 0, 14, $noreg %4(s32) = G_ANYEXT %3(s1) - ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] $r0 = COPY %4 - ; CHECK: $r0 = COPY [[RES]] BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_stores -# CHECK-LABEL: name: test_stores legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -996,41 +973,41 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_stores + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gprnopc = COPY [[COPY1]] + ; CHECK: [[ANDri:%[0-9]+]]:gprnopc = ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: STRBi12 [[ANDri]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: STRBi12 [[COPY2]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: STRH [[COPY1]], [[COPY]], $noreg, 0, 14 [always], $noreg :: (store 2) + ; CHECK: STRi12 [[COPY1]], [[COPY]], 0, 14 [always], $noreg :: (store 4) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[P:%[0-9]+]]:gpr = COPY $r0 %3(s32) = COPY $r1 - ; CHECK: [[V32:%[0-9]+]]:gpr = COPY $r1 %4(s1) = G_TRUNC %3(s32) %1(s8) = G_TRUNC %3(s32) - ; CHECK: [[V8:%[0-9]+]]:gprnopc = COPY [[V32]] %2(s16) = G_TRUNC %3(s32) G_STORE %4(s1), %0(p0) :: (store 1) - ; CHECK: [[V1:%[0-9]+]]:gprnopc = ANDri [[V32]], 1, 14, $noreg, $noreg - ; CHECK: STRBi12 [[V1]], [[P]], 0, 14, $noreg G_STORE %1(s8), %0(p0) :: (store 1) - ; CHECK: STRBi12 [[V8]], [[P]], 0, 14, $noreg G_STORE %2(s16), %0(p0) :: (store 2) - ; CHECK: STRH [[V32]], [[P]], $noreg, 0, 14, $noreg G_STORE %3(s32), %0(p0) :: (store 4) - ; CHECK: STRi12 [[V32]], [[P]], 0, 14, $noreg BX_RET 14, $noreg ... --- name: test_gep -# CHECK-LABEL: name: test_gep legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -1039,84 +1016,91 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_gep + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[ADDrr:%[0-9]+]]:gpr = ADDrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[ADDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(p0) = COPY $r0 - ; CHECK: %[[PTR:[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: %[[OFF:[0-9]+]]:gpr = COPY $r1 %2(p0) = G_PTR_ADD %0, %1(s32) - ; CHECK: %[[GEP:[0-9]+]]:gpr = ADDrr %[[PTR]], %[[OFF]], 14, $noreg, $noreg $r0 = COPY %2(p0) BX_RET 14, $noreg, implicit $r0 ... --- name: test_MOVi32imm -# CHECK-LABEL: name: test_MOVi32imm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_MOVi32imm + ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr = MOVi32imm 65537 + ; CHECK: $r0 = COPY [[MOVi32imm]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = G_CONSTANT i32 65537 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi32imm 65537 $r0 = COPY %0(s32) BX_RET 14, $noreg, implicit $r0 ... --- name: test_constant_imm -# CHECK-LABEL: name: test_constant_imm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_constant_imm + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MOVi]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = G_CONSTANT i32 42 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg $r0 = COPY %0(s32) BX_RET 14, $noreg, implicit $r0 ... --- name: test_constant_cimm -# CHECK-LABEL: name: test_constant_cimm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: ; Adding a type on G_CONSTANT changes its operand from an Imm into a CImm. ; We still want to see the same thing in the output though. + ; CHECK-LABEL: name: test_constant_cimm + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 42, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MOVi]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = G_CONSTANT i32 42 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 42, 14, $noreg, $noreg $r0 = COPY %0(s32) BX_RET 14, $noreg, implicit $r0 ... --- name: test_pointer_constant_unconstrained -# CHECK-LABEL: name: test_pointer_constant_unconstrained legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_pointer_constant_unconstrained + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[MOVi]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(p0) = G_CONSTANT i32 0 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; This leaves %0 unconstrained before the G_CONSTANT is selected. $r0 = COPY %0(p0) @@ -1124,28 +1108,26 @@ ... --- name: test_pointer_constant_constrained -# CHECK-LABEL: name: test_pointer_constant_constrained legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_pointer_constant_constrained + ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: STRi12 [[MOVi]], [[MOVi]], 0, 14 [always], $noreg :: (store 4) %0(p0) = G_CONSTANT i32 0 - ; CHECK: %[[C:[0-9]+]]:gpr = MOVi 0, 14, $noreg, $noreg ; This constrains %0 before the G_CONSTANT is selected. G_STORE %0(p0), %0(p0) :: (store 4) ... --- name: test_inttoptr_s32 -# CHECK-LABEL: name: test_inttoptr_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -1153,22 +1135,22 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_inttoptr_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(p0) = G_INTTOPTR %0(s32) - ; CHECK: [[INT:%[0-9]+]]:gpr = COPY $r0 $r0 = COPY %1(p0) - ; CHECK: $r0 = COPY [[INT]] BX_RET 14, $noreg, implicit $r0 ... --- name: test_ptrtoint_s32 -# CHECK-LABEL: name: test_ptrtoint_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -1176,22 +1158,22 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_ptrtoint_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(p0) = COPY $r0 %1(s32) = G_PTRTOINT %0(p0) - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 $r0 = COPY %1(s32) - ; CHECK: $r0 = COPY [[PTR]] BX_RET 14, $noreg, implicit $r0 ... --- name: test_select_s32 -# CHECK-LABEL: name: test_select_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -1201,31 +1183,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_select_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: TSTri [[COPY1]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 [equal], $cpsr + ; CHECK: $r0 = COPY [[MOVCCr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s32) = G_SELECT %2(s1), %0, %1 - ; CHECK: TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr - ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr $r0 = COPY %3(s32) - ; CHECK: $r0 = COPY [[RES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_select_ptr -# CHECK-LABEL: name: test_select_ptr legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -1236,73 +1217,73 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_select_ptr + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2 + ; CHECK: TSTri [[COPY2]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[MOVCCr:%[0-9]+]]:gpr = MOVCCr [[COPY]], [[COPY1]], 0 [equal], $cpsr + ; CHECK: $r0 = COPY [[MOVCCr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(p0) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(p0) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY $r2 %3(s1) = G_TRUNC %2(s32) %4(p0) = G_SELECT %3(s1), %0, %1 - ; CHECK: TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr - ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr $r0 = COPY %4(p0) - ; CHECK: $r0 = COPY [[RES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_br -# CHECK-LABEL: name: test_br legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } body: | + ; CHECK-LABEL: name: test_br + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: TSTri [[COPY]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: Bcc %bb.1, 1 [notequal], $cpsr + ; CHECK: B %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: B %bb.2 + ; CHECK: bb.2: + ; CHECK: BX_RET 14 [always], $noreg bb.0: - ; CHECK: bb.0 successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0 %0(s32) = COPY $r0 - ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) G_BRCOND %1(s1), %bb.1 - ; CHECK: TSTri [[COND32]], 1, 14, $noreg, implicit-def $cpsr - ; CHECK: Bcc %bb.1, 1, $cpsr G_BR %bb.2 - ; CHECK: B %bb.2 bb.1: - ; CHECK: bb.1 successors: %bb.2(0x80000000) G_BR %bb.2 - ; CHECK: B %bb.2 bb.2: - ; CHECK: bb.2 BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_phi_s32 -# CHECK-LABEL: name: test_phi_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -1311,8 +1292,24 @@ - { id: 3, class: gprb } - { id: 4, class: gprb } body: | + ; CHECK-LABEL: name: test_phi_s32 + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: $r0, $r1, $r2 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2 + ; CHECK: TSTri [[COPY]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: Bcc %bb.1, 1 [notequal], $cpsr + ; CHECK: B %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: B %bb.2 + ; CHECK: bb.2: + ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, [[COPY2]], %bb.1 + ; CHECK: $r0 = COPY [[PHI]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 bb.0: - ; CHECK: [[BB1:bb.0]]: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0, $r1, $r2 @@ -1321,23 +1318,17 @@ %2(s32) = COPY $r1 %3(s32) = COPY $r2 - ; CHECK: [[V1:%[0-9]+]]:gpr = COPY $r1 - ; CHECK: [[V2:%[0-9]+]]:gpr = COPY $r2 G_BRCOND %1(s1), %bb.1 G_BR %bb.2 bb.1: - ; CHECK: [[BB2:bb.1]]: successors: %bb.2(0x80000000) G_BR %bb.2 - ; CHECK: B %bb.2 bb.2: - ; CHECK: bb.2 %4(s32) = G_PHI %2(s32), %bb.0, %3(s32), %bb.1 - ; CHECK: {{%[0-9]+}}:gpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]] $r0 = COPY %4(s32) BX_RET 14, $noreg, implicit $r0 Index: llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -3,7 +3,7 @@ define void @test_void_return() { ; CHECK-LABEL: name: test_void_return -; CHECK: BX_RET 14, $noreg +; CHECK: BX_RET 14 [always], $noreg entry: ret void } @@ -18,7 +18,7 @@ ; CHECK: [[SUM:%[0-9]+]]:_(s1) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[EXT:%[0-9]+]]:_(s32) = G_SEXT [[SUM]] ; CHECK: $r0 = COPY [[EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i1 %x, %y ret i1 %sum @@ -34,7 +34,7 @@ ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: $r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i8 %x, %y ret i8 %sum @@ -50,7 +50,7 @@ ; CHECK: [[RES:%[0-9]+]]:_(s8) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: $r0 = COPY [[RES_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %res = sub i8 %x, %y ret i8 %res @@ -63,7 +63,7 @@ ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]] ; CHECK: $r0 = COPY [[VREGEXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: ret i8 %x } @@ -78,7 +78,7 @@ ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: $r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i16 %x, %y ret i16 %sum @@ -94,7 +94,7 @@ ; CHECK: [[RES:%[0-9]+]]:_(s16) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: [[RES_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[RES]] ; CHECK: $r0 = COPY [[RES_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %res = sub i16 %x, %y ret i16 %res @@ -107,7 +107,7 @@ ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]] ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]] ; CHECK: $r0 = COPY [[VREGEXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: ret i16 %x } @@ -119,7 +119,7 @@ ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGX]], [[VREGY]] ; CHECK: $r0 = COPY [[SUM]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i32 %x, %y ret i32 %sum @@ -132,7 +132,7 @@ ; CHECK-DAG: [[VREGY:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SUB [[VREGX]], [[VREGY]] ; CHECK: $r0 = COPY [[RES]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %res = sub i32 %x, %y ret i32 %res @@ -149,7 +149,7 @@ ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]]{{.*}}load 4 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[VREGP2]], [[VREGP5]] ; CHECK: $r0 = COPY [[SUM]] -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i32 %p2, %p5 ret i32 %sum @@ -170,7 +170,7 @@ ; CHECK: [[SUM:%[0-9]+]]:_(s16) = G_ADD [[VREGP1]], [[VREGP5]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: $r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i16 %p1, %p5 ret i16 %sum @@ -191,7 +191,7 @@ ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: $r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i8 %p2, %p4 ret i8 %sum @@ -211,7 +211,7 @@ ; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[VREGP2]], [[VREGP4]] ; CHECK: [[SUM_EXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SUM]] ; CHECK: $r0 = COPY [[SUM_EXT]](s32) -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %sum = add i8 %p2, %p4 ret i8 %sum @@ -229,7 +229,7 @@ ; CHECK: [[VREGP5:%[0-9]+]]:_(s16) = G_TRUNC [[VREGP5SEXT]] ; CHECK: [[VREGP5ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREGP5]] ; CHECK: $r0 = COPY [[VREGP5ZEXT]] -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: ret i16 %p5 } @@ -251,7 +251,7 @@ ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[VREGV:%[0-9]+]]:_(p0) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: $r0 = COPY [[VREGV]] -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %v = load i32*, i32** %p ret i32* %v @@ -266,7 +266,7 @@ ; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load 4 ; CHECK: $r0 = COPY [[VREGV]] -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %v = load i32, i32* %p ret i32 %v @@ -284,7 +284,7 @@ ; CHECK: [[VREGP5:%[0-9]+]]:_(s32) = G_LOAD [[FIP5]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGP5]] ; CHECK: $r0 = COPY [[VREGV]] -; CHECK: BX_RET 14, $noreg, implicit $r0 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0 entry: %v = fadd float %p1, %p5 ret float %v @@ -313,7 +313,7 @@ ; CHECK: [[VREGQ1:%[0-9]+]]:_(s32) = G_LOAD [[FIQ1]](p0){{.*}}load 4 ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: $s0 = COPY [[VREGV]] -; CHECK: BX_RET 14, $noreg, implicit $s0 +; CHECK: BX_RET 14 [always], $noreg, implicit $s0 entry: %v = fadd float %p1, %q1 ret float %v @@ -334,7 +334,7 @@ ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: $d0 = COPY [[VREGV]] -; CHECK: BX_RET 14, $noreg, implicit $d0 +; CHECK: BX_RET 14 [always], $noreg, implicit $d0 entry: %v = fadd double %p1, %q1 ret double %v @@ -360,7 +360,7 @@ ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; CHECK-DAG: $r0 = COPY [[VREGVLO]] ; CHECK-DAG: $r1 = COPY [[VREGVHI]] -; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 entry: %v = fadd double %p1, %p5 ret double %v @@ -382,7 +382,7 @@ ; CHECK: [[VREGQ1:%[0-9]+]]:_(s64) = G_LOAD [[FIQ1]](p0){{.*}}load 8 ; CHECK: [[VREGV:%[0-9]+]]:_(s64) = G_FADD [[VREGP1]], [[VREGQ1]] ; CHECK: $d0 = COPY [[VREGV]] -; CHECK: BX_RET 14, $noreg, implicit $d0 +; CHECK: BX_RET 14 [always], $noreg, implicit $d0 entry: %v = fadd double %p1, %q1 ret double %v @@ -405,7 +405,7 @@ ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; CHECK-DAG: $r0 = COPY [[VREGVLO]] ; CHECK-DAG: $r1 = COPY [[VREGVHI]] -; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 entry: %v = fadd double %p0, %p1 ret double %v @@ -428,7 +428,7 @@ ; BIG: [[VREGVHI:%[0-9]+]]:_(s32), [[VREGVLO:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VREGV]](s64) ; CHECK-DAG: $r0 = COPY [[VREGVLO]] ; CHECK-DAG: $r1 = COPY [[VREGVHI]] -; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 +; CHECK: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 entry: %v = fadd double %p0, %p1 ret double %v Index: llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir @@ -51,9 +51,9 @@ ; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r1 = COPY [[Y]] ; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SDIV @@ -88,9 +88,9 @@ ; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r1 = COPY [[Y]] ; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UDIV @@ -139,9 +139,9 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SDIV @@ -191,9 +191,9 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UDIV @@ -245,9 +245,9 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_idiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__divsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SDIV @@ -297,9 +297,9 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_uidiv, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; ARM-DEFAULT: BL &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__udivsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UDIV @@ -339,10 +339,10 @@ ; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r1 = COPY [[Y]] ; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1 ; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SREM @@ -379,10 +379,10 @@ ; SOFT-DAG: $r0 = COPY [[X]] ; SOFT-DAG: $r1 = COPY [[Y]] ; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; SOFT-AEABI: [[R:%[0-9]+]]:_(s32) = COPY $r1 ; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: [[R:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UREM @@ -433,10 +433,10 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SREM @@ -488,10 +488,10 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UREM @@ -545,10 +545,10 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_idivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; ARM-DEFAULT: BL &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__modsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_SREM @@ -600,10 +600,10 @@ ; SOFT-DAG: $r0 = COPY [[X32]] ; SOFT-DAG: $r1 = COPY [[Y32]] ; ARM-AEABI: BL &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-AEABI: tBL 14, $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-AEABI: tBL 14 [always], $noreg, &__aeabi_uidivmod, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-AEABI: [[R32:%[0-9]+]]:_(s32) = COPY $r1 ; ARM-DEFAULT: BL &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 - ; THUMB-DEFAULT: tBL 14, $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 + ; THUMB-DEFAULT: tBL 14 [always], $noreg, &__umodsi3, {{.*}}, implicit $r0, implicit $r1, implicit-def $r0 ; SOFT-DEFAULT: [[R32:%[0-9]+]]:_(s32) = COPY $r0 ; SOFT: ADJCALLSTACKUP ; SOFT-NOT: G_UREM Index: llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll +++ llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll @@ -8,16 +8,16 @@ ; CHECK-LABEL: name: test_call_simple_reg_params ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]] ; ARM: BL @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0 -; THUMB: tBL 14, $noreg, @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0 +; THUMB: tBL 14 [always], $noreg, @simple_reg_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0 -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[RVREG]] -; ARM: BX_RET 14, $noreg, implicit $r0 -; THUMB: tBX_RET 14, $noreg, implicit $r0 +; ARM: BX_RET 14 [always], $noreg, implicit $r0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0 entry: %r = notail call arm_aapcscc i32 *@simple_reg_params_target(i32 %b, i32 *%a) ret i32 *%r @@ -29,7 +29,7 @@ ; CHECK-LABEL: name: test_call_simple_stack_params ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]] ; CHECK-DAG: $r2 = COPY [[BVREG]] @@ -43,12 +43,12 @@ ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 ; ARM: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 -; THUMB: tBL 14, $noreg, @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 +; THUMB: tBL 14 [always], $noreg, @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0 -; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[RVREG]] -; ARM: BX_RET 14, $noreg, implicit $r0 -; THUMB: tBX_RET 14, $noreg, implicit $r0 +; ARM: BX_RET 14 [always], $noreg, implicit $r0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0 entry: %r = notail call arm_aapcscc i32 *@simple_stack_params_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a) ret i32 *%r @@ -64,7 +64,7 @@ ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R1VREG]] ; CHECK-DAG: [[R2VREG:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK-DAG: [[CVREG:%[0-9]+]]:_(s1) = G_TRUNC [[R2VREG]] -; CHECK: ADJCALLSTACKDOWN 20, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 20, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: [[SEXTA:%[0-9]+]]:_(s32) = G_SEXT [[AVREG]](s8) ; CHECK: $r0 = COPY [[SEXTA]] ; CHECK: [[ZEXTA:%[0-9]+]]:_(s32) = G_ZEXT [[AVREG]](s8) @@ -99,14 +99,14 @@ ; CHECK: [[ZEXTC:%[0-9]+]]:_(s32) = G_ZEXT [[CVREG]] ; CHECK: G_STORE [[ZEXTC]](s32), [[FI5]](p0){{.*}}store 4 ; ARM: BL @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 -; THUMB: tBL 14, $noreg, @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 +; THUMB: tBL 14 [always], $noreg, @ext_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[R0VREG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s16) = G_TRUNC [[R0VREG]] -; CHECK: ADJCALLSTACKUP 20, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 20, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: [[RExtVREG:%[0-9]+]]:_(s32) = G_SEXT [[RVREG]] ; CHECK: $r0 = COPY [[RExtVREG]] -; ARM: BX_RET 14, $noreg, implicit $r0 -; THUMB: tBX_RET 14, $noreg, implicit $r0 +; ARM: BX_RET 14 [always], $noreg, implicit $r0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0 entry: %r = notail call arm_aapcscc signext i16 @ext_target(i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i8 signext %a, i8 zeroext %a, i16 signext %b, i16 zeroext %b, i1 zeroext %c) ret i16 %r @@ -118,16 +118,16 @@ ; CHECK-LABEL: name: test_call_vfpcc_fp_params ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s64) = COPY $d0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $s2 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $s0 = COPY [[BVREG]] ; CHECK-DAG: $d1 = COPY [[AVREG]] ; ARM: BL @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0 -; THUMB: tBL 14, $noreg, @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0 +; THUMB: tBL 14 [always], $noreg, @vfpcc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $d1, implicit-def $d0 ; CHECK: [[RVREG:%[0-9]+]]:_(s64) = COPY $d0 -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $d0 = COPY [[RVREG]] -; ARM: BX_RET 14, $noreg, implicit $d0 -; THUMB: tBX_RET 14, $noreg, implicit $d0 +; ARM: BX_RET 14 [always], $noreg, implicit $d0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $d0 entry: %r = notail call arm_aapcs_vfpcc double @vfpcc_fp_target(float %b, double %a) ret double %r @@ -142,7 +142,7 @@ ; LITTLE-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A1]](s32), [[A2]](s32) ; BIG-DAG: [[AVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[A2]](s32), [[A1]](s32) ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r2 -; CHECK: ADJCALLSTACKDOWN 16, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 16, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: [[A1:%[0-9]+]]:_(s32), [[A2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AVREG]](s64) ; LITTLE-DAG: $r2 = COPY [[A1]] @@ -158,19 +158,19 @@ ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) ; CHECK: G_STORE [[AVREG]](s64), [[FI2]](p0){{.*}}store 8 ; ARM: BL @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 -; THUMB: tBL 14, $noreg, @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 +; THUMB: tBL 14 [always], $noreg, @aapcscc_fp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; CHECK-DAG: [[R1:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[R2:%[0-9]+]]:_(s32) = COPY $r1 ; LITTLE: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R1]](s32), [[R2]](s32) ; BIG: [[RVREG:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[R2]](s32), [[R1]](s32) -; CHECK: ADJCALLSTACKUP 16, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 16, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: [[R1:%[0-9]+]]:_(s32), [[R2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[RVREG]](s64) ; LITTLE-DAG: $r0 = COPY [[R1]] ; LITTLE-DAG: $r1 = COPY [[R2]] ; BIG-DAG: $r0 = COPY [[R2]] ; BIG-DAG: $r1 = COPY [[R1]] -; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 -; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 +; ARM: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0, implicit $r1 entry: %r = notail call arm_aapcscc double @aapcscc_fp_target(float %b, double %a, float %b, double %a) ret double %r @@ -181,15 +181,15 @@ define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) { ; CHECK-LABEL: name: test_call_different_call_conv ; CHECK: [[X:%[0-9]+]]:_(s32) = COPY $s0 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[X]] ; ARM: BL @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0 -; THUMB: tBL 14, $noreg, @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0 +; THUMB: tBL 14 [always], $noreg, @different_call_conv_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit-def $r0 ; CHECK: [[R:%[0-9]+]]:_(s32) = COPY $r0 -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $s0 = COPY [[R]] -; ARM: BX_RET 14, $noreg, implicit $s0 -; THUMB: tBX_RET 14, $noreg, implicit $s0 +; ARM: BX_RET 14 [always], $noreg, implicit $s0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $s0 entry: %r = notail call arm_aapcscc float @different_call_conv_target(float %x) ret float %r @@ -202,23 +202,23 @@ ; CHECK: liveins: $r0, $r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] ; ARM: BL @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 -; THUMB: tBL 14, $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 +; THUMB: tBL 14 [always], $noreg, @tiny_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2 -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say ; that composite types larger than 4 bytes should be passed through memory), ; but it's what DAGISel does. We should fix it in the common code for both. ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] ; CHECK: $r2 = COPY [[R2]] -; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1, implicit $r2 -; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1, implicit $r2 +; ARM: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1, implicit $r2 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0, implicit $r1, implicit $r2 entry: %r = notail call arm_aapcscc [3 x i32] @tiny_int_arrays_target([2 x i32] %arr) ret [3 x i32] %r @@ -233,16 +233,16 @@ ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $r2 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $r3 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] ; CHECK: $r2 = COPY [[R2]] ; CHECK: $r3 = COPY [[R3]] ; ARM: BL @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 -; THUMB: tBL 14, $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp -; ARM: BX_RET 14, $noreg -; THUMB: tBX_RET 14, $noreg +; THUMB: tBL 14 [always], $noreg, @multiple_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp +; ARM: BX_RET 14 [always], $noreg +; THUMB: tBX_RET 14 [always], $noreg entry: notail call arm_aapcscc void @multiple_int_arrays_target([2 x i32] %arr0, [2 x i32] %arr1) ret void @@ -266,7 +266,7 @@ ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] -; CHECK: ADJCALLSTACKDOWN 64, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 64, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] ; CHECK: $r2 = COPY [[R2]] @@ -282,10 +282,10 @@ ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; ARM: BL @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 -; THUMB: tBL 14, $noreg, @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 -; CHECK: ADJCALLSTACKUP 64, 0, 14, $noreg, implicit-def $sp, implicit $sp -; ARM: BX_RET 14, $noreg -; THUMB: tBX_RET 14, $noreg +; THUMB: tBL 14 [always], $noreg, @large_int_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3 +; CHECK: ADJCALLSTACKUP 64, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp +; ARM: BX_RET 14 [always], $noreg +; THUMB: tBX_RET 14 [always], $noreg entry: notail call arm_aapcscc void @large_int_arrays_target([20 x i32] %arr) ret void @@ -308,7 +308,7 @@ ; BIG: [[ARR1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32) ; CHECK: [[ARR2_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2:%[0-9]+]]:_(s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]] -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: [[ARR0_0:%[0-9]+]]:_(s32), [[ARR0_1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ARR0]](s64) ; LITTLE: $r0 = COPY [[ARR0_0]](s32) ; LITTLE: $r1 = COPY [[ARR0_1]](s32) @@ -324,14 +324,14 @@ ; CHECK: [[ARR2_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[ARR2_OFFSET]](s32) ; CHECK: G_STORE [[ARR2]](s64), [[ARR2_ADDR]](p0){{.*}}store 8 ; ARM: BL @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 -; THUMB: tBL 14, $noreg, @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 +; THUMB: tBL 14 [always], $noreg, @fp_arrays_aapcs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] -; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 -; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 +; ARM: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0, implicit $r1 entry: %r = notail call arm_aapcscc [2 x float] @fp_arrays_aapcs_target([3 x double] %arr) ret [2 x float] %r @@ -361,7 +361,7 @@ ; CHECK: [[Z2:%[0-9]+]]:_(s64) = G_LOAD [[Z2_FI]]{{.*}}load 8 ; CHECK: [[Z3_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]] ; CHECK: [[Z3:%[0-9]+]]:_(s64) = G_LOAD [[Z3_FI]]{{.*}}load 8 -; CHECK: ADJCALLSTACKDOWN 32, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 32, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $d0 = COPY [[X0]](s64) ; CHECK: $d1 = COPY [[X1]](s64) ; CHECK: $d2 = COPY [[X2]](s64) @@ -385,18 +385,18 @@ ; CHECK: [[Z3_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[Z3_OFFSET]](s32) ; CHECK: G_STORE [[Z3]](s64), [[Z3_ADDR]](p0){{.*}}store 8 ; ARM: BL @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3 -; THUMB: tBL 14, $noreg, @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3 +; THUMB: tBL 14 [always], $noreg, @fp_arrays_aapcs_vfp_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit $d2, implicit $s6, implicit $s7, implicit $s8, implicit-def $s0, implicit-def $s1, implicit-def $s2, implicit-def $s3 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $s1 ; CHECK: [[R2:%[0-9]+]]:_(s32) = COPY $s2 ; CHECK: [[R3:%[0-9]+]]:_(s32) = COPY $s3 -; CHECK: ADJCALLSTACKUP 32, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 32, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $s0 = COPY [[R0]] ; CHECK: $s1 = COPY [[R1]] ; CHECK: $s2 = COPY [[R2]] ; CHECK: $s3 = COPY [[R3]] -; ARM: BX_RET 14, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3 -; THUMB: tBX_RET 14, $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3 +; ARM: BX_RET 14 [always], $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3 +; THUMB: tBX_RET 14 [always], $noreg, implicit $s0, implicit $s1, implicit $s2, implicit $s3 entry: %r = notail call arm_aapcs_vfpcc [4 x float] @fp_arrays_aapcs_vfp_target([3 x double] %x, [3 x float] %y, [4 x double] %z) ret [4 x float] %r @@ -420,7 +420,7 @@ ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]]:_(s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] -; CHECK: ADJCALLSTACKDOWN 80, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 80, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] ; CHECK: $r2 = COPY [[R2]] @@ -436,14 +436,14 @@ ; CHECK: [[LAST_STACK_ARG_ADDR:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[OFF_LAST_ELEMENT]](s32) ; CHECK: G_STORE [[LAST_STACK_ELEMENT]](s32), [[LAST_STACK_ARG_ADDR]]{{.*}}store 4 ; ARM: BL @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 -; THUMB: tBL 14, $noreg, @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 +; THUMB: tBL 14 [always], $noreg, @tough_arrays_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0, implicit-def $r1 ; CHECK: [[R0:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK: [[R1:%[0-9]+]]:_(p0) = COPY $r1 -; CHECK: ADJCALLSTACKUP 80, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 80, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]] ; CHECK: $r1 = COPY [[R1]] -; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 -; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 +; ARM: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0, implicit $r1 entry: %r = notail call arm_aapcscc [2 x i32*] @tough_arrays_target([6 x [4 x i32]] %arr) ret [2 x i32*] %r @@ -456,18 +456,18 @@ ; CHECK: liveins: $r0, $r1 ; CHECK-DAG: [[X0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[X1:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[X0]](s32) ; CHECK-DAG: $r1 = COPY [[X1]](s32) ; ARM: BL @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 -; THUMB: tBL 14, $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 +; THUMB: tBL 14 [always], $noreg, @structs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $r0, implicit-def $r1 ; CHECK: [[R0:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK: [[R1:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 0, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[R0]](s32) ; CHECK: $r1 = COPY [[R1]](s32) -; ARM: BX_RET 14, $noreg, implicit $r0, implicit $r1 -; THUMB: tBX_RET 14, $noreg, implicit $r0, implicit $r1 +; ARM: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0, implicit $r1 %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x) ret {i32, i32} %r } Index: llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-select-copy_to_regclass-of-fptosi.mir @@ -19,10 +19,10 @@ bb.1: ; CHECK-LABEL: name: test_fptosi ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0 - ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14, $noreg + ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14 [always], $noreg ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]] ; CHECK: $r0 = COPY [[COPY1]] - ; CHECK: MOVPCLR 14, $noreg, implicit $r0 + ; CHECK: MOVPCLR 14 [always], $noreg, implicit $r0 %0:fprb(s32) = COPY $s0 %1:gprb(s32) = G_FPTOSI %0(s32) $r0 = COPY %1(s32) Index: llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-pic.mir @@ -33,13 +33,13 @@ ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_global @@ -59,13 +59,13 @@ ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_global :: (load 4 from got) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_internal_constant @@ -85,13 +85,13 @@ ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_constant @@ -111,11 +111,11 @@ ; ELF: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel_ldr target-flags(arm-got) @external_constant :: (load 4 from got) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-ropi-rwpi.mir @@ -37,19 +37,19 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global - ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm target-flags(arm-sbrel) @internal_global - ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) - ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg + ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) + ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14 [always], $noreg, $noreg %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_global @@ -71,19 +71,19 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global - ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) ; RWPI-MOVT: [[OFF:%[0-9]+]]:gpr = MOVi32imm target-flags(arm-sbrel) @external_global - ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) - ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14, $noreg, $noreg + ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) + ; RWPI: [[G:%[0-9]+]]:gpr = ADDrr $r9, [[OFF]], 14 [always], $noreg, $noreg %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_internal_constant @@ -104,16 +104,16 @@ ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_constant - ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_constant @@ -134,14 +134,14 @@ ; ROPI-MOVT: [[G:%[0-9]+]]:gpr = MOV_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_pcrel @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_constant - ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir +++ llvm/test/CodeGen/ARM/GlobalISel/arm-select-globals-static.mir @@ -26,18 +26,18 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global - ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @internal_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_global @@ -56,16 +56,16 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; ELF-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global - ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = LDRi12 %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = MOVi32imm @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = LDRLIT_ga_abs @external_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14, $noreg + ; CHECK: [[V:%[0-9]+]]:gpr = LDRi12 [[G]], 0, 14 [always], $noreg $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll +++ llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll @@ -7,7 +7,7 @@ ; CHECK-LABEL: name: test_call_to_varargs_with_ints ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(p0) = COPY $r0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s32) = COPY $r1 -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[BVREG]] ; CHECK-DAG: $r1 = COPY [[AVREG]] ; CHECK-DAG: $r2 = COPY [[BVREG]] @@ -21,12 +21,12 @@ ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) ; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store 4 ; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 -; THUMB: tBL 14, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 +; THUMB: tBL 14 [always], $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 -; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $r0 = COPY [[RVREG]] -; ARM: BX_RET 14, $noreg, implicit $r0 -; THUMB: tBX_RET 14, $noreg, implicit $r0 +; ARM: BX_RET 14 [always], $noreg, implicit $r0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $r0 entry: %r = notail call arm_aapcscc i32(i32, ...) @int_varargs_target(i32 %b, i32 *%a, i32 %b, i32 *%a, i32 %b, i32 *%a) ret i32 %r @@ -38,7 +38,7 @@ ; CHECK-LABEL: name: test_call_to_varargs_with_floats ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1 -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[AVREG]] ; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64) ; CHECK-DAG: $r2 = COPY [[B1]] @@ -48,12 +48,12 @@ ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8 ; ARM: BL @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 -; THUMB: tBL 14, $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 +; THUMB: tBL 14 [always], $noreg, @float_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 -; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $s0 = COPY [[RVREG]] -; ARM: BX_RET 14, $noreg, implicit $s0 -; THUMB: tBX_RET 14, $noreg, implicit $s0 +; ARM: BX_RET 14 [always], $noreg, implicit $s0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $s0 entry: %r = notail call arm_aapcs_vfpcc float(float, double, ...) @float_varargs_target(float %a, double %b, double %b) ret float %r @@ -64,7 +64,7 @@ ; CHECK-DAG: [[FPTRVREG:%[0-9]+]]:gpr(p0) = COPY $r0 ; CHECK-DAG: [[AVREG:%[0-9]+]]:_(s32) = COPY $s0 ; CHECK-DAG: [[BVREG:%[0-9]+]]:_(s64) = COPY $d1 -; CHECK: ADJCALLSTACKDOWN 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKDOWN 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK-DAG: $r0 = COPY [[AVREG]] ; CHECK-DAG: [[B1:%[0-9]+]]:_(s32), [[B2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[BVREG]](s64) ; CHECK-DAG: $r2 = COPY [[B1]] @@ -74,12 +74,12 @@ ; CHECK: [[FI1:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP1]], [[OFF1]](s32) ; CHECK: G_STORE [[BVREG]](s64), [[FI1]](p0){{.*}}store 8 ; ARM: BLX [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 -; THUMB: tBLXr 14, $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 +; THUMB: tBLXr 14 [always], $noreg, [[FPTRVREG]](p0), csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 -; CHECK: ADJCALLSTACKUP 8, 0, 14, $noreg, implicit-def $sp, implicit $sp +; CHECK: ADJCALLSTACKUP 8, 0, 14 [always], $noreg, implicit-def $sp, implicit $sp ; CHECK: $s0 = COPY [[RVREG]] -; ARM: BX_RET 14, $noreg, implicit $s0 -; THUMB: tBX_RET 14, $noreg, implicit $s0 +; ARM: BX_RET 14 [always], $noreg, implicit $s0 +; THUMB: tBX_RET 14 [always], $noreg, implicit $s0 entry: %r = notail call arm_aapcs_vfpcc float(float, double, ...) %fptr(float %a, double %b, double %b) ret float %r Index: llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-clz.mir @@ -22,12 +22,12 @@ ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CTLZ %0(s32) - ; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14 [always], $noreg $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-fp-const.mir @@ -32,13 +32,13 @@ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_FCONSTANT float 0.0 - ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; CHECK: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) G_STORE %1(s32), %0 :: (store 4) - ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg + ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 [always], $noreg BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg + ; CHECK: BX_RET 14 [always], $noreg ... --- name: test_fpconst_zero_s64 @@ -63,13 +63,13 @@ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s64) = G_FCONSTANT double 0.0 - ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool) + ; CHECK: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 [always], $noreg :: (load 8 from constant-pool) G_STORE %1(s64), %0 :: (store 8) - ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg + ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 [always], $noreg BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg + ; CHECK: BX_RET 14 [always], $noreg ... --- name: test_fpconst_8bit_s32 @@ -95,14 +95,14 @@ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_FCONSTANT float -2.0 - ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14, $noreg - ; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool) + ; VFP3: [[VREG:%[0-9]+]]:spr = FCONSTS 128, 14 [always], $noreg + ; VFP2: [[VREG:%[0-9]+]]:spr = VLDRS %const.0, 0, 14 [always], $noreg :: (load 4 from constant-pool) G_STORE %1(s32), %0 :: (store 4) - ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14, $noreg + ; CHECK: VSTRS [[VREG]], [[PTR]], 0, 14 [always], $noreg BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg + ; CHECK: BX_RET 14 [always], $noreg ... --- name: test_fpconst_8bit_s64 @@ -128,12 +128,12 @@ ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s64) = G_FCONSTANT double 5.0e-1 - ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14, $noreg - ; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool) + ; VFP3: [[VREG:%[0-9]+]]:dpr = FCONSTD 96, 14 [always], $noreg + ; VFP2: [[VREG:%[0-9]+]]:dpr = VLDRD %const.0, 0, 14 [always], $noreg :: (load 8 from constant-pool) G_STORE %1(s64), %0 :: (store 8) - ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14, $noreg + ; CHECK: VSTRD [[VREG]], [[PTR]], 0, 14 [always], $noreg BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg + ; CHECK: BX_RET 14 [always], $noreg ... Index: llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-fp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple arm-- -mattr=+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+vfp4,-neonfp -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | @@ -69,10 +70,10 @@ ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]] G_STORE %1(s32), %2 :: (store 4) - ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14, $noreg + ; CHECK: STRi12 [[VREGTRUNC]], [[PTR]], 0, 14 [always], $noreg BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg + ; CHECK: BX_RET 14 [always], $noreg ... --- name: test_fadd_s32 @@ -96,13 +97,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VADDS [[VREGX]], [[VREGY]], 14 [always], $noreg $s0 = COPY %2(s32) ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fadd_s64 @@ -126,13 +127,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDD [[VREGX]], [[VREGY]], 14 [always], $noreg $d0 = COPY %2(s64) ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fsub_s32 @@ -156,13 +157,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VSUBS [[VREGX]], [[VREGY]], 14 [always], $noreg $s0 = COPY %2(s32) ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fsub_s64 @@ -186,13 +187,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FSUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBD [[VREGX]], [[VREGY]], 14 [always], $noreg $d0 = COPY %2(s64) ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fmul_s32 @@ -216,13 +217,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VMULS [[VREGX]], [[VREGY]], 14 [always], $noreg $s0 = COPY %2(s32) ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fmul_s64 @@ -246,13 +247,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FMUL %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VMULD [[VREGX]], [[VREGY]], 14 [always], $noreg $d0 = COPY %2(s64) ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fdiv_s32 @@ -276,13 +277,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:spr = COPY $s1 %2(s32) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VDIVS [[VREGX]], [[VREGY]], 14 [always], $noreg $s0 = COPY %2(s32) ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fdiv_s64 @@ -306,13 +307,13 @@ ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_FDIV %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VDIVD [[VREGX]], [[VREGY]], 14 [always], $noreg $d0 = COPY %2(s64) ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fneg_s32 @@ -332,13 +333,13 @@ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FNEG %0 - ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:spr = VNEGS [[VREGX]], 14 [always], $noreg $s0 = COPY %1(s32) ; CHECK: $s0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fneg_s64 @@ -359,13 +360,13 @@ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = G_FNEG %0 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14, $noreg + ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VNEGD [[VREGX]], 14 [always], $noreg $d0 = COPY %1(s64) ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fma_s32 @@ -393,13 +394,13 @@ ; CHECK: [[VREGZ:%[0-9]+]]:spr = COPY $s2 %3(s32) = G_FMA %0, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:spr = VFMAS [[VREGZ]], [[VREGX]], [[VREGY]], 14 [always], $noreg $s0 = COPY %3(s32) ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fma_s64 @@ -427,13 +428,13 @@ ; CHECK: [[VREGZ:%[0-9]+]]:dpr = COPY $d2 %3(s64) = G_FMA %0, %1, %2 - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:dpr = VFMAD [[VREGZ]], [[VREGX]], [[VREGY]], 14 [always], $noreg $d0 = COPY %3(s64) ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fpext_s32_to_s64 @@ -453,13 +454,13 @@ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s64) = G_FPEXT %0(s32) - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:dpr = VCVTDS [[VREGX]], 14 [always], $noreg $d0 = COPY %1(s64) ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_fptrunc_s64_to_s32 @@ -479,13 +480,13 @@ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTRUNC %0(s64) - ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:spr = VCVTSD [[VREGX]], 14 [always], $noreg $s0 = COPY %1(s32) ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_fptosi_s32 @@ -505,14 +506,14 @@ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FPTOSI %0(s32) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14, $noreg + ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZS [[VREGX]], 14 [always], $noreg ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_fptosi_s64 @@ -532,14 +533,14 @@ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTOSI %0(s64) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14, $noreg + ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOSIZD [[VREGX]], 14 [always], $noreg ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_fptoui_s32 @@ -559,14 +560,14 @@ ; CHECK: [[VREGX:%[0-9]+]]:spr = COPY $s0 %1(s32) = G_FPTOUI %0(s32) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14, $noreg + ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZS [[VREGX]], 14 [always], $noreg ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_fptoui_s64 @@ -586,14 +587,14 @@ ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s32) = G_FPTOUI %0(s64) - ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14, $noreg + ; CHECK: [[VREGI:%[0-9]+]]:spr = VTOUIZD [[VREGX]], 14 [always], $noreg ; CHECK: [[VREGR:%[0-9]+]]:gpr = COPY [[VREGI]] $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_sitofp_s32 @@ -614,13 +615,13 @@ %1(s32) = G_SITOFP %0(s32) ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:spr = VSITOS [[VREGF]], 14 [always], $noreg $s0 = COPY %1(s32) ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_sitofp_s64 @@ -641,13 +642,13 @@ %1(s64) = G_SITOFP %0(s32) ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:dpr = VSITOD [[VREGF]], 14 [always], $noreg $d0 = COPY %1(s64) ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_uitofp_s32 @@ -668,13 +669,13 @@ %1(s32) = G_UITOFP %0(s32) ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:spr = VUITOS [[VREGF]], 14 [always], $noreg $s0 = COPY %1(s32) ; CHECK: $s0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_uitofp_s64 @@ -695,13 +696,13 @@ %1(s64) = G_UITOFP %0(s32) ; CHECK: [[VREGF:%[0-9]+]]:spr = COPY [[VREGX]] - ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14, $noreg + ; CHECK: [[VREGR:%[0-9]+]]:dpr = VUITOD [[VREGF]], 14 [always], $noreg $d0 = COPY %1(s64) ; CHECK: $d0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_load_f32 @@ -721,13 +722,13 @@ ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s32) = G_LOAD %0(p0) :: (load 4) - ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14, $noreg + ; CHECK: %[[V:[0-9]+]]:spr = VLDRS %[[P]], 0, 14 [always], $noreg $s0 = COPY %1 ; CHECK: $s0 = COPY %[[V]] BX_RET 14, $noreg, implicit $s0 - ; CHECK: BX_RET 14, $noreg, implicit $s0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $s0 ... --- name: test_load_f64 @@ -747,13 +748,13 @@ ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s64) = G_LOAD %0(p0) :: (load 8) - ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14, $noreg + ; CHECK: %[[V:[0-9]+]]:dpr = VLDRD %[[P]], 0, 14 [always], $noreg $d0 = COPY %1 ; CHECK: $d0 = COPY %[[V]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_stores @@ -778,10 +779,10 @@ %2(s64) = COPY $d2 G_STORE %1(s32), %0(p0) :: (store 4) - ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, $noreg + ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14 [always], $noreg G_STORE %2(s64), %0(p0) :: (store 8) - ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14, $noreg + ; CHECK: VSTRD %[[F64]], %[[P]], 0, 14 [always], $noreg BX_RET 14, $noreg ... @@ -829,7 +830,7 @@ ; CHECK: {{%[0-9]+}}:dpr = PHI [[V1]], %[[BB1]], [[V2]], %[[BB2]] $d0 = COPY %4(s64) - BX_RET 14, $noreg, implicit $d0 + BX_RET 14 [always], $noreg, implicit $d0 ... --- name: test_soft_fp_double @@ -867,5 +868,5 @@ ; CHECK: $r1 = COPY [[OUT2]] BX_RET 14, $noreg, implicit $r0, implicit $r1 - ; CHECK: BX_RET 14, $noreg, implicit $r0, implicit $r1 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0, implicit $r1 ... Index: llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-neon.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple arm-- -mattr=+neon -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | @@ -6,11 +7,9 @@ ... --- name: test_add_s64 -# CHECK-LABEL: name: test_add_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -19,28 +18,27 @@ bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_add_s64 + ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK: [[VADDv1i64_:%[0-9]+]]:dpr = VADDv1i64 [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $d0 = COPY [[VADDv1i64_]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_ADD %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VADDv1i64 [[VREGX]], [[VREGY]], 14, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 ... --- name: test_sub_s64 -# CHECK-LABEL: name: test_sub_s64 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: fprb } - { id: 1, class: fprb } @@ -49,18 +47,19 @@ bb.0: liveins: $d0, $d1 + ; CHECK-LABEL: name: test_sub_s64 + ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK: [[VSUBv1i64_:%[0-9]+]]:dpr = VSUBv1i64 [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $d0 = COPY [[VSUBv1i64_]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $d0 %0(s64) = COPY $d0 - ; CHECK: [[VREGX:%[0-9]+]]:dpr = COPY $d0 %1(s64) = COPY $d1 - ; CHECK: [[VREGY:%[0-9]+]]:dpr = COPY $d1 %2(s64) = G_SUB %0, %1 - ; CHECK: [[VREGSUM:%[0-9]+]]:dpr = VSUBv1i64 [[VREGX]], [[VREGY]], 14, $noreg $d0 = COPY %2(s64) - ; CHECK: $d0 = COPY [[VREGSUM]] BX_RET 14, $noreg, implicit $d0 - ; CHECK: BX_RET 14, $noreg, implicit $d0 Index: llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-pkhbt.mir @@ -46,14 +46,14 @@ %7(s32) = G_AND %5, %6 %8(s32) = G_OR %3, %7 - ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 [always], $noreg $r0 = COPY %8(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_pkhbt_commutative @@ -92,14 +92,14 @@ %7(s32) = G_AND %5, %6 %8(s32) = G_OR %7, %3 - ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 7, 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 7, 14 [always], $noreg $r0 = COPY %8(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_pkhbt_imm16_31 @@ -134,14 +134,14 @@ %5(s32) = G_SHL %1, %4 %6(s32) = G_OR %3, %5 - ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 17, 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 17, 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 17, 14 [always], $noreg $r0 = COPY %6(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_pkhbt_unshifted @@ -176,14 +176,14 @@ %5(s32) = G_AND %1, %4 %6(s32) = G_OR %3, %5 - ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 0, 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHBT [[VREGX]], [[VREGY]], 0, 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHBT [[VREGX]], [[VREGY]], 0, 14 [always], $noreg $r0 = COPY %6(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_pkhtb_imm16 @@ -218,14 +218,14 @@ %5(s32) = G_LSHR %1, %4 %6(s32) = G_OR %3, %5 - ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 16, 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 16, 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 16, 14 [always], $noreg $r0 = COPY %6(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_pkhtb_imm1_15 @@ -264,12 +264,12 @@ %7(s32) = G_AND %5, %6 %8(s32) = G_OR %3, %7 - ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg - ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 7, 14, $noreg + ; ARM: [[VREGR:%[0-9]+]]:gprnopc = PKHTB [[VREGX]], [[VREGY]], 7, 14 [always], $noreg + ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2PKHTB [[VREGX]], [[VREGY]], 7, 14 [always], $noreg $r0 = COPY %8(s32) ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-pr35926.mir @@ -1,17 +1,18 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple arm-gnueabihf -mattr=+vfp4 -run-pass=instruction-select -o - %s | FileCheck %s --- | declare double @llvm.fma.f64(double, double, double) #0 - + define double @vfnmsd(double %x, double %y, double %z) #1 { %minus.y = fsub double -0.000000e+00, %y %fma = tail call double @llvm.fma.f64(double %x, double %minus.y, double %z) %minus.fma = fsub double -0.000000e+00, %fma ret double %minus.fma } - + ; Function Attrs: nounwind declare void @llvm.stackprotector(i8*, i8**) #2 - + attributes #0 = { nounwind readnone speculatable "target-features"="+vfp4" } attributes #1 = { "target-features"="+vfp4" } attributes #2 = { nounwind } @@ -25,7 +26,14 @@ body: | bb.1 (%ir-block.0): liveins: $d0, $d1, $d2 - + + ; CHECK-LABEL: name: vfnmsd + ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0 + ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1 + ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2 + ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $d0 = COPY [[VFNMSD]] + ; CHECK: MOVPCLR 14 [always], $noreg, implicit $d0 %0:fprb(s64) = COPY $d0 %1:fprb(s64) = COPY $d1 %2:fprb(s64) = COPY $d2 @@ -35,6 +43,5 @@ $d0 = COPY %5(s64) MOVPCLR 14, $noreg, implicit $d0 -# CHECK: %{{[0-9]+}}:dpr = VFNMSD %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, 14, $noreg ... Index: llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir +++ llvm/test/CodeGen/ARM/GlobalISel/select-revsh.mir @@ -51,7 +51,7 @@ ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_shifts_to_revsh_commutative @@ -99,7 +99,7 @@ ; CHECK: $r0 = COPY [[VREGR]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_shifts_no_revsh_constants Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-instruction-select-cmp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_icmp_eq_s32() { ret void } @@ -28,12 +29,12 @@ ; CHECK-LABEL: name: test_icmp_eq_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 0, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 0 [equal], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(eq), %0(s32), %1 @@ -58,12 +59,12 @@ ; CHECK-LABEL: name: test_icmp_ne_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 1, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 1 [notequal], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ne), %0(s32), %1 @@ -88,12 +89,12 @@ ; CHECK-LABEL: name: test_icmp_ugt_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 8, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 8 [higher], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ugt), %0(s32), %1 @@ -118,12 +119,12 @@ ; CHECK-LABEL: name: test_icmp_uge_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 2, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 2 [highersame], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(uge), %0(s32), %1 @@ -148,12 +149,12 @@ ; CHECK-LABEL: name: test_icmp_ult_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 3, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 3 [lower], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ult), %0(s32), %1 @@ -178,12 +179,12 @@ ; CHECK-LABEL: name: test_icmp_ule_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 9, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 9 [lowersame], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(ule), %0(s32), %1 @@ -208,12 +209,12 @@ ; CHECK-LABEL: name: test_icmp_sgt_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 12, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 12 [greater], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(sgt), %0(s32), %1 @@ -238,12 +239,12 @@ ; CHECK-LABEL: name: test_icmp_sge_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 10, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 10 [greaterequal], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(sge), %0(s32), %1 @@ -268,12 +269,12 @@ ; CHECK-LABEL: name: test_icmp_slt_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 11, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 11 [less], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(slt), %0(s32), %1 @@ -298,12 +299,12 @@ ; CHECK-LABEL: name: test_icmp_sle_s32 ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 - ; CHECK: [[MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14, $noreg, implicit-def $cpsr - ; CHECK: [[MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[MOVi]], 1, 13, $cpsr - ; CHECK: [[ANDri:%[0-9]+]]:rgpr = t2ANDri [[MOVCCi]], 1, 14, $noreg, $noreg - ; CHECK: $r0 = COPY [[ANDri]] - ; CHECK: BX_RET 14, $noreg, implicit $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[COPY]], [[COPY1]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 1, 13 [lessequal], $cpsr + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2MOVCCi]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 %2(s1) = G_ICMP intpred(sle), %0(s32), %1 Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_add_regs() { ret void } @@ -16,11 +17,9 @@ ... --- name: test_add_regs -# CHECK-LABEL: name: test_add_regs legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -29,28 +28,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_add_regs + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ADDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_add_fold_imm -# CHECK-LABEL: name: test_add_fold_imm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -59,26 +57,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_add_fold_imm + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 786444, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ADDri [[VREGX]], 786444, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_add_fold_imm12 -# CHECK-LABEL: name: test_add_fold_imm12 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -87,26 +84,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_add_fold_imm12 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[t2ADDri12_:%[0-9]+]]:rgpr = t2ADDri12 [[COPY]], 4093, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2ADDri12_]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY $r0 %1(s32) = G_CONSTANT i32 4093 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ADDri12 [[VREGX]], 4093, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_add_no_fold_imm -# CHECK-LABEL: name: test_add_no_fold_imm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -115,28 +111,27 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_add_no_fold_imm + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479 + ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[t2MOVi32imm]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ADDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479 %2(s32) = G_ADD %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:gprnopc = t2ADDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sub_imm_lhs -# CHECK-LABEL: name: test_sub_imm_lhs legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -145,26 +140,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_sub_imm_lhs + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[COPY]], 786444, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2RSBri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %2(s32) = G_SUB %1, %0 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2RSBri [[VREGX]], 786444, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sub_imm_rhs -# CHECK-LABEL: name: test_sub_imm_rhs legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -173,26 +167,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_sub_imm_rhs + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 786444, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2SUBri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %2(s32) = G_SUB %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2SUBri [[VREGX]], 786444, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mul -# CHECK-LABEL: name: test_mul legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -201,28 +194,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_mul + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2MUL:%[0-9]+]]:rgpr = t2MUL [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2MUL]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_MUL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MUL [[VREGX]], [[VREGY]], 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_mla -# CHECK-LABEL: name: test_mla legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -233,32 +225,31 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_mla + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r2 + ; CHECK: [[t2MLA:%[0-9]+]]:rgpr = t2MLA [[COPY]], [[COPY1]], [[COPY2]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2MLA]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGZ:%[0-9]+]]:rgpr = COPY $r2 %3(s32) = G_MUL %0, %1 %4(s32) = G_ADD %3, %2 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MLA [[VREGX]], [[VREGY]], [[VREGZ]], 14, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_sdiv -# CHECK-LABEL: name: test_sdiv legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -267,28 +258,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_sdiv + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2SDIV]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_SDIV %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2SDIV [[VREGX]], [[VREGY]], 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_udiv -# CHECK-LABEL: name: test_udiv legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -297,18 +287,19 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_udiv + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2UDIV:%[0-9]+]]:rgpr = t2UDIV [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2UDIV]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_UDIV %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2UDIV [[VREGX]], [[VREGY]], 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-br.mir @@ -1,44 +1,46 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_br() { ret void } ... --- name: test_br -# CHECK-LABEL: name: test_br legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } body: | + ; CHECK-LABEL: name: test_br + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: t2TSTri [[COPY1]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.1, 1 [notequal], $cpsr + ; CHECK: t2B %bb.2, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: t2B %bb.2, 14 [always], $noreg + ; CHECK: bb.2: + ; CHECK: tBX_RET 14 [always], $noreg bb.0: - ; CHECK: bb.0 successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0 %0(s32) = COPY $r0 - ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) - ; CHECK: [[COND:%[0-9]+]]:rgpr = COPY [[COND32]] G_BRCOND %1(s1), %bb.1 - ; CHECK: t2TSTri [[COND]], 1, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.1, 1, $cpsr G_BR %bb.2 - ; CHECK: t2B %bb.2, 14, $noreg bb.1: - ; CHECK: bb.1 successors: %bb.2(0x80000000) G_BR %bb.2 - ; CHECK: t2B %bb.2, 14, $noreg bb.2: - ; CHECK: bb.2 tBX_RET 14, $noreg - ; CHECK: tBX_RET 14, $noreg ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-exts.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_trunc_and_zext_s1_to_s32() { ret void } @@ -26,11 +27,9 @@ ... --- name: test_trunc_and_zext_s1_to_s32 -# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -40,28 +39,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) %2(s32) = G_ZEXT %1(s1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_sext_s1_to_s32 -# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -71,29 +70,29 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY1]], 1, 14 [always], $noreg, $noreg + ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2RSBri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) %2(s32) = G_SEXT %1(s1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_anyext_s1_to_s32 -# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -103,26 +102,26 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s1) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s1) $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREG]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_zext_s8_to_s32 -# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -132,28 +131,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY1]], 0, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2UXTB]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s8) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]] %2(s32) = G_ZEXT %1(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_sext_s8_to_s32 -# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -163,28 +162,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY1]], 0, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2SXTB]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s8) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]] %2(s32) = G_SEXT %1(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_anyext_s8_to_s32 -# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -194,26 +193,26 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s8) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s8) $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREG]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_zext_s16_to_s32 -# CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -223,28 +222,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_zext_s16_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: [[t2UXTH:%[0-9]+]]:rgpr = t2UXTH [[COPY1]], 0, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2UXTH]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s16) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]] %2(s32) = G_ZEXT %1(s16) - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTH [[VREGTRUNC]], 0, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_sext_s16_to_s32 -# CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -254,28 +253,28 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_sext_s16_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY [[COPY]] + ; CHECK: [[t2SXTH:%[0-9]+]]:rgpr = t2SXTH [[COPY1]], 0, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2SXTH]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s16) = G_TRUNC %0(s32) - ; CHECK: [[VREGTRUNC:%[0-9]+]]:rgpr = COPY [[VREG]] %2(s32) = G_SEXT %1(s16) - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTH [[VREGTRUNC]], 0, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGEXT]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_anyext_s16_to_s32 -# CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -285,26 +284,26 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_trunc_and_anyext_s16_to_s32 + ; CHECK: liveins: $r0 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0 %1(s16) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s16) $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREG]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_trunc_and_zext_s1_to_s16 -# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -315,31 +314,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 [always], $noreg, $noreg + ; CHECK: t2STRHi12 [[t2ANDri]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s16) = G_ZEXT %2(s1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_sext_s1_to_s16 -# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -350,32 +349,32 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 [always], $noreg, $noreg + ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 [always], $noreg, $noreg + ; CHECK: t2STRHi12 [[t2RSBri]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s16) = G_SEXT %2(s1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_anyext_s1_to_s16 -# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -386,30 +385,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s16) = G_ANYEXT %2(s1) G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: t2STRHi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_zext_s8_to_s16 -# CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -420,31 +419,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_zext_s8_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY2]], 0, 14 [always], $noreg + ; CHECK: t2STRHi12 [[t2UXTB]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s8) = G_TRUNC %1(s32) - ; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]] %3(s16) = G_ZEXT %2(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2UXTB [[VREGTRUNC]], 0, 14, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_sext_s8_to_s16 -# CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -455,31 +454,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_sext_s8_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: [[t2SXTB:%[0-9]+]]:rgpr = t2SXTB [[COPY2]], 0, 14 [always], $noreg + ; CHECK: t2STRHi12 [[t2SXTB]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s8) = G_TRUNC %1(s32) - ; CHECK: [[VREGTRUNC:%[1-9]+]]:rgpr = COPY [[VREG]] %3(s16) = G_SEXT %2(s8) - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2SXTB [[VREGTRUNC]], 0, 14, $noreg G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: t2STRHi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_anyext_s8_to_s16 -# CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -490,30 +489,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_anyext_s8_to_s16 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: t2STRHi12 [[COPY2]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s8) = G_TRUNC %1(s32) %3(s16) = G_ANYEXT %2(s8) G_STORE %3(s16), %0(p0) :: (store 2) - ; CHECK: [[VREGR:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: t2STRHi12 [[VREGR]], [[PTR]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_zext_s1_to_s8 -# CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -524,31 +523,31 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_zext_s1_to_s8 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 [always], $noreg, $noreg + ; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s8) = G_ZEXT %2(s1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg G_STORE %3(s8), %0(p0) :: (store 1) - ; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_sext_s1_to_s8 -# CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -559,32 +558,32 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_sext_s1_to_s8 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY2]], 1, 14 [always], $noreg, $noreg + ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[t2ANDri]], 0, 14 [always], $noreg, $noreg + ; CHECK: t2STRBi12 [[t2RSBri]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s8) = G_SEXT %2(s1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: [[VREGAND:%[0-9]+]]:rgpr = t2ANDri [[RVREG]], 1, 14, $noreg, $noreg - ; CHECK: [[VREGEXT:%[0-9]+]]:rgpr = t2RSBri [[VREGAND]], 0, 14, $noreg, $noreg G_STORE %3(s8), %0(p0) :: (store 1) - ; CHECK: t2STRBi12 [[VREGEXT]], [[PTR]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_trunc_and_anyext_s1_to_s8 -# CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true tracksRegLiveness: true registers: - { id: 0, class: gprb } @@ -595,20 +594,22 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_trunc_and_anyext_s1_to_s8 + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY [[COPY1]] + ; CHECK: t2STRBi12 [[COPY2]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s8) = G_ANYEXT %2(s1) G_STORE %3(s8), %0(p0) :: (store 1) - ; CHECK: [[RVREG:%[0-9]+]]:rgpr = COPY [[VREG]] - ; CHECK: t2STRBi12 [[RVREG]], [[PTR]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-pic.mir @@ -33,13 +33,13 @@ ; ELF: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_global @@ -55,20 +55,20 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; DARWIN-MOVT: [[G_GOT:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @external_global - ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) + ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 [always], $noreg :: (load 4 from got) ; DARWIN-NOMOVT: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @external_global - ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) + ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 [always], $noreg :: (load 4 from got) ; ELF: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-got) @external_global - ; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) + ; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 [always], $noreg :: (load 4 from got) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_internal_constant @@ -88,13 +88,13 @@ ; ELF: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_constant @@ -110,18 +110,18 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @external_constant ; DARWIN-MOVT: [[G_GOT:%[0-9]+]]:rgpr = t2MOV_ga_pcrel target-flags(arm-nonlazy) @external_constant - ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) + ; DARWIN-MOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 [always], $noreg :: (load 4 from got) ; DARWIN-NOMOVT: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-nonlazy) @external_constant - ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) + ; DARWIN-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 [always], $noreg :: (load 4 from got) ; ELF: [[G_GOT:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel target-flags(arm-got) @external_constant - ; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14, $noreg :: (load 4 from got) + ; ELF: [[G:%[0-9]+]]:gpr = t2LDRi12 [[G_GOT]], 0, 14 [always], $noreg :: (load 4 from got) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-ropi-rwpi.mir @@ -37,19 +37,19 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @internal_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global - ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) + ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) ; RWPI-MOVT: [[OFF:%[0-9]+]]:rgpr = t2MOVi32imm target-flags(arm-sbrel) @internal_global - ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) - ; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14, $noreg, $noreg + ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) + ; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14 [always], $noreg, $noreg %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_global @@ -71,19 +71,19 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; RW-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global - ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) + ; RW-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) ; RWPI-MOVT: [[OFF:%[0-9]+]]:rgpr = t2MOVi32imm target-flags(arm-sbrel) @external_global - ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) - ; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14, $noreg, $noreg + ; RWPI-NOMOVT: [[OFF:%[0-9]+]]:rgpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) + ; RWPI: [[G:%[0-9]+]]:gprnopc = t2ADDrr $r9, [[OFF]], 14 [always], $noreg, $noreg %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_internal_constant @@ -104,16 +104,16 @@ ; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @internal_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @internal_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_constant - ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) + ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_constant @@ -134,14 +134,14 @@ ; ROPI-MOVT: [[G:%[0-9]+]]:rgpr = t2MOV_ga_pcrel @external_constant ; ROPI-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_pcrel @external_constant ; RO-DEFAULT-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_constant - ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) + ; RO-DEFAULT-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_constant) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_constant) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_constant) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-globals-static.mir @@ -26,18 +26,18 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @internal_global ; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global - ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) + ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @internal_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @internal_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @internal_global) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @internal_global) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @internal_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... --- name: test_external_global @@ -56,16 +56,16 @@ bb.0: %0(p0) = G_GLOBAL_VALUE @external_global ; ELF-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global - ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) + ; ELF-NOMOVT: [[G:%[0-9]+]]:gpr = t2LDRpci %const.0, 14 [always], $noreg :: (load 4 from constant-pool) ; DARWIN-MOVT: [[G:%[0-9]+]]:rgpr = t2MOVi32imm @external_global ; DARWIN-NOMOVT: [[G:%[0-9]+]]:tgpr = tLDRLIT_ga_abs @external_global %1(s32) = G_LOAD %0(p0) :: (load 4 from @external_global) - ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14, $noreg :: (load 4 from @external_global) + ; CHECK: [[V:%[0-9]+]]:gpr = t2LDRi12 [[G]], 0, 14 [always], $noreg :: (load 4 from @external_global) $r0 = COPY %1(s32) ; CHECK: $r0 = COPY [[V]] tBX_RET 14, $noreg, implicit $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-imm.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_movi() { ret void } @@ -6,61 +7,58 @@ ... --- name: test_movi -# CHECK-LABEL: name: test_movi legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_movi + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 786444, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2MOVi]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = G_CONSTANT i32 786444 ; 0x000c000c - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MOVi 786444, 14, $noreg, $noreg $r0 = COPY %0(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_movi16 -# CHECK-LABEL: name: test_movi16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_movi16 + ; CHECK: [[t2MOVi16_:%[0-9]+]]:rgpr = t2MOVi16 65533, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2MOVi16_]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = G_CONSTANT i32 65533 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MOVi16 65533, 14, $noreg $r0 = COPY %0(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_movi32 -# CHECK-LABEL: name: test_movi32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } body: | bb.0: + ; CHECK-LABEL: name: test_movi32 + ; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479 + ; CHECK: $r0 = COPY [[t2MOVi32imm]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi32imm 185470479 $r0 = COPY %0(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_s1() { ret void } @@ -11,11 +12,9 @@ ... --- name: test_s1 -# CHECK-LABEL: name: test_s1 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -23,26 +22,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_s1 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 [always], $noreg :: (load 1) + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[t2LDRBi12_]], 1, 14 [always], $noreg, $noreg + ; CHECK: t2STRBi12 [[t2ANDri]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s1) = G_LOAD %0(p0) :: (load 1) - ; CHECK: %[[V8:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1) G_STORE %1(s1), %0(p0) :: (store 1) - ; CHECK: %[[V1:[0-9]+]]:rgpr = t2ANDri %[[V8]], 1, 14, $noreg - ; CHECK: t2STRBi12 %[[V1]], %[[P]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_s8 -# CHECK-LABEL: name: test_s8 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -50,25 +48,24 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_s8 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 [always], $noreg :: (load 1) + ; CHECK: t2STRBi12 [[t2LDRBi12_]], [[COPY]], 0, 14 [always], $noreg :: (store 1) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s8) = G_LOAD %0(p0) :: (load 1) - ; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRBi12 %[[P]], 0, 14, $noreg :: (load 1) G_STORE %1(s8), %0(p0) :: (store 1) - ; CHECK: t2STRBi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 1) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_s16 -# CHECK-LABEL: name: test_s16 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -76,25 +73,24 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_s16 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 [always], $noreg :: (load 2) + ; CHECK: t2STRHi12 [[t2LDRHi12_]], [[COPY]], 0, 14 [always], $noreg :: (store 2) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s16) = G_LOAD %0(p0) :: (load 2) - ; CHECK: %[[V:[0-9]+]]:rgpr = t2LDRHi12 %[[P]], 0, 14, $noreg :: (load 2) G_STORE %1(s16), %0(p0) :: (store 2) - ; CHECK: t2STRHi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 2) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_s32 -# CHECK-LABEL: name: test_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -102,25 +98,24 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_s32 + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 + ; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[COPY]], 0, 14 [always], $noreg :: (load 4) + ; CHECK: t2STRi12 [[t2LDRi12_]], [[COPY]], 0, 14 [always], $noreg :: (store 4) + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = COPY $r0 - ; CHECK: %[[P:[0-9]+]]:gpr = COPY $r0 %1(s32) = G_LOAD %0(p0) :: (load 4) - ; CHECK: %[[V:[0-9]+]]:gpr = t2LDRi12 %[[P]], 0, 14, $noreg :: (load 4) G_STORE %1(s32), %0(p0) :: (store 4) - ; CHECK: t2STRi12 %[[V]], %[[P]], 0, 14, $noreg :: (store 4) BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... --- name: test_gep -# CHECK-LABEL: name: test_gep legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -129,28 +124,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_gep + ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ADDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(p0) = COPY $r0 - ; CHECK: [[PTR:%[0-9]+]]:gprnopc = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[OFF:%[0-9]+]]:rgpr = COPY $r1 %2(p0) = G_PTR_ADD %0, %1(s32) - ; CHECK: [[GEP:%[0-9]+]]:gprnopc = t2ADDrr [[PTR]], [[OFF]], 14, $noreg, $noreg $r0 = COPY %2(p0) - ; CHECK: $r0 = COPY [[GEP]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_load_from_stack -# CHECK-LABEL: name: test_load_from_stack legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -161,33 +155,32 @@ - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } -# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 -# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 body: | bb.0: liveins: $r0, $r1, $r2, $r3 + ; CHECK-LABEL: name: test_load_from_stack + ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.0, 0, 14 [always], $noreg, $noreg + ; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[t2ADDri]], 0, 14 [always], $noreg :: (load 4) + ; CHECK: $r0 = COPY [[t2LDRi12_]] + ; CHECK: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.2, 0, 14 [always], $noreg, $noreg + ; CHECK: [[t2LDRBi12_:%[0-9]+]]:gprnopc = t2LDRBi12 [[t2ADDri1]], 0, 14 [always], $noreg :: (load 1) + ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[t2LDRBi12_]] + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: BX_RET 14 [always], $noreg %0(p0) = G_FRAME_INDEX %fixed-stack.2 - ; CHECK: [[FI32VREG:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.[[FI32]], 0, 14, $noreg, $noreg %1(s32) = G_LOAD %0(p0) :: (load 4) - ; CHECK: [[LD32VREG:%[0-9]+]]:gpr = t2LDRi12 [[FI32VREG]], 0, 14, $noreg $r0 = COPY %1 - ; CHECK: $r0 = COPY [[LD32VREG]] %2(p0) = G_FRAME_INDEX %fixed-stack.0 - ; CHECK: [[FI1VREG:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.[[FI1]], 0, 14, $noreg, $noreg %3(s1) = G_LOAD %2(p0) :: (load 1) - ; CHECK: [[LD1VREG:%[0-9]+]]:gprnopc = t2LDRBi12 [[FI1VREG]], 0, 14, $noreg %4(s32) = G_ANYEXT %3(s1) - ; CHECK: [[RES:%[0-9]+]]:gpr = COPY [[LD1VREG]] $r0 = COPY %4 - ; CHECK: $r0 = COPY [[RES]] BX_RET 14, $noreg - ; CHECK: BX_RET 14, $noreg ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-logical-ops.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_and_regs() { ret void } @@ -12,11 +13,9 @@ ... --- name: test_and_regs -# CHECK-LABEL: name: test_and_regs legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -25,28 +24,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_and_regs + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2ANDrr:%[0-9]+]]:rgpr = t2ANDrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_AND %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_and_imm -# CHECK-LABEL: name: test_and_imm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -55,26 +53,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_and_imm + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %2(s32) = G_AND %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ANDri [[VREGX]], 786444, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bfc -# CHECK-LABEL: name: test_bfc legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -83,26 +80,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_bfc + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2BFC:%[0-9]+]]:rgpr = t2BFC [[COPY]], -65529, 14 [always], $noreg + ; CHECK: $r0 = COPY [[t2BFC]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CONSTANT i32 -65529 ; 0xFFFF0007 %2(s32) = G_AND %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BFC [[VREGX]], -65529, 14, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_no_bfc_bad_mask -# CHECK-LABEL: name: test_no_bfc_bad_mask legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -111,11 +107,15 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_no_bfc_bad_mask + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2ANDri:%[0-9]+]]:rgpr = t2ANDri [[COPY]], 786444, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ANDri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c %2(s32) = G_AND %0, %1 - ; CHECK-NOT: t2BFC $r0 = COPY %2(s32) @@ -123,11 +123,9 @@ ... --- name: test_mvn -# CHECK-LABEL: name: test_mvn legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -136,26 +134,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_mvn + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2MVNr:%[0-9]+]]:rgpr = t2MVNr [[COPY]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2MVNr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CONSTANT i32 -1 %2(s32) = G_XOR %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2MVNr [[VREGX]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_bic -# CHECK-LABEL: name: test_bic legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -166,30 +163,29 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_bic + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2BICrr:%[0-9]+]]:rgpr = t2BICrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2BICrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_AND %0, %3 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2BICrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_orn -# CHECK-LABEL: name: test_orn legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -200,20 +196,21 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_orn + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2ORNrr:%[0-9]+]]:rgpr = t2ORNrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ORNrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 %1(s32) = COPY $r1 - ; CHECK-DAG: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 - ; CHECK-DAG: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_CONSTANT i32 -1 %3(s32) = G_XOR %1, %2 %4(s32) = G_OR %0, %3 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ORNrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %4(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-select.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_select_s32() { ret void } @@ -5,11 +6,9 @@ ... --- name: test_select_s32 -# CHECK-LABEL: name: test_select_s32 legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -19,31 +18,30 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_select_s32 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: t2TSTri [[COPY1]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 [equal], $cpsr + ; CHECK: $r0 = COPY [[t2MOVCCr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s1) = G_TRUNC %1(s32) %3(s32) = G_SELECT %2(s1), %0, %1 - ; CHECK: t2TSTri [[VREGY]], 1, 14, $noreg, implicit-def $cpsr - ; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr $r0 = COPY %3(s32) - ; CHECK: $r0 = COPY [[RES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_select_ptr -# CHECK-LABEL: name: test_select_ptr legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -54,25 +52,26 @@ bb.0: liveins: $r0, $r1, $r2 + ; CHECK-LABEL: name: test_select_ptr + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[COPY2:%[0-9]+]]:gpr = COPY $r2 + ; CHECK: [[COPY3:%[0-9]+]]:rgpr = COPY [[COPY2]] + ; CHECK: t2TSTri [[COPY3]], 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: [[t2MOVCCr:%[0-9]+]]:rgpr = t2MOVCCr [[COPY]], [[COPY1]], 0 [equal], $cpsr + ; CHECK: $r0 = COPY [[t2MOVCCr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(p0) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(p0) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = COPY $r2 - ; CHECK: [[VREGC32:%[0-9]+]]:gpr = COPY $r2 %3(s1) = G_TRUNC %2(s32) - ; CHECK: [[VREGC:%[0-9]+]]:rgpr = COPY [[VREGC32]] %4(p0) = G_SELECT %3(s1), %0, %1 - ; CHECK: t2TSTri [[VREGC]], 1, 14, $noreg, implicit-def $cpsr - ; CHECK: [[RES:%[0-9]+]]:rgpr = t2MOVCCr [[VREGX]], [[VREGY]], 0, $cpsr $r0 = COPY %4(p0) - ; CHECK: $r0 = COPY [[RES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir =================================================================== --- llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir +++ llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --- | define void @test_ashr_rr() { ret void } @@ -7,11 +8,9 @@ ... --- name: test_ashr_rr -# CHECK-LABEL: name: test_ashr_rr legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -20,28 +19,27 @@ bb.0: liveins: $r0, $r1 + ; CHECK-LABEL: name: test_ashr_rr + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[COPY1]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2ASRrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = COPY $r1 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = COPY $r1 %2(s32) = G_ASHR %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2ASRrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_shl_ri -# CHECK-LABEL: name: test_shl_ri legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -50,26 +48,25 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_shl_ri + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 31, 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2LSLri]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CONSTANT i32 31 %2(s32) = G_SHL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2LSLri [[VREGX]], 31, 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... --- name: test_shl_ri_bad_imm -# CHECK-LABEL: name: test_shl_ri_bad_imm legalized: true regBankSelected: true selected: false -# CHECK: selected: true registers: - { id: 0, class: gprb } - { id: 1, class: gprb } @@ -78,18 +75,19 @@ bb.0: liveins: $r0 + ; CHECK-LABEL: name: test_shl_ri_bad_imm + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 32, 14 [always], $noreg, $noreg + ; CHECK: [[t2LSLrr:%[0-9]+]]:rgpr = t2LSLrr [[COPY]], [[t2MOVi]], 14 [always], $noreg, $noreg + ; CHECK: $r0 = COPY [[t2LSLrr]] + ; CHECK: BX_RET 14 [always], $noreg, implicit $r0 %0(s32) = COPY $r0 - ; CHECK: [[VREGX:%[0-9]+]]:rgpr = COPY $r0 %1(s32) = G_CONSTANT i32 32 - ; CHECK: [[VREGY:%[0-9]+]]:rgpr = t2MOVi 32, 14, $noreg, $noreg %2(s32) = G_SHL %0, %1 - ; CHECK: [[VREGRES:%[0-9]+]]:rgpr = t2LSLrr [[VREGX]], [[VREGY]], 14, $noreg, $noreg $r0 = COPY %2(s32) - ; CHECK: $r0 = COPY [[VREGRES]] BX_RET 14, $noreg, implicit $r0 - ; CHECK: BX_RET 14, $noreg, implicit $r0 ... Index: llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir =================================================================== --- llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir +++ llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s --- | @@ -17,7 +18,6 @@ ... --- name: f -# CHECK-LABEL: name: f alignment: 2 exposesReturnsTwice: false legalized: false @@ -49,11 +49,23 @@ hasVAStart: false hasMustTailInVarArgFunc: false -# CHECK: tMOVi8 1, 14, $noreg -# CHECK: tMOVi8 0, 14, $noreg -# CHECK: tMUL %1, %0, 14, $noreg -# CHECK-NOT: tCMPi8 body: | + ; CHECK-LABEL: name: f + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 + ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %3:tgpr, $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: %4:tgpr, $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: %2:tgpr, $cpsr = tMUL [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 0 [equal], $cpsr + ; CHECK: bb.1.entry: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: bb.2.entry: + ; CHECK: [[PHI:%[0-9]+]]:tgpr = PHI %4, %bb.1, %3, %bb.0 + ; CHECK: $r0 = COPY [[PHI]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0.entry: liveins: $r0, $r1 Index: llvm/test/CodeGen/ARM/cmpxchg.mir =================================================================== --- llvm/test/CodeGen/ARM/cmpxchg.mir +++ llvm/test/CodeGen/ARM/cmpxchg.mir @@ -1,24 +1,27 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s --- -# CHECK-LABEL: name: func name: func tracksRegLiveness: true body: | bb.0: liveins: $r0_r1, $r4_r5, $r3, $lr + ; CHECK-LABEL: name: func + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $r0_r1, $r4_r5, $r3, $lr + ; CHECK: .1: + ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: $r4_r5, $r3 + ; CHECK: $r0_r1 = LDREXD $r3, 14 [always], $noreg + ; CHECK: CMPrr killed $r0, $r4, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: CMPrr killed $r1, $r5, 0 [equal], killed $cpsr, implicit-def $cpsr + ; CHECK: Bcc %bb.3, 1 [notequal], killed $cpsr + ; CHECK: .2: + ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK: liveins: $r4_r5, $r3 + ; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14 [always], $noreg + ; CHECK: CMPri killed $r2, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: Bcc %bb.1, 1 [notequal], killed $cpsr + ; CHECK: .3: dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic 8) - ; CHECK: bb.0: - ; CHECK: liveins: $r0_r1, $r4_r5, $r3, $lr - ; CHECK: bb.1: - ; CHECK: liveins: $r4_r5, $r3 - ; CHECK: $r0_r1 = LDREXD $r3, 14, $noreg - ; CHECK: CMPrr killed $r0, $r4, 14, $noreg, implicit-def $cpsr - ; CHECK: CMPrr killed $r1, $r5, 0, killed $cpsr, implicit-def $cpsr - ; CHECK: Bcc %bb.3, 1, killed $cpsr - ; CHECK: bb.2: - ; CHECK: liveins: $r4_r5, $r3 - ; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14, $noreg - ; CHECK: CMPri killed $r2, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: Bcc %bb.1, 1, killed $cpsr - ; CHECK: bb.3: ... Index: llvm/test/CodeGen/ARM/codesize-ifcvt.mir =================================================================== --- llvm/test/CodeGen/ARM/codesize-ifcvt.mir +++ llvm/test/CodeGen/ARM/codesize-ifcvt.mir @@ -159,30 +159,30 @@ ; CHECK: bb.0 (%ir-block.0): ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $lr, $r7 - ; CHECK: renamable $r0 = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tTAILJMPdND @extfunc, 1, killed $cpsr, implicit $sp, implicit $sp - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: renamable $r0 = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tTAILJMPdND @extfunc, 1 [notequal], killed $cpsr, implicit $sp, implicit $sp + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r0 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.2, 1, killed $cpsr + ; CHECK: renamable $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.2, 1 [notequal], killed $cpsr ; CHECK: bb.1.b2: ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: tBL 14, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 - ; CHECK: t2B %bb.3, 14, $noreg + ; CHECK: tBL 14 [always], $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 + ; CHECK: t2B %bb.3, 14 [always], $noreg ; CHECK: bb.2.b3: ; CHECK: successors: %bb.3(0x80000000) - ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14, $noreg :: (load 4 from `i32* undef`) - ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14, $noreg, $noreg + ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14 [always], $noreg :: (load 4 from `i32* undef`) + ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14 [always], $noreg, $noreg ; CHECK: bb.3.b5: ; CHECK: liveins: $r0 - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: tBX_RET 0, killed $cpsr - ; CHECK: tTAILJMPdND @extfunc, 14, $noreg, implicit $sp, implicit $sp + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: tBX_RET 0 [equal], killed $cpsr + ; CHECK: tTAILJMPdND @extfunc, 14 [always], $noreg, implicit $sp, implicit $sp bb.0 (%ir-block.0): successors: %bb.1(0x50000000), %bb.6(0x30000000) liveins: $lr, $r7 @@ -281,39 +281,39 @@ ; CHECK: bb.0 (%ir-block.0): ; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000) ; CHECK: liveins: $lr, $r7 - ; CHECK: renamable $r0 = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.6, 1, killed $cpsr + ; CHECK: renamable $r0 = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.6, 1 [notequal], killed $cpsr ; CHECK: bb.1.b1: ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $r7, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r0 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.3, 1, killed $cpsr + ; CHECK: renamable $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.3, 1 [notequal], killed $cpsr ; CHECK: bb.2.b2: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: tBL 14, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 - ; CHECK: t2B %bb.4, 14, $noreg + ; CHECK: tBL 14 [always], $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 + ; CHECK: t2B %bb.4, 14 [always], $noreg ; CHECK: bb.3.b3: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14, $noreg :: (load 4 from `i32* undef`) - ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14, $noreg, $noreg + ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14 [always], $noreg :: (load 4 from `i32* undef`) + ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14 [always], $noreg, $noreg ; CHECK: bb.4.b5: ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000) ; CHECK: liveins: $r0 - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: t2Bcc %bb.6, 1, killed $cpsr + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: t2Bcc %bb.6, 1 [notequal], killed $cpsr ; CHECK: bb.5.b8: ; CHECK: liveins: $lr, $r7 - ; CHECK: tBX_RET 14, $noreg + ; CHECK: tBX_RET 14 [always], $noreg ; CHECK: bb.6.b7: ; CHECK: liveins: $lr, $r7 - ; CHECK: tTAILJMPdND @extfunc, 14, $noreg, implicit $sp, implicit $sp + ; CHECK: tTAILJMPdND @extfunc, 14 [always], $noreg, implicit $sp, implicit $sp bb.0 (%ir-block.0): successors: %bb.1(0x50000000), %bb.6(0x30000000) liveins: $lr, $r7 @@ -412,39 +412,39 @@ ; CHECK: bb.0 (%ir-block.0): ; CHECK: successors: %bb.1(0x50000000), %bb.6(0x30000000) ; CHECK: liveins: $lr, $r7 - ; CHECK: renamable $r0 = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.6, 1, killed $cpsr + ; CHECK: renamable $r0 = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.6, 1 [notequal], killed $cpsr ; CHECK: bb.1.b1: ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $r7, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r0 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.3, 1, killed $cpsr + ; CHECK: renamable $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.3, 1 [notequal], killed $cpsr ; CHECK: bb.2.b2: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: tBL 14, $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 - ; CHECK: t2B %bb.4, 14, $noreg + ; CHECK: tBL 14 [always], $noreg, @extfunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0 + ; CHECK: t2B %bb.4, 14 [always], $noreg ; CHECK: bb.3.b3: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14, $noreg :: (load 4 from `i32* undef`) - ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14, $noreg, $noreg + ; CHECK: renamable $r0 = t2LDRi12 undef renamable $r0, 0, 14 [always], $noreg :: (load 4 from `i32* undef`) + ; CHECK: renamable $r0 = t2ANDri killed renamable $r0, 256, 14 [always], $noreg, $noreg ; CHECK: bb.4.b5: ; CHECK: successors: %bb.5(0x30000000), %bb.6(0x50000000) ; CHECK: liveins: $r0 - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: t2Bcc %bb.6, 1, killed $cpsr + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: t2Bcc %bb.6, 1 [notequal], killed $cpsr ; CHECK: bb.5.b8: ; CHECK: liveins: $lr, $r7 - ; CHECK: tBX_RET 14, $noreg + ; CHECK: tBX_RET 14 [always], $noreg ; CHECK: bb.6.b7: ; CHECK: liveins: $lr, $r7 - ; CHECK: tTAILJMPdND @extfunc, 14, $noreg, implicit $sp, implicit $sp + ; CHECK: tTAILJMPdND @extfunc, 14 [always], $noreg, implicit $sp, implicit $sp bb.0 (%ir-block.0): successors: %bb.1(0x50000000), %bb.6(0x30000000) liveins: $lr, $r7 Index: llvm/test/CodeGen/ARM/constant-island-movwt.mir =================================================================== --- llvm/test/CodeGen/ARM/constant-island-movwt.mir +++ llvm/test/CodeGen/ARM/constant-island-movwt.mir @@ -384,7 +384,7 @@ bb.0.entry: liveins: $r0, $r4, $r5, $r6, $r7, $r11, $lr, $d8, $d9, $d10, $d11 - $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r11, killed $lr + $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r11, killed $lr frame-setup CFI_INSTRUCTION def_cfa_offset 24 frame-setup CFI_INSTRUCTION offset $lr, -4 frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -392,494 +392,494 @@ frame-setup CFI_INSTRUCTION offset $r6, -16 frame-setup CFI_INSTRUCTION offset $r5, -20 frame-setup CFI_INSTRUCTION offset $r4, -24 - $sp = frame-setup VSTMDDB_UPD $sp, 14, $noreg, killed $d8, killed $d9, killed $d10, killed $d11 + $sp = frame-setup VSTMDDB_UPD $sp, 14 [always], $noreg, killed $d8, killed $d9, killed $d10, killed $d11 frame-setup CFI_INSTRUCTION def_cfa_offset 56 frame-setup CFI_INSTRUCTION offset $d11, -32 frame-setup CFI_INSTRUCTION offset $d10, -40 frame-setup CFI_INSTRUCTION offset $d9, -48 frame-setup CFI_INSTRUCTION offset $d8, -56 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.18, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.18, 14, $noreg - renamable $r4, dead $cpsr = tMOVi8 100, 14, $noreg - renamable $r6 = t2ADDri renamable $r0, 520, 14, $noreg, $noreg - $d2 = VSETLNi32 undef $d2, killed $r1, 1, 14, $noreg, implicit-def $q1, implicit-def $s5 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.71, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.71, 14, $noreg - renamable $d25 = VSETLNi32 undef renamable $d25, killed renamable $r1, 0, 14, $noreg, implicit-def $q12 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.73, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.73, 14, $noreg - renamable $d26 = VSETLNi32 undef renamable $d26, killed renamable $r1, 0, 14, $noreg, implicit-def $q13 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.75, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.75, 14, $noreg - renamable $d27 = VSETLNi32 undef renamable $d27, killed renamable $r1, 0, 14, $noreg, implicit killed $q13, implicit-def $q13 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.19, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.19, 14, $noreg - renamable $s4 = VLDRS %const.0, 0, 14, $noreg, implicit killed $q1, implicit-def $q1 :: (load 4 from constant-pool) - renamable $d3 = VSETLNi32 undef renamable $d3, killed renamable $r1, 0, 14, $noreg, implicit killed $q1, implicit-def $q1 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.61, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.61, 14, $noreg - renamable $d20 = VSETLNi32 undef renamable $d20, killed renamable $r1, 0, 14, $noreg, implicit-def $q10 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.63, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.63, 14, $noreg - renamable $d21 = VSETLNi32 undef renamable $d21, killed renamable $r1, 0, 14, $noreg, implicit killed $q10, implicit-def $q10 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.122, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.122, 14, $noreg - $r12 = t2MOVi16 target-flags(arm-lo16) @.str.112, 14, $noreg - $r12 = t2MOVTi16 $r12, target-flags(arm-hi16) @.str.112, 14, $noreg - renamable $d16 = VSETLNi32 undef renamable $d16, killed renamable $r1, 0, 14, $noreg, implicit-def $q8 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.114, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.114, 14, $noreg - renamable $d18 = VSETLNi32 undef renamable $d18, renamable $r12, 0, 14, $noreg, implicit-def $q9 - renamable $d19 = VSETLNi32 undef renamable $d19, killed renamable $r1, 0, 14, $noreg, implicit killed $q9, implicit-def $q9 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.57, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.57, 14, $noreg - renamable $d28 = VSETLNi32 undef renamable $d28, killed renamable $r1, 0, 14, $noreg, implicit-def $q14 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.53, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.53, 14, $noreg - renamable $d22 = VSETLNi32 undef renamable $d22, killed renamable $r1, 0, 14, $noreg, implicit-def $q11 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.49, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.49, 14, $noreg - renamable $d30 = VSETLNi32 undef renamable $d30, killed renamable $r1, 0, 14, $noreg, implicit-def $q15 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.45, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.45, 14, $noreg - renamable $d0 = VSETLNi32 undef renamable $d0, killed renamable $r1, 0, 14, $noreg, implicit-def $q0 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.37, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.37, 14, $noreg - renamable $d8 = VSETLNi32 undef renamable $d8, killed renamable $r1, 0, 14, $noreg, implicit-def $q4 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.25, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.25, 14, $noreg - renamable $d4 = VSETLNi32 undef renamable $d4, killed renamable $r1, 0, 14, $noreg, implicit-def $q2 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.21, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.21, 14, $noreg - renamable $d6 = VSETLNi32 undef renamable $d6, killed renamable $r1, 0, 14, $noreg, implicit-def $q3 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.27, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.27, 14, $noreg - renamable $d5 = VSETLNi32 undef renamable $d5, killed renamable $r1, 0, 14, $noreg, implicit killed $q2, implicit-def $q2 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.23, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.23, 14, $noreg - renamable $d7 = VSETLNi32 undef renamable $d7, killed renamable $r1, 0, 14, $noreg, implicit killed $q3, implicit-def $q3 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.28, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.28, 14, $noreg - renamable $d5 = VSETLNi32 killed renamable $d5, killed renamable $r1, 1, 14, $noreg, implicit $q2, implicit-def $q2 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.24, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.24, 14, $noreg - renamable $d7 = VSETLNi32 killed renamable $d7, killed renamable $r1, 1, 14, $noreg, implicit $q3, implicit-def $q3 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.22, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.22, 14, $noreg - renamable $d6 = VSETLNi32 killed renamable $d6, killed renamable $r1, 1, 14, $noreg, implicit $q3, implicit-def $q3 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.26, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.26, 14, $noreg - renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r1, 1, 14, $noreg, implicit $q2, implicit-def $q2 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.29, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.29, 14, $noreg - renamable $d10 = VSETLNi32 undef renamable $d10, killed renamable $r1, 0, 14, $noreg, implicit-def $q5 - renamable $r1 = t2ADDri renamable $r0, 16, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q3, 14, $noreg :: (store 16 into %ir.1, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.39, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.39, 14, $noreg - renamable $d9 = VSETLNi32 undef renamable $d9, killed renamable $r1, 0, 14, $noreg, implicit killed $q4, implicit-def $q4 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.69, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.69, 14, $noreg - renamable $d24 = VSETLNi32 undef renamable $d24, killed renamable $r1, 0, 14, $noreg, implicit killed $q12, implicit-def $q12 - renamable $r1 = t2ADDri renamable $r0, 32, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q2, 14, $noreg :: (store 16 into %ir.2, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.31, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.31, 14, $noreg - renamable $d11 = VSETLNi32 undef renamable $d11, killed renamable $r1, 0, 14, $noreg, implicit killed $q5, implicit-def $q5 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.40, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.40, 14, $noreg - renamable $d9 = VSETLNi32 killed renamable $d9, killed renamable $r1, 1, 14, $noreg, implicit $q4, implicit-def $q4 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.32, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.32, 14, $noreg - renamable $d11 = VSETLNi32 killed renamable $d11, killed renamable $r1, 1, 14, $noreg, implicit $q5, implicit-def $q5 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.30, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.30, 14, $noreg - renamable $d10 = VSETLNi32 killed renamable $d10, killed renamable $r1, 1, 14, $noreg, implicit $q5, implicit-def $q5 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.38, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.38, 14, $noreg - renamable $d8 = VSETLNi32 killed renamable $d8, killed renamable $r1, 1, 14, $noreg, implicit $q4, implicit-def $q4 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.67, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.67, 14, $noreg - renamable $d5 = VSETLNi32 undef renamable $d5, killed renamable $r1, 0, 14, $noreg, implicit-def $q2 - renamable $r1 = t2ADDri renamable $r0, 48, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q5, 14, $noreg :: (store 16 into %ir.3, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.51, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.51, 14, $noreg - renamable $d31 = VSETLNi32 undef renamable $d31, killed renamable $r1, 0, 14, $noreg, implicit killed $q15, implicit-def $q15 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.43, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.43, 14, $noreg - renamable $d7 = VSETLNi32 undef renamable $d7, killed renamable $r1, 0, 14, $noreg, implicit-def $q3 - renamable $r1 = t2ADDri renamable $r0, 80, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q4, 14, $noreg :: (store 16 into %ir.5, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.47, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.47, 14, $noreg - renamable $d1 = VSETLNi32 undef renamable $d1, killed renamable $r1, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.52, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.52, 14, $noreg - renamable $d31 = VSETLNi32 killed renamable $d31, killed renamable $r1, 1, 14, $noreg, implicit $q15, implicit-def $q15 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.48, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.48, 14, $noreg - renamable $d1 = VSETLNi32 killed renamable $d1, killed renamable $r1, 1, 14, $noreg, implicit $q0, implicit-def $q0 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.46, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.46, 14, $noreg - renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r1, 1, 14, $noreg, implicit $q0, implicit-def $q0 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.50, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.50, 14, $noreg - renamable $d30 = VSETLNi32 killed renamable $d30, killed renamable $r1, 1, 14, $noreg, implicit $q15, implicit-def $q15 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.41, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.41, 14, $noreg - renamable $d6 = VSETLNi32 undef renamable $d6, killed renamable $r1, 0, 14, $noreg, implicit killed $q3, implicit-def $q3 - renamable $r1 = t2ADDri renamable $r0, 112, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q0, 14, $noreg :: (store 16 into %ir.7, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.59, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.59, 14, $noreg - renamable $d29 = VSETLNi32 undef renamable $d29, killed renamable $r1, 0, 14, $noreg, implicit killed $q14, implicit-def $q14 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.65, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.65, 14, $noreg - renamable $d4 = VSETLNi32 undef renamable $d4, killed renamable $r1, 0, 14, $noreg, implicit killed $q2, implicit-def $q2 - renamable $r1 = t2ADDri renamable $r0, 128, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q15, 14, $noreg :: (store 16 into %ir.8, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.55, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.55, 14, $noreg - renamable $d23 = VSETLNi32 undef renamable $d23, killed renamable $r1, 0, 14, $noreg, implicit killed $q11, implicit-def $q11 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.60, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.60, 14, $noreg - renamable $d29 = VSETLNi32 killed renamable $d29, killed renamable $r1, 1, 14, $noreg, implicit $q14, implicit-def $q14 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.56, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.56, 14, $noreg - renamable $d23 = VSETLNi32 killed renamable $d23, killed renamable $r1, 1, 14, $noreg, implicit $q11, implicit-def $q11 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.54, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.54, 14, $noreg - renamable $d22 = VSETLNi32 killed renamable $d22, killed renamable $r1, 1, 14, $noreg, implicit $q11, implicit-def $q11 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.58, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.58, 14, $noreg - renamable $d28 = VSETLNi32 killed renamable $d28, killed renamable $r1, 1, 14, $noreg, implicit $q14, implicit-def $q14 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.104, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.104, 14, $noreg - renamable $d31 = VSETLNi32 undef renamable $d31, killed renamable $r1, 0, 14, $noreg, implicit-def $q15 - renamable $r1 = t2ADDri renamable $r0, 144, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q11, 14, $noreg :: (store 16 into %ir.9, align 8) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.126, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.126, 14, $noreg - renamable $d23 = VSETLNi32 undef renamable $d23, killed renamable $r1, 0, 14, $noreg, implicit-def $q11 - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.98, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.98, 14, $noreg - renamable $d0 = VSETLNi32 undef renamable $d0, killed renamable $r1, 0, 14, $noreg, implicit-def $q0 - renamable $r1 = t2ADDri renamable $r0, 200, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q14, 14, $noreg :: (store 16 into %ir.11, align 8) - $lr = t2MOVi16 target-flags(arm-lo16) @.str.124, 14, $noreg - $lr = t2MOVTi16 $lr, target-flags(arm-hi16) @.str.124, 14, $noreg - $r2 = t2MOVi16 target-flags(arm-lo16) @.str.127, 14, $noreg - $r2 = t2MOVTi16 $r2, target-flags(arm-hi16) @.str.127, 14, $noreg - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.125, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.125, 14, $noreg - $r7 = t2MOVi16 target-flags(arm-lo16) @.str.115, 14, $noreg - $r7 = t2MOVTi16 $r7, target-flags(arm-hi16) @.str.115, 14, $noreg - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.113, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.113, 14, $noreg - renamable $d22 = VSETLNi32 undef renamable $d22, renamable $lr, 0, 14, $noreg, implicit killed $q11, implicit-def $q11 - renamable $d19 = VSETLNi32 killed renamable $d19, renamable $r7, 1, 14, $noreg, implicit $q9, implicit-def $q9 - renamable $d23 = VSETLNi32 killed renamable $d23, renamable $r2, 1, 14, $noreg, implicit $q11, implicit-def $q11 - renamable $d18 = VSETLNi32 killed renamable $d18, killed renamable $r3, 1, 14, $noreg, implicit $q9, implicit-def $q9 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.123, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.123, 14, $noreg - renamable $d16 = VSETLNi32 killed renamable $d16, killed renamable $r3, 1, 14, $noreg, implicit $q8, implicit-def $q8 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.64, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.64, 14, $noreg - renamable $d21 = VSETLNi32 killed renamable $d21, killed renamable $r3, 1, 14, $noreg, implicit $q10, implicit-def $q10 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.62, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.62, 14, $noreg - renamable $d22 = VSETLNi32 killed renamable $d22, killed renamable $r1, 1, 14, $noreg, implicit $q11, implicit-def $q11 - renamable $r1 = t2ADDri renamable $r0, 456, 14, $noreg, $noreg - renamable $d20 = VSETLNi32 killed renamable $d20, killed renamable $r3, 1, 14, $noreg, implicit $q10, implicit-def $q10 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.20, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.20, 14, $noreg - renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r3, 1, 14, $noreg, implicit $q1, implicit-def $q1 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.121, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.121, 14, $noreg - renamable $q14 = VDUP32q killed renamable $r3, 14, $noreg - renamable $r3 = t2ADDri renamable $r0, 216, 14, $noreg, $noreg - VST1q64 killed $r3, 0, killed $q10, 14, $noreg :: (store 16 into %ir.12, align 8) - $r3 = tMOVr $r0, 14, $noreg - renamable $r3 = VST1q32wb_register killed $r3, 0, killed $r4, killed $q1, 14, $noreg :: (store 16 into %ir.0, align 8) - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.120, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.120, 14, $noreg - renamable $q10 = VMOVv4i32 0, 14, $noreg - renamable $d28 = VSETLNi32 killed renamable $d28, killed renamable $r4, 0, 14, $noreg, implicit $q14, implicit-def $q14 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.76, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.76, 14, $noreg - renamable $d27 = VSETLNi32 killed renamable $d27, killed renamable $r4, 1, 14, $noreg, implicit $q13, implicit-def $q13 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.74, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.74, 14, $noreg - renamable $d17 = VDUP32d killed renamable $lr, 14, $noreg, implicit killed $q8, implicit-def $q8 - renamable $lr = t2ADDri renamable $r0, 788, 14, $noreg, $noreg - renamable $d26 = VSETLNi32 killed renamable $d26, killed renamable $r4, 1, 14, $noreg, implicit $q13, implicit-def $q13 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.72, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.72, 14, $noreg - renamable $d25 = VSETLNi32 killed renamable $d25, killed renamable $r4, 1, 14, $noreg, implicit $q12, implicit-def $q12 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.70, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.70, 14, $noreg - renamable $d24 = VSETLNi32 killed renamable $d24, killed renamable $r4, 1, 14, $noreg, implicit $q12, implicit-def $q12 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.68, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.68, 14, $noreg - renamable $d5 = VSETLNi32 killed renamable $d5, killed renamable $r4, 1, 14, $noreg, implicit $q2, implicit-def $q2 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.44, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.44, 14, $noreg - renamable $d7 = VSETLNi32 killed renamable $d7, killed renamable $r4, 1, 14, $noreg, implicit $q3, implicit-def $q3 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.42, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.42, 14, $noreg - renamable $d6 = VSETLNi32 killed renamable $d6, killed renamable $r4, 1, 14, $noreg, implicit $q3, implicit-def $q3 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.66, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.66, 14, $noreg - renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r4, 1, 14, $noreg, implicit $q2, implicit-def $q2 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.88, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.88, 14, $noreg - renamable $d8 = VSETLNi32 undef renamable $d8, killed renamable $r4, 0, 14, $noreg, implicit-def $q4 - renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg - tSTRi renamable $r4, killed renamable $r3, 0, 14, $noreg :: (store 4 into %ir.4 + 36) - $r3 = tMOVr $r0, 14, $noreg - t2STRDi8 $r4, $r4, $r0, 192, 14, $noreg - early-clobber renamable $r3 = t2STR_PRE renamable $r4, killed renamable $r3, 96, 14, $noreg :: (store 4 into %ir.4 + 32) - VST1q64 killed $r3, 0, killed $q3, 14, $noreg :: (store 16 into %ir.6, align 8) - renamable $r3 = t2ADDri renamable $r0, 64, 14, $noreg, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.81, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.81, 14, $noreg - VST1q32 killed $r3, 0, $q10, 14, $noreg :: (store 16 into %ir.4, align 4) - renamable $r3 = t2ADDri renamable $r0, 176, 14, $noreg, $noreg - VST1q32 killed $r3, 0, $q10, 14, $noreg :: (store 16 into %ir.10 + 16, align 4) - renamable $r3 = t2ADDri renamable $r0, 160, 14, $noreg, $noreg - renamable $q1 = VDUP32q killed renamable $r5, 14, $noreg - renamable $r5 = t2ADDri renamable $r0, 248, 14, $noreg, $noreg - VST1q32 killed $r3, 0, $q10, 14, $noreg :: (store 16 into %ir.10, align 4) - renamable $r3 = t2ADDri renamable $r0, 232, 14, $noreg, $noreg - VST1q64 killed $r3, 0, killed $q2, 14, $noreg :: (store 16 into %ir.13, align 8) - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.82, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.82, 14, $noreg - VST1q64 killed $r5, 0, killed $q12, 14, $noreg :: (store 16 into %ir.14, align 8) - renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r3, 1, 14, $noreg, implicit $q1, implicit-def $q1 - renamable $r3 = t2ADDri renamable $r0, 264, 14, $noreg, $noreg - VST1q64 killed $r3, 0, killed $q13, 14, $noreg :: (store 16 into %ir.15, align 8) - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.91, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.91, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.90, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.90, 14, $noreg - renamable $d9 = VSETLNi32 undef renamable $d9, killed renamable $r5, 0, 14, $noreg, implicit killed $q4, implicit-def $q4 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.118, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14, $noreg - renamable $q12 = VDUP32q killed renamable $r5, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14, $noreg - renamable $q13 = VDUP32q killed renamable $r5, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.92, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.92, 14, $noreg - t2STRDi8 killed $r4, $r4, $r0, 312, 14, $noreg - renamable $r4 = t2ADDri renamable $r0, 296, 14, $noreg, $noreg - renamable $d5 = VSETLNi32 undef renamable $d5, killed renamable $r5, 0, 14, $noreg, implicit-def $q2 - renamable $r5 = t2ADDri renamable $r0, 280, 14, $noreg, $noreg - VST1q32 $r4, 0, $q10, 14, $noreg :: (store 16 into %ir.16 + 16, align 4) - VST1q32 killed $r5, 0, $q10, 14, $noreg :: (store 16 into %ir.16, align 4) - VST1q64 killed $r4, 0, killed $q1, 14, $noreg :: (store 16 into %ir.17, align 8) - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.83, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.83, 14, $noreg - renamable $d9 = VSETLNi32 killed renamable $d9, renamable $r3, 1, 14, $noreg, implicit $q4, implicit-def $q4 - renamable $r4 = t2ADDri renamable $r0, 312, 14, $noreg, $noreg - renamable $d26 = VSETLNi32 killed renamable $d26, killed renamable $r5, 0, 14, $noreg, implicit $q13, implicit-def $q13 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.89, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.89, 14, $noreg - renamable $d8 = VSETLNi32 killed renamable $d8, killed renamable $r5, 1, 14, $noreg, implicit $q4, implicit-def $q4 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.106, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.106, 14, $noreg - VST1q64 killed $r4, 0, killed $q13, 14, $noreg :: (store 16 into %ir.18, align 8) - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.119, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.119, 14, $noreg - renamable $q1 = VDUP32q killed renamable $r5, 14, $noreg - renamable $r5 = t2ADDri renamable $r0, 436, 14, $noreg, $noreg - renamable $d25 = VSETLNi32 killed renamable $d25, killed renamable $r4, 1, 14, $noreg, implicit $q12, implicit-def $q12 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.116, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.116, 14, $noreg - renamable $d27 = VSETLNi32 undef renamable $d27, killed renamable $r4, 0, 14, $noreg, implicit-def $q13 - renamable $r4 = t2ADDri renamable $r0, 344, 14, $noreg, $noreg - VST1q64 killed $r4, 0, killed $q4, 14, $noreg :: (store 16 into %ir.19, align 8) - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.107, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.107, 14, $noreg - renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r4, 1, 14, $noreg, implicit $q1, implicit-def $q1 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.105, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.105, 14, $noreg - renamable $d31 = VSETLNi32 killed renamable $d31, killed renamable $r4, 1, 14, $noreg, implicit $q15, implicit-def $q15 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.99, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.99, 14, $noreg - renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r4, 1, 14, $noreg, implicit $q0, implicit-def $q0 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.93, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.93, 14, $noreg - renamable $d5 = VSETLNi32 killed renamable $d5, killed renamable $r4, 1, 14, $noreg, implicit $q2, implicit-def $q2 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.117, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.117, 14, $noreg - renamable $d27 = VSETLNi32 killed renamable $d27, killed renamable $r4, 1, 14, $noreg, implicit $q13, implicit-def $q13 - renamable $r4 = t2ADDri renamable $r0, 392, 14, $noreg, $noreg - renamable $d4 = VDUP32d killed renamable $r3, 14, $noreg, implicit killed $q2, implicit-def $q2 - renamable $r3 = t2ADDri renamable $r0, 360, 14, $noreg, $noreg - renamable $d26 = VDUP32d killed renamable $r7, 14, $noreg, implicit killed $q13, implicit-def $q13 - renamable $r7 = t2ADDri renamable $r0, 504, 14, $noreg, $noreg - VST1q64 killed $r3, 0, killed $q2, 14, $noreg :: (store 16 into %ir.20, align 8) - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.97, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.97, 14, $noreg - renamable $q2 = VDUP32q killed renamable $r3, 14, $noreg - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.96, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.96, 14, $noreg - renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r3, 0, 14, $noreg, implicit $q2, implicit-def $q2 - renamable $r3 = t2ADDri renamable $r0, 388, 14, $noreg, $noreg - VST1q32 killed $r3, 0, $q10, 14, $noreg :: (store 16 into %ir.21 + 12, align 4) - renamable $r3 = t2ADDri renamable $r0, 376, 14, $noreg, $noreg - VST1q32 killed $r3, 0, $q10, 14, $noreg :: (store 16 into %ir.21, align 4) - renamable $r3 = t2ADDri renamable $r0, 584, 14, $noreg, $noreg - VST1q64 killed $r4, 0, killed $q2, 14, $noreg :: (store 16 into %ir.22, align 8) - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.100, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.100, 14, $noreg - renamable $d1 = VDUP32d killed renamable $r4, 14, $noreg, implicit killed $q0, implicit-def $q0 - renamable $r4 = t2ADDri renamable $r0, 408, 14, $noreg, $noreg - VST1q64 killed $r4, 0, killed $q0, 14, $noreg :: (store 16 into %ir.23, align 8) - renamable $r4 = t2ADDri renamable $r0, 440, 14, $noreg, $noreg - VST1q32 killed $r5, 0, $q10, 14, $noreg :: (store 16 into %ir.24 + 12, align 4) - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.103, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.103, 14, $noreg - renamable $d30 = VDUP32d killed renamable $r5, 14, $noreg, implicit killed $q15, implicit-def $q15 - renamable $r5 = t2ADDri renamable $r0, 424, 14, $noreg, $noreg - VST1q32 killed $r5, 0, $q10, 14, $noreg :: (store 16 into %ir.24, align 4) - VST1q64 killed $r4, 0, killed $q15, 14, $noreg :: (store 16 into %ir.25, align 8) - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.111, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.111, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.110, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.110, 14, $noreg - renamable $d30 = VSETLNi32 undef renamable $d30, killed renamable $r5, 0, 14, $noreg, implicit-def $q15 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.109, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.109, 14, $noreg - renamable $q0 = VDUP32q killed renamable $r5, 14, $noreg - renamable $r5 = t2ADDri renamable $r0, 488, 14, $noreg, $noreg - renamable $d30 = VSETLNi32 killed renamable $d30, killed renamable $r4, 1, 14, $noreg, implicit $q15, implicit-def $q15 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.108, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.108, 14, $noreg - renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r4, 0, 14, $noreg, implicit $q0, implicit-def $q0 - renamable $r4 = t2ADDri renamable $r0, 568, 14, $noreg, $noreg - renamable $d31 = VDUP32d killed renamable $r12, 14, $noreg, implicit killed $q15, implicit-def $q15 - VST1q64 killed $r1, 0, killed $q1, 14, $noreg :: (store 16 into %ir.26, align 8) - renamable $r1 = t2ADDri renamable $r0, 472, 14, $noreg, $noreg - VST1q64 killed $r1, 0, killed $q0, 14, $noreg :: (store 16 into %ir.27, align 8) - renamable $r1 = t2ADDri renamable $r0, 552, 14, $noreg, $noreg - VST1q64 killed $r5, 0, killed $q15, 14, $noreg :: (store 16 into %ir.28, align 8) - renamable $r5 = t2ADDri renamable $r0, 536, 14, $noreg, $noreg - VST1q64 killed $r7, 0, killed $q9, 14, $noreg :: (store 16 into %ir.29, align 8) - renamable $r7 = t2ADDri renamable $r0, 660, 14, $noreg, $noreg - VST1q64 killed $r6, 0, killed $q13, 14, $noreg :: (store 16 into %ir.30, align 8) - VST1q64 killed $r5, 0, killed $q12, 14, $noreg :: (store 16 into %ir.31, align 8) - VST1q64 killed $r1, 0, killed $q14, 14, $noreg :: (store 16 into %ir.32, align 8) - renamable $r1 = t2ADDri renamable $r0, 608, 14, $noreg, $noreg - VST1q64 killed $r4, 0, killed $q8, 14, $noreg :: (store 16 into %ir.33, align 8) - VST1q64 killed $r3, 0, killed $q11, 14, $noreg :: (store 16 into %ir.34, align 8) - t2STRDi8 killed $r2, $r2, $r0, 600, 14, $noreg - VST1q32 killed $r1, 0, $q10, 14, $noreg :: (store 16 into %ir.35, align 4) - $r12 = t2MOVi16 target-flags(arm-lo16) @.str.139, 14, $noreg - $r12 = t2MOVTi16 $r12, target-flags(arm-hi16) @.str.139, 14, $noreg - $r2 = t2MOVi16 target-flags(arm-lo16) @.str.151, 14, $noreg - $r2 = t2MOVTi16 $r2, target-flags(arm-hi16) @.str.151, 14, $noreg - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.134, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.134, 14, $noreg - renamable $r1 = t2ADDri renamable $r0, 620, 14, $noreg, $noreg - renamable $d24 = VSETLNi32 undef renamable $d24, killed renamable $r3, 0, 14, $noreg, implicit-def $q12 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.140, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.140, 14, $noreg - renamable $d23 = VSETLNi32 undef renamable $d23, killed renamable $r3, 0, 14, $noreg, implicit-def $q11 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.146, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.146, 14, $noreg - renamable $d18 = VSETLNi32 undef renamable $d18, killed renamable $r3, 0, 14, $noreg, implicit-def $q9 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.152, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.152, 14, $noreg - renamable $d17 = VSETLNi32 undef renamable $d17, killed renamable $r3, 0, 14, $noreg, implicit-def $q8 - $r3 = t2MOVi16 target-flags(arm-lo16) @.str.136, 14, $noreg - $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.136, 14, $noreg - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.138, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.138, 14, $noreg - renamable $d28 = VSETLNi32 undef renamable $d28, renamable $r3, 0, 14, $noreg, implicit-def $q14 - renamable $d29 = VSETLNi32 undef renamable $d29, killed renamable $r4, 0, 14, $noreg, implicit killed $q14, implicit-def $q14 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.148, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.148, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.150, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.150, 14, $noreg - renamable $d26 = VSETLNi32 undef renamable $d26, renamable $r4, 0, 14, $noreg, implicit-def $q13 - renamable $d29 = VSETLNi32 killed renamable $d29, renamable $r12, 1, 14, $noreg, implicit $q14, implicit-def $q14 - renamable $d27 = VSETLNi32 undef renamable $d27, killed renamable $r5, 0, 14, $noreg, implicit killed $q13, implicit-def $q13 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.130, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.130, 14, $noreg - renamable $q1 = VDUP32q killed renamable $r5, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.142, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.142, 14, $noreg - renamable $d27 = VSETLNi32 killed renamable $d27, renamable $r2, 1, 14, $noreg, implicit $q13, implicit-def $q13 - renamable $q15 = VDUP32q killed renamable $r5, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.149, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.149, 14, $noreg - renamable $d26 = VSETLNi32 killed renamable $d26, killed renamable $r5, 1, 14, $noreg, implicit $q13, implicit-def $q13 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.145, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.145, 14, $noreg - renamable $q0 = VDUP32q killed renamable $r5, 14, $noreg - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.137, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.137, 14, $noreg - renamable $d28 = VSETLNi32 killed renamable $d28, killed renamable $r5, 1, 14, $noreg, implicit $q14, implicit-def $q14 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.153, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.153, 14, $noreg - renamable $d17 = VSETLNi32 killed renamable $d17, killed renamable $r5, 1, 14, $noreg, implicit $q8, implicit-def $q8 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.147, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.147, 14, $noreg - renamable $d18 = VSETLNi32 killed renamable $d18, killed renamable $r5, 1, 14, $noreg, implicit $q9, implicit-def $q9 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.141, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.141, 14, $noreg - renamable $d23 = VSETLNi32 killed renamable $d23, killed renamable $r5, 1, 14, $noreg, implicit $q11, implicit-def $q11 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.135, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.135, 14, $noreg - renamable $d24 = VSETLNi32 killed renamable $d24, killed renamable $r5, 1, 14, $noreg, implicit $q12, implicit-def $q12 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.144, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.144, 14, $noreg - renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r5, 0, 14, $noreg, implicit $q0, implicit-def $q0 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.143, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.143, 14, $noreg - renamable $d31 = VSETLNi32 killed renamable $d31, killed renamable $r5, 1, 14, $noreg, implicit $q15, implicit-def $q15 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.131, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.131, 14, $noreg - renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r5, 1, 14, $noreg, implicit $q1, implicit-def $q1 - $r5 = t2MOVi16 target-flags(arm-lo16) @.str.133, 14, $noreg - $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.133, 14, $noreg - renamable $q2 = VDUP32q killed renamable $r5, 14, $noreg - renamable $r5 = t2ADDri renamable $r0, 756, 14, $noreg, $noreg - VST1q32 killed $r1, 0, killed $q10, 14, $noreg :: (store 16 into %ir.35 + 12, align 4) - $r1 = t2MOVi16 target-flags(arm-lo16) @.str.132, 14, $noreg - $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.132, 14, $noreg - renamable $d19 = VDUP32d killed renamable $r4, 14, $noreg, implicit killed $q9, implicit-def $q9 - $r4 = t2MOVi16 target-flags(arm-lo16) @.str.128, 14, $noreg - $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.128, 14, $noreg - renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r1, 0, 14, $noreg, implicit $q2, implicit-def $q2 - $r6 = t2MOVi16 target-flags(arm-lo16) @.str.129, 14, $noreg - $r6 = t2MOVTi16 $r6, target-flags(arm-hi16) @.str.129, 14, $noreg - renamable $r1 = t2ADDri renamable $r0, 772, 14, $noreg, $noreg - renamable $d16 = VDUP32d killed renamable $r2, 14, $noreg, implicit killed $q8, implicit-def $q8 - renamable $r2 = t2ADDri renamable $r0, 740, 14, $noreg, $noreg - renamable $d22 = VDUP32d killed renamable $r12, 14, $noreg, implicit killed $q11, implicit-def $q11 - renamable $d25 = VDUP32d killed renamable $r3, 14, $noreg, implicit killed $q12, implicit-def $q12 - t2STRDi8 killed $r4, killed $r6, $r0, 636, 14, $noreg - renamable $r4 = t2ADDri renamable $r0, 644, 14, $noreg, $noreg - renamable $r6 = t2ADDri renamable $r0, 692, 14, $noreg, $noreg - VST1q64 killed $r4, 0, killed $q1, 14, $noreg :: (store 16 into %ir.36, align 8) - renamable $r4 = t2ADDri renamable $r0, 724, 14, $noreg, $noreg - VST1q64 killed $r7, 0, killed $q2, 14, $noreg :: (store 16 into %ir.37, align 8) - renamable $r7 = t2ADDri renamable $r0, 708, 14, $noreg, $noreg - renamable $r0 = t2ADDri killed renamable $r0, 676, 14, $noreg, $noreg - VST1q64 killed $r0, 0, killed $q12, 14, $noreg :: (store 16 into %ir.38, align 8) - VST1q64 killed $r6, 0, killed $q14, 14, $noreg :: (store 16 into %ir.39, align 8) - VST1q64 killed $r7, 0, killed $q11, 14, $noreg :: (store 16 into %ir.40, align 8) - VST1q64 killed $r4, 0, killed $q15, 14, $noreg :: (store 16 into %ir.41, align 8) - VST1q64 killed $r2, 0, killed $q0, 14, $noreg :: (store 16 into %ir.42, align 8) - VST1q64 killed $r5, 0, killed $q9, 14, $noreg :: (store 16 into %ir.43, align 8) - VST1q64 killed $r1, 0, killed $q13, 14, $noreg :: (store 16 into %ir.44, align 8) - VST1q64 killed $lr, 0, killed $q8, 14, $noreg :: (store 16 into %ir.45, align 8) - $sp = VLDMDIA_UPD $sp, 14, $noreg, def $d8, def $d9, def $d10, def $d11 - $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r11, def $pc + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.18, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.18, 14 [always], $noreg + renamable $r4, dead $cpsr = tMOVi8 100, 14 [always], $noreg + renamable $r6 = t2ADDri renamable $r0, 520, 14 [always], $noreg, $noreg + $d2 = VSETLNi32 undef $d2, killed $r1, 1, 14 [always], $noreg, implicit-def $q1, implicit-def $s5 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.71, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.71, 14 [always], $noreg + renamable $d25 = VSETLNi32 undef renamable $d25, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q12 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.73, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.73, 14 [always], $noreg + renamable $d26 = VSETLNi32 undef renamable $d26, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q13 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.75, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.75, 14 [always], $noreg + renamable $d27 = VSETLNi32 undef renamable $d27, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q13, implicit-def $q13 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.19, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.19, 14 [always], $noreg + renamable $s4 = VLDRS %const.0, 0, 14 [always], $noreg, implicit killed $q1, implicit-def $q1 :: (load 4 from constant-pool) + renamable $d3 = VSETLNi32 undef renamable $d3, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q1, implicit-def $q1 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.61, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.61, 14 [always], $noreg + renamable $d20 = VSETLNi32 undef renamable $d20, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q10 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.63, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.63, 14 [always], $noreg + renamable $d21 = VSETLNi32 undef renamable $d21, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q10, implicit-def $q10 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.122, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.122, 14 [always], $noreg + $r12 = t2MOVi16 target-flags(arm-lo16) @.str.112, 14 [always], $noreg + $r12 = t2MOVTi16 $r12, target-flags(arm-hi16) @.str.112, 14 [always], $noreg + renamable $d16 = VSETLNi32 undef renamable $d16, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q8 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.114, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.114, 14 [always], $noreg + renamable $d18 = VSETLNi32 undef renamable $d18, renamable $r12, 0, 14 [always], $noreg, implicit-def $q9 + renamable $d19 = VSETLNi32 undef renamable $d19, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q9, implicit-def $q9 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.57, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.57, 14 [always], $noreg + renamable $d28 = VSETLNi32 undef renamable $d28, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q14 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.53, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.53, 14 [always], $noreg + renamable $d22 = VSETLNi32 undef renamable $d22, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q11 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.49, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.49, 14 [always], $noreg + renamable $d30 = VSETLNi32 undef renamable $d30, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q15 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.45, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.45, 14 [always], $noreg + renamable $d0 = VSETLNi32 undef renamable $d0, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q0 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.37, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.37, 14 [always], $noreg + renamable $d8 = VSETLNi32 undef renamable $d8, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q4 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.25, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.25, 14 [always], $noreg + renamable $d4 = VSETLNi32 undef renamable $d4, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q2 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.21, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.21, 14 [always], $noreg + renamable $d6 = VSETLNi32 undef renamable $d6, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q3 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.27, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.27, 14 [always], $noreg + renamable $d5 = VSETLNi32 undef renamable $d5, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q2, implicit-def $q2 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.23, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.23, 14 [always], $noreg + renamable $d7 = VSETLNi32 undef renamable $d7, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q3, implicit-def $q3 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.28, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.28, 14 [always], $noreg + renamable $d5 = VSETLNi32 killed renamable $d5, killed renamable $r1, 1, 14 [always], $noreg, implicit $q2, implicit-def $q2 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.24, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.24, 14 [always], $noreg + renamable $d7 = VSETLNi32 killed renamable $d7, killed renamable $r1, 1, 14 [always], $noreg, implicit $q3, implicit-def $q3 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.22, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.22, 14 [always], $noreg + renamable $d6 = VSETLNi32 killed renamable $d6, killed renamable $r1, 1, 14 [always], $noreg, implicit $q3, implicit-def $q3 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.26, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.26, 14 [always], $noreg + renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r1, 1, 14 [always], $noreg, implicit $q2, implicit-def $q2 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.29, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.29, 14 [always], $noreg + renamable $d10 = VSETLNi32 undef renamable $d10, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q5 + renamable $r1 = t2ADDri renamable $r0, 16, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q3, 14 [always], $noreg :: (store 16 into %ir.1, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.39, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.39, 14 [always], $noreg + renamable $d9 = VSETLNi32 undef renamable $d9, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q4, implicit-def $q4 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.69, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.69, 14 [always], $noreg + renamable $d24 = VSETLNi32 undef renamable $d24, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q12, implicit-def $q12 + renamable $r1 = t2ADDri renamable $r0, 32, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q2, 14 [always], $noreg :: (store 16 into %ir.2, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.31, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.31, 14 [always], $noreg + renamable $d11 = VSETLNi32 undef renamable $d11, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q5, implicit-def $q5 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.40, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.40, 14 [always], $noreg + renamable $d9 = VSETLNi32 killed renamable $d9, killed renamable $r1, 1, 14 [always], $noreg, implicit $q4, implicit-def $q4 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.32, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.32, 14 [always], $noreg + renamable $d11 = VSETLNi32 killed renamable $d11, killed renamable $r1, 1, 14 [always], $noreg, implicit $q5, implicit-def $q5 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.30, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.30, 14 [always], $noreg + renamable $d10 = VSETLNi32 killed renamable $d10, killed renamable $r1, 1, 14 [always], $noreg, implicit $q5, implicit-def $q5 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.38, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.38, 14 [always], $noreg + renamable $d8 = VSETLNi32 killed renamable $d8, killed renamable $r1, 1, 14 [always], $noreg, implicit $q4, implicit-def $q4 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.67, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.67, 14 [always], $noreg + renamable $d5 = VSETLNi32 undef renamable $d5, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q2 + renamable $r1 = t2ADDri renamable $r0, 48, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q5, 14 [always], $noreg :: (store 16 into %ir.3, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.51, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.51, 14 [always], $noreg + renamable $d31 = VSETLNi32 undef renamable $d31, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q15, implicit-def $q15 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.43, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.43, 14 [always], $noreg + renamable $d7 = VSETLNi32 undef renamable $d7, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q3 + renamable $r1 = t2ADDri renamable $r0, 80, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q4, 14 [always], $noreg :: (store 16 into %ir.5, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.47, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.47, 14 [always], $noreg + renamable $d1 = VSETLNi32 undef renamable $d1, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q0, implicit-def $q0 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.52, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.52, 14 [always], $noreg + renamable $d31 = VSETLNi32 killed renamable $d31, killed renamable $r1, 1, 14 [always], $noreg, implicit $q15, implicit-def $q15 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.48, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.48, 14 [always], $noreg + renamable $d1 = VSETLNi32 killed renamable $d1, killed renamable $r1, 1, 14 [always], $noreg, implicit $q0, implicit-def $q0 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.46, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.46, 14 [always], $noreg + renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r1, 1, 14 [always], $noreg, implicit $q0, implicit-def $q0 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.50, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.50, 14 [always], $noreg + renamable $d30 = VSETLNi32 killed renamable $d30, killed renamable $r1, 1, 14 [always], $noreg, implicit $q15, implicit-def $q15 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.41, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.41, 14 [always], $noreg + renamable $d6 = VSETLNi32 undef renamable $d6, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q3, implicit-def $q3 + renamable $r1 = t2ADDri renamable $r0, 112, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q0, 14 [always], $noreg :: (store 16 into %ir.7, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.59, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.59, 14 [always], $noreg + renamable $d29 = VSETLNi32 undef renamable $d29, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q14, implicit-def $q14 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.65, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.65, 14 [always], $noreg + renamable $d4 = VSETLNi32 undef renamable $d4, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q2, implicit-def $q2 + renamable $r1 = t2ADDri renamable $r0, 128, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q15, 14 [always], $noreg :: (store 16 into %ir.8, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.55, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.55, 14 [always], $noreg + renamable $d23 = VSETLNi32 undef renamable $d23, killed renamable $r1, 0, 14 [always], $noreg, implicit killed $q11, implicit-def $q11 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.60, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.60, 14 [always], $noreg + renamable $d29 = VSETLNi32 killed renamable $d29, killed renamable $r1, 1, 14 [always], $noreg, implicit $q14, implicit-def $q14 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.56, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.56, 14 [always], $noreg + renamable $d23 = VSETLNi32 killed renamable $d23, killed renamable $r1, 1, 14 [always], $noreg, implicit $q11, implicit-def $q11 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.54, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.54, 14 [always], $noreg + renamable $d22 = VSETLNi32 killed renamable $d22, killed renamable $r1, 1, 14 [always], $noreg, implicit $q11, implicit-def $q11 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.58, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.58, 14 [always], $noreg + renamable $d28 = VSETLNi32 killed renamable $d28, killed renamable $r1, 1, 14 [always], $noreg, implicit $q14, implicit-def $q14 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.104, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.104, 14 [always], $noreg + renamable $d31 = VSETLNi32 undef renamable $d31, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q15 + renamable $r1 = t2ADDri renamable $r0, 144, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q11, 14 [always], $noreg :: (store 16 into %ir.9, align 8) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.126, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.126, 14 [always], $noreg + renamable $d23 = VSETLNi32 undef renamable $d23, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q11 + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.98, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.98, 14 [always], $noreg + renamable $d0 = VSETLNi32 undef renamable $d0, killed renamable $r1, 0, 14 [always], $noreg, implicit-def $q0 + renamable $r1 = t2ADDri renamable $r0, 200, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q14, 14 [always], $noreg :: (store 16 into %ir.11, align 8) + $lr = t2MOVi16 target-flags(arm-lo16) @.str.124, 14 [always], $noreg + $lr = t2MOVTi16 $lr, target-flags(arm-hi16) @.str.124, 14 [always], $noreg + $r2 = t2MOVi16 target-flags(arm-lo16) @.str.127, 14 [always], $noreg + $r2 = t2MOVTi16 $r2, target-flags(arm-hi16) @.str.127, 14 [always], $noreg + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.125, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.125, 14 [always], $noreg + $r7 = t2MOVi16 target-flags(arm-lo16) @.str.115, 14 [always], $noreg + $r7 = t2MOVTi16 $r7, target-flags(arm-hi16) @.str.115, 14 [always], $noreg + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.113, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.113, 14 [always], $noreg + renamable $d22 = VSETLNi32 undef renamable $d22, renamable $lr, 0, 14 [always], $noreg, implicit killed $q11, implicit-def $q11 + renamable $d19 = VSETLNi32 killed renamable $d19, renamable $r7, 1, 14 [always], $noreg, implicit $q9, implicit-def $q9 + renamable $d23 = VSETLNi32 killed renamable $d23, renamable $r2, 1, 14 [always], $noreg, implicit $q11, implicit-def $q11 + renamable $d18 = VSETLNi32 killed renamable $d18, killed renamable $r3, 1, 14 [always], $noreg, implicit $q9, implicit-def $q9 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.123, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.123, 14 [always], $noreg + renamable $d16 = VSETLNi32 killed renamable $d16, killed renamable $r3, 1, 14 [always], $noreg, implicit $q8, implicit-def $q8 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.64, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.64, 14 [always], $noreg + renamable $d21 = VSETLNi32 killed renamable $d21, killed renamable $r3, 1, 14 [always], $noreg, implicit $q10, implicit-def $q10 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.62, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.62, 14 [always], $noreg + renamable $d22 = VSETLNi32 killed renamable $d22, killed renamable $r1, 1, 14 [always], $noreg, implicit $q11, implicit-def $q11 + renamable $r1 = t2ADDri renamable $r0, 456, 14 [always], $noreg, $noreg + renamable $d20 = VSETLNi32 killed renamable $d20, killed renamable $r3, 1, 14 [always], $noreg, implicit $q10, implicit-def $q10 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.20, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.20, 14 [always], $noreg + renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r3, 1, 14 [always], $noreg, implicit $q1, implicit-def $q1 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.121, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.121, 14 [always], $noreg + renamable $q14 = VDUP32q killed renamable $r3, 14 [always], $noreg + renamable $r3 = t2ADDri renamable $r0, 216, 14 [always], $noreg, $noreg + VST1q64 killed $r3, 0, killed $q10, 14 [always], $noreg :: (store 16 into %ir.12, align 8) + $r3 = tMOVr $r0, 14 [always], $noreg + renamable $r3 = VST1q32wb_register killed $r3, 0, killed $r4, killed $q1, 14 [always], $noreg :: (store 16 into %ir.0, align 8) + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.120, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.120, 14 [always], $noreg + renamable $q10 = VMOVv4i32 0, 14 [always], $noreg + renamable $d28 = VSETLNi32 killed renamable $d28, killed renamable $r4, 0, 14 [always], $noreg, implicit $q14, implicit-def $q14 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.76, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.76, 14 [always], $noreg + renamable $d27 = VSETLNi32 killed renamable $d27, killed renamable $r4, 1, 14 [always], $noreg, implicit $q13, implicit-def $q13 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.74, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.74, 14 [always], $noreg + renamable $d17 = VDUP32d killed renamable $lr, 14 [always], $noreg, implicit killed $q8, implicit-def $q8 + renamable $lr = t2ADDri renamable $r0, 788, 14 [always], $noreg, $noreg + renamable $d26 = VSETLNi32 killed renamable $d26, killed renamable $r4, 1, 14 [always], $noreg, implicit $q13, implicit-def $q13 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.72, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.72, 14 [always], $noreg + renamable $d25 = VSETLNi32 killed renamable $d25, killed renamable $r4, 1, 14 [always], $noreg, implicit $q12, implicit-def $q12 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.70, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.70, 14 [always], $noreg + renamable $d24 = VSETLNi32 killed renamable $d24, killed renamable $r4, 1, 14 [always], $noreg, implicit $q12, implicit-def $q12 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.68, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.68, 14 [always], $noreg + renamable $d5 = VSETLNi32 killed renamable $d5, killed renamable $r4, 1, 14 [always], $noreg, implicit $q2, implicit-def $q2 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.44, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.44, 14 [always], $noreg + renamable $d7 = VSETLNi32 killed renamable $d7, killed renamable $r4, 1, 14 [always], $noreg, implicit $q3, implicit-def $q3 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.42, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.42, 14 [always], $noreg + renamable $d6 = VSETLNi32 killed renamable $d6, killed renamable $r4, 1, 14 [always], $noreg, implicit $q3, implicit-def $q3 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.66, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.66, 14 [always], $noreg + renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r4, 1, 14 [always], $noreg, implicit $q2, implicit-def $q2 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.88, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.88, 14 [always], $noreg + renamable $d8 = VSETLNi32 undef renamable $d8, killed renamable $r4, 0, 14 [always], $noreg, implicit-def $q4 + renamable $r4, dead $cpsr = tMOVi8 0, 14 [always], $noreg + tSTRi renamable $r4, killed renamable $r3, 0, 14 [always], $noreg :: (store 4 into %ir.4 + 36) + $r3 = tMOVr $r0, 14 [always], $noreg + t2STRDi8 $r4, $r4, $r0, 192, 14 [always], $noreg + early-clobber renamable $r3 = t2STR_PRE renamable $r4, killed renamable $r3, 96, 14 [always], $noreg :: (store 4 into %ir.4 + 32) + VST1q64 killed $r3, 0, killed $q3, 14 [always], $noreg :: (store 16 into %ir.6, align 8) + renamable $r3 = t2ADDri renamable $r0, 64, 14 [always], $noreg, $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.81, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.81, 14 [always], $noreg + VST1q32 killed $r3, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.4, align 4) + renamable $r3 = t2ADDri renamable $r0, 176, 14 [always], $noreg, $noreg + VST1q32 killed $r3, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.10 + 16, align 4) + renamable $r3 = t2ADDri renamable $r0, 160, 14 [always], $noreg, $noreg + renamable $q1 = VDUP32q killed renamable $r5, 14 [always], $noreg + renamable $r5 = t2ADDri renamable $r0, 248, 14 [always], $noreg, $noreg + VST1q32 killed $r3, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.10, align 4) + renamable $r3 = t2ADDri renamable $r0, 232, 14 [always], $noreg, $noreg + VST1q64 killed $r3, 0, killed $q2, 14 [always], $noreg :: (store 16 into %ir.13, align 8) + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.82, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.82, 14 [always], $noreg + VST1q64 killed $r5, 0, killed $q12, 14 [always], $noreg :: (store 16 into %ir.14, align 8) + renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r3, 1, 14 [always], $noreg, implicit $q1, implicit-def $q1 + renamable $r3 = t2ADDri renamable $r0, 264, 14 [always], $noreg, $noreg + VST1q64 killed $r3, 0, killed $q13, 14 [always], $noreg :: (store 16 into %ir.15, align 8) + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.91, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.91, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.90, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.90, 14 [always], $noreg + renamable $d9 = VSETLNi32 undef renamable $d9, killed renamable $r5, 0, 14 [always], $noreg, implicit killed $q4, implicit-def $q4 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.118, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14 [always], $noreg + renamable $q12 = VDUP32q killed renamable $r5, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14 [always], $noreg + renamable $q13 = VDUP32q killed renamable $r5, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.92, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.92, 14 [always], $noreg + t2STRDi8 killed $r4, $r4, $r0, 312, 14 [always], $noreg + renamable $r4 = t2ADDri renamable $r0, 296, 14 [always], $noreg, $noreg + renamable $d5 = VSETLNi32 undef renamable $d5, killed renamable $r5, 0, 14 [always], $noreg, implicit-def $q2 + renamable $r5 = t2ADDri renamable $r0, 280, 14 [always], $noreg, $noreg + VST1q32 $r4, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.16 + 16, align 4) + VST1q32 killed $r5, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.16, align 4) + VST1q64 killed $r4, 0, killed $q1, 14 [always], $noreg :: (store 16 into %ir.17, align 8) + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.83, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.83, 14 [always], $noreg + renamable $d9 = VSETLNi32 killed renamable $d9, renamable $r3, 1, 14 [always], $noreg, implicit $q4, implicit-def $q4 + renamable $r4 = t2ADDri renamable $r0, 312, 14 [always], $noreg, $noreg + renamable $d26 = VSETLNi32 killed renamable $d26, killed renamable $r5, 0, 14 [always], $noreg, implicit $q13, implicit-def $q13 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.89, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.89, 14 [always], $noreg + renamable $d8 = VSETLNi32 killed renamable $d8, killed renamable $r5, 1, 14 [always], $noreg, implicit $q4, implicit-def $q4 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.106, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.106, 14 [always], $noreg + VST1q64 killed $r4, 0, killed $q13, 14 [always], $noreg :: (store 16 into %ir.18, align 8) + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.119, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.119, 14 [always], $noreg + renamable $q1 = VDUP32q killed renamable $r5, 14 [always], $noreg + renamable $r5 = t2ADDri renamable $r0, 436, 14 [always], $noreg, $noreg + renamable $d25 = VSETLNi32 killed renamable $d25, killed renamable $r4, 1, 14 [always], $noreg, implicit $q12, implicit-def $q12 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.116, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.116, 14 [always], $noreg + renamable $d27 = VSETLNi32 undef renamable $d27, killed renamable $r4, 0, 14 [always], $noreg, implicit-def $q13 + renamable $r4 = t2ADDri renamable $r0, 344, 14 [always], $noreg, $noreg + VST1q64 killed $r4, 0, killed $q4, 14 [always], $noreg :: (store 16 into %ir.19, align 8) + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.107, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.107, 14 [always], $noreg + renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r4, 1, 14 [always], $noreg, implicit $q1, implicit-def $q1 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.105, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.105, 14 [always], $noreg + renamable $d31 = VSETLNi32 killed renamable $d31, killed renamable $r4, 1, 14 [always], $noreg, implicit $q15, implicit-def $q15 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.99, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.99, 14 [always], $noreg + renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r4, 1, 14 [always], $noreg, implicit $q0, implicit-def $q0 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.93, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.93, 14 [always], $noreg + renamable $d5 = VSETLNi32 killed renamable $d5, killed renamable $r4, 1, 14 [always], $noreg, implicit $q2, implicit-def $q2 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.117, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.117, 14 [always], $noreg + renamable $d27 = VSETLNi32 killed renamable $d27, killed renamable $r4, 1, 14 [always], $noreg, implicit $q13, implicit-def $q13 + renamable $r4 = t2ADDri renamable $r0, 392, 14 [always], $noreg, $noreg + renamable $d4 = VDUP32d killed renamable $r3, 14 [always], $noreg, implicit killed $q2, implicit-def $q2 + renamable $r3 = t2ADDri renamable $r0, 360, 14 [always], $noreg, $noreg + renamable $d26 = VDUP32d killed renamable $r7, 14 [always], $noreg, implicit killed $q13, implicit-def $q13 + renamable $r7 = t2ADDri renamable $r0, 504, 14 [always], $noreg, $noreg + VST1q64 killed $r3, 0, killed $q2, 14 [always], $noreg :: (store 16 into %ir.20, align 8) + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.97, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.97, 14 [always], $noreg + renamable $q2 = VDUP32q killed renamable $r3, 14 [always], $noreg + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.96, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.96, 14 [always], $noreg + renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r3, 0, 14 [always], $noreg, implicit $q2, implicit-def $q2 + renamable $r3 = t2ADDri renamable $r0, 388, 14 [always], $noreg, $noreg + VST1q32 killed $r3, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.21 + 12, align 4) + renamable $r3 = t2ADDri renamable $r0, 376, 14 [always], $noreg, $noreg + VST1q32 killed $r3, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.21, align 4) + renamable $r3 = t2ADDri renamable $r0, 584, 14 [always], $noreg, $noreg + VST1q64 killed $r4, 0, killed $q2, 14 [always], $noreg :: (store 16 into %ir.22, align 8) + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.100, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.100, 14 [always], $noreg + renamable $d1 = VDUP32d killed renamable $r4, 14 [always], $noreg, implicit killed $q0, implicit-def $q0 + renamable $r4 = t2ADDri renamable $r0, 408, 14 [always], $noreg, $noreg + VST1q64 killed $r4, 0, killed $q0, 14 [always], $noreg :: (store 16 into %ir.23, align 8) + renamable $r4 = t2ADDri renamable $r0, 440, 14 [always], $noreg, $noreg + VST1q32 killed $r5, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.24 + 12, align 4) + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.103, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.103, 14 [always], $noreg + renamable $d30 = VDUP32d killed renamable $r5, 14 [always], $noreg, implicit killed $q15, implicit-def $q15 + renamable $r5 = t2ADDri renamable $r0, 424, 14 [always], $noreg, $noreg + VST1q32 killed $r5, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.24, align 4) + VST1q64 killed $r4, 0, killed $q15, 14 [always], $noreg :: (store 16 into %ir.25, align 8) + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.111, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.111, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.110, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.110, 14 [always], $noreg + renamable $d30 = VSETLNi32 undef renamable $d30, killed renamable $r5, 0, 14 [always], $noreg, implicit-def $q15 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.109, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.109, 14 [always], $noreg + renamable $q0 = VDUP32q killed renamable $r5, 14 [always], $noreg + renamable $r5 = t2ADDri renamable $r0, 488, 14 [always], $noreg, $noreg + renamable $d30 = VSETLNi32 killed renamable $d30, killed renamable $r4, 1, 14 [always], $noreg, implicit $q15, implicit-def $q15 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.108, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.108, 14 [always], $noreg + renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r4, 0, 14 [always], $noreg, implicit $q0, implicit-def $q0 + renamable $r4 = t2ADDri renamable $r0, 568, 14 [always], $noreg, $noreg + renamable $d31 = VDUP32d killed renamable $r12, 14 [always], $noreg, implicit killed $q15, implicit-def $q15 + VST1q64 killed $r1, 0, killed $q1, 14 [always], $noreg :: (store 16 into %ir.26, align 8) + renamable $r1 = t2ADDri renamable $r0, 472, 14 [always], $noreg, $noreg + VST1q64 killed $r1, 0, killed $q0, 14 [always], $noreg :: (store 16 into %ir.27, align 8) + renamable $r1 = t2ADDri renamable $r0, 552, 14 [always], $noreg, $noreg + VST1q64 killed $r5, 0, killed $q15, 14 [always], $noreg :: (store 16 into %ir.28, align 8) + renamable $r5 = t2ADDri renamable $r0, 536, 14 [always], $noreg, $noreg + VST1q64 killed $r7, 0, killed $q9, 14 [always], $noreg :: (store 16 into %ir.29, align 8) + renamable $r7 = t2ADDri renamable $r0, 660, 14 [always], $noreg, $noreg + VST1q64 killed $r6, 0, killed $q13, 14 [always], $noreg :: (store 16 into %ir.30, align 8) + VST1q64 killed $r5, 0, killed $q12, 14 [always], $noreg :: (store 16 into %ir.31, align 8) + VST1q64 killed $r1, 0, killed $q14, 14 [always], $noreg :: (store 16 into %ir.32, align 8) + renamable $r1 = t2ADDri renamable $r0, 608, 14 [always], $noreg, $noreg + VST1q64 killed $r4, 0, killed $q8, 14 [always], $noreg :: (store 16 into %ir.33, align 8) + VST1q64 killed $r3, 0, killed $q11, 14 [always], $noreg :: (store 16 into %ir.34, align 8) + t2STRDi8 killed $r2, $r2, $r0, 600, 14 [always], $noreg + VST1q32 killed $r1, 0, $q10, 14 [always], $noreg :: (store 16 into %ir.35, align 4) + $r12 = t2MOVi16 target-flags(arm-lo16) @.str.139, 14 [always], $noreg + $r12 = t2MOVTi16 $r12, target-flags(arm-hi16) @.str.139, 14 [always], $noreg + $r2 = t2MOVi16 target-flags(arm-lo16) @.str.151, 14 [always], $noreg + $r2 = t2MOVTi16 $r2, target-flags(arm-hi16) @.str.151, 14 [always], $noreg + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.134, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.134, 14 [always], $noreg + renamable $r1 = t2ADDri renamable $r0, 620, 14 [always], $noreg, $noreg + renamable $d24 = VSETLNi32 undef renamable $d24, killed renamable $r3, 0, 14 [always], $noreg, implicit-def $q12 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.140, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.140, 14 [always], $noreg + renamable $d23 = VSETLNi32 undef renamable $d23, killed renamable $r3, 0, 14 [always], $noreg, implicit-def $q11 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.146, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.146, 14 [always], $noreg + renamable $d18 = VSETLNi32 undef renamable $d18, killed renamable $r3, 0, 14 [always], $noreg, implicit-def $q9 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.152, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.152, 14 [always], $noreg + renamable $d17 = VSETLNi32 undef renamable $d17, killed renamable $r3, 0, 14 [always], $noreg, implicit-def $q8 + $r3 = t2MOVi16 target-flags(arm-lo16) @.str.136, 14 [always], $noreg + $r3 = t2MOVTi16 $r3, target-flags(arm-hi16) @.str.136, 14 [always], $noreg + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.138, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.138, 14 [always], $noreg + renamable $d28 = VSETLNi32 undef renamable $d28, renamable $r3, 0, 14 [always], $noreg, implicit-def $q14 + renamable $d29 = VSETLNi32 undef renamable $d29, killed renamable $r4, 0, 14 [always], $noreg, implicit killed $q14, implicit-def $q14 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.148, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.148, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.150, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.150, 14 [always], $noreg + renamable $d26 = VSETLNi32 undef renamable $d26, renamable $r4, 0, 14 [always], $noreg, implicit-def $q13 + renamable $d29 = VSETLNi32 killed renamable $d29, renamable $r12, 1, 14 [always], $noreg, implicit $q14, implicit-def $q14 + renamable $d27 = VSETLNi32 undef renamable $d27, killed renamable $r5, 0, 14 [always], $noreg, implicit killed $q13, implicit-def $q13 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.130, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.130, 14 [always], $noreg + renamable $q1 = VDUP32q killed renamable $r5, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.142, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.142, 14 [always], $noreg + renamable $d27 = VSETLNi32 killed renamable $d27, renamable $r2, 1, 14 [always], $noreg, implicit $q13, implicit-def $q13 + renamable $q15 = VDUP32q killed renamable $r5, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.149, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.149, 14 [always], $noreg + renamable $d26 = VSETLNi32 killed renamable $d26, killed renamable $r5, 1, 14 [always], $noreg, implicit $q13, implicit-def $q13 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.145, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.145, 14 [always], $noreg + renamable $q0 = VDUP32q killed renamable $r5, 14 [always], $noreg + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.137, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.137, 14 [always], $noreg + renamable $d28 = VSETLNi32 killed renamable $d28, killed renamable $r5, 1, 14 [always], $noreg, implicit $q14, implicit-def $q14 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.153, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.153, 14 [always], $noreg + renamable $d17 = VSETLNi32 killed renamable $d17, killed renamable $r5, 1, 14 [always], $noreg, implicit $q8, implicit-def $q8 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.147, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.147, 14 [always], $noreg + renamable $d18 = VSETLNi32 killed renamable $d18, killed renamable $r5, 1, 14 [always], $noreg, implicit $q9, implicit-def $q9 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.141, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.141, 14 [always], $noreg + renamable $d23 = VSETLNi32 killed renamable $d23, killed renamable $r5, 1, 14 [always], $noreg, implicit $q11, implicit-def $q11 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.135, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.135, 14 [always], $noreg + renamable $d24 = VSETLNi32 killed renamable $d24, killed renamable $r5, 1, 14 [always], $noreg, implicit $q12, implicit-def $q12 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.144, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.144, 14 [always], $noreg + renamable $d0 = VSETLNi32 killed renamable $d0, killed renamable $r5, 0, 14 [always], $noreg, implicit $q0, implicit-def $q0 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.143, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.143, 14 [always], $noreg + renamable $d31 = VSETLNi32 killed renamable $d31, killed renamable $r5, 1, 14 [always], $noreg, implicit $q15, implicit-def $q15 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.131, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.131, 14 [always], $noreg + renamable $d3 = VSETLNi32 killed renamable $d3, killed renamable $r5, 1, 14 [always], $noreg, implicit $q1, implicit-def $q1 + $r5 = t2MOVi16 target-flags(arm-lo16) @.str.133, 14 [always], $noreg + $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.133, 14 [always], $noreg + renamable $q2 = VDUP32q killed renamable $r5, 14 [always], $noreg + renamable $r5 = t2ADDri renamable $r0, 756, 14 [always], $noreg, $noreg + VST1q32 killed $r1, 0, killed $q10, 14 [always], $noreg :: (store 16 into %ir.35 + 12, align 4) + $r1 = t2MOVi16 target-flags(arm-lo16) @.str.132, 14 [always], $noreg + $r1 = t2MOVTi16 $r1, target-flags(arm-hi16) @.str.132, 14 [always], $noreg + renamable $d19 = VDUP32d killed renamable $r4, 14 [always], $noreg, implicit killed $q9, implicit-def $q9 + $r4 = t2MOVi16 target-flags(arm-lo16) @.str.128, 14 [always], $noreg + $r4 = t2MOVTi16 $r4, target-flags(arm-hi16) @.str.128, 14 [always], $noreg + renamable $d4 = VSETLNi32 killed renamable $d4, killed renamable $r1, 0, 14 [always], $noreg, implicit $q2, implicit-def $q2 + $r6 = t2MOVi16 target-flags(arm-lo16) @.str.129, 14 [always], $noreg + $r6 = t2MOVTi16 $r6, target-flags(arm-hi16) @.str.129, 14 [always], $noreg + renamable $r1 = t2ADDri renamable $r0, 772, 14 [always], $noreg, $noreg + renamable $d16 = VDUP32d killed renamable $r2, 14 [always], $noreg, implicit killed $q8, implicit-def $q8 + renamable $r2 = t2ADDri renamable $r0, 740, 14 [always], $noreg, $noreg + renamable $d22 = VDUP32d killed renamable $r12, 14 [always], $noreg, implicit killed $q11, implicit-def $q11 + renamable $d25 = VDUP32d killed renamable $r3, 14 [always], $noreg, implicit killed $q12, implicit-def $q12 + t2STRDi8 killed $r4, killed $r6, $r0, 636, 14 [always], $noreg + renamable $r4 = t2ADDri renamable $r0, 644, 14 [always], $noreg, $noreg + renamable $r6 = t2ADDri renamable $r0, 692, 14 [always], $noreg, $noreg + VST1q64 killed $r4, 0, killed $q1, 14 [always], $noreg :: (store 16 into %ir.36, align 8) + renamable $r4 = t2ADDri renamable $r0, 724, 14 [always], $noreg, $noreg + VST1q64 killed $r7, 0, killed $q2, 14 [always], $noreg :: (store 16 into %ir.37, align 8) + renamable $r7 = t2ADDri renamable $r0, 708, 14 [always], $noreg, $noreg + renamable $r0 = t2ADDri killed renamable $r0, 676, 14 [always], $noreg, $noreg + VST1q64 killed $r0, 0, killed $q12, 14 [always], $noreg :: (store 16 into %ir.38, align 8) + VST1q64 killed $r6, 0, killed $q14, 14 [always], $noreg :: (store 16 into %ir.39, align 8) + VST1q64 killed $r7, 0, killed $q11, 14 [always], $noreg :: (store 16 into %ir.40, align 8) + VST1q64 killed $r4, 0, killed $q15, 14 [always], $noreg :: (store 16 into %ir.41, align 8) + VST1q64 killed $r2, 0, killed $q0, 14 [always], $noreg :: (store 16 into %ir.42, align 8) + VST1q64 killed $r5, 0, killed $q9, 14 [always], $noreg :: (store 16 into %ir.43, align 8) + VST1q64 killed $r1, 0, killed $q13, 14 [always], $noreg :: (store 16 into %ir.44, align 8) + VST1q64 killed $lr, 0, killed $q8, 14 [always], $noreg :: (store 16 into %ir.45, align 8) + $sp = VLDMDIA_UPD $sp, 14 [always], $noreg, def $d8, def $d9, def $d10, def $d11 + $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r11, def $pc ... @@ -888,9 +888,9 @@ # covers both movw and movt, so we can't allow anything to be inserted between # them. # -# CHECK: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14, $noreg -# CHECK-NEXT: renamable $q12 = VDUP32q killed renamable $r5, 14, $noreg -# CHECK-NEXT: t2B %bb.2, 14, $noreg +# CHECK: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.118, 14 [always], $noreg +# CHECK-NEXT: renamable $q12 = VDUP32q killed renamable $r5, 14 [always], $noreg +# CHECK-NEXT: t2B %bb.2, 14 [always], $noreg # CHECK-NEXT: {{^ $}} # CHECK-NEXT: bb.1 (align 4): # CHECK-NEXT: successors:{{ }} @@ -906,5 +906,5 @@ # CHECK-SAME: $d30, $d31, $r12, $s1, $d0, $d24, $s2, $d1, $q0, $s6, # CHECK-SAME: $d3, $d2, $s4, $q1, $s7, $s5, $d9, $s18, $s19, $q4 # CHECK-NEXT: {{^ $}} -# CHECK-NEXT: $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14, $noreg -# CHECK-NEXT: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14, $noreg +# CHECK-NEXT: $r5 = t2MOVi16 target-flags(arm-lo16) @.str.84, 14 [always], $noreg +# CHECK-NEXT: $r5 = t2MOVTi16 $r5, target-flags(arm-hi16) @.str.84, 14 [always], $noreg Index: llvm/test/CodeGen/ARM/constant-islands-cfg.mir =================================================================== --- llvm/test/CodeGen/ARM/constant-islands-cfg.mir +++ llvm/test/CodeGen/ARM/constant-islands-cfg.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=thumbv6m-apple-ios -run-pass=arm-cp-islands --verify-machine-dom-info %s -o - | FileCheck %s --- | ; Function Attrs: minsize nounwind optsize uwtable @@ -34,18 +35,26 @@ savePoint: '' restorePoint: '' fixedStack: -# CHECK-LABEL: name: test_split_cfg -# CHECK: bb.0: -# CHECK: successors: %[[LONG_BR_BB:bb.[0-9]+]](0x{{[0-9a-f]+}}), %[[DEST1:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}} -# CHECK: tBcc %[[LONG_BR_BB]], 0, $cpsr -# CHECK: tB %[[DEST1]] -# CHECK: [[LONG_BR_BB]]: -# CHECK: successors: %[[DEST2:bb.[0-9]+]](0x{{[0-9a-f]+}}){{$}} -# CHECK: tB %[[DEST2]] -# CHECK: [[DEST1]]: -# CHECK: [[DEST2]]: body: | + ; CHECK-LABEL: name: test_split_cfg + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) + ; CHECK: liveins: $r0 + ; CHECK: tCMPi8 killed $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.1, 0 [equal], $cpsr + ; CHECK: tB %bb.3, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: successors: %bb.4(0x40000000) + ; CHECK: liveins: $cpsr + ; CHECK: tB %bb.4, 14 [always], $noreg + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: dead $r0 = SPACE 256, undef $r0 + ; CHECK: bb.3: + ; CHECK: tPOP_RET 14 [always], $noreg, def $pc + ; CHECK: bb.4: + ; CHECK: tPOP_RET 14 [always], $noreg, def $pc bb.0: liveins: $r0 tCMPi8 killed $r0, 0, 14, $noreg, implicit-def $cpsr Index: llvm/test/CodeGen/ARM/constant-islands-split-IT.mir =================================================================== --- llvm/test/CodeGen/ARM/constant-islands-split-IT.mir +++ llvm/test/CodeGen/ARM/constant-islands-split-IT.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -run-pass=arm-cp-islands %s -o - | FileCheck %s # This test make sure that the constant pool does not keep in the middle of an IT block @@ -66,6 +67,53 @@ isTargetSpecific: false machineFunctionInfo: {} body: | + ; CHECK-LABEL: name: h + ; CHECK: bb.0: + ; CHECK: successors: %bb.4(0x80000000) + ; CHECK: renamable $d0 = VLDRD %const.3, 0, 14 [always], $noreg :: (load 8 from constant-pool) + ; CHECK: dead renamable $r0 = SPACE 40, undef renamable $r0 + ; CHECK: tB %bb.4, 14 [always], $noreg + ; CHECK: bb.1 (align 8): + ; CHECK: successors: + ; CHECK: CONSTPOOL_ENTRY 3, %const.0, 8 + ; CHECK: bb.2: + ; CHECK: successors: + ; CHECK: bb.3 (align 8): + ; CHECK: successors: + ; CHECK: CONSTPOOL_ENTRY 5, %const.2, 8 + ; CHECK: bb.4 (align 2): + ; CHECK: successors: %bb.5(0x80000000) + ; CHECK: dead renamable $r0 = SPACE 790, undef renamable $r0 + ; CHECK: bb.5: + ; CHECK: successors: %bb.7(0x80000000) + ; CHECK: renamable $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPri $r0, 32, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = SPACE 200, undef renamable $r0 + ; CHECK: t2IT 0, 1, implicit-def $itstate + ; CHECK: renamable $d0 = VLDRD %const.7, 0, 0 [equal], $cpsr, implicit $itstate :: (load 8 from constant-pool) + ; CHECK: renamable $d1 = VLDRD %const.5, 0, 0 [equal], $cpsr, implicit $itstate :: (load 8 from constant-pool) + ; CHECK: renamable $d2 = VLDRD %const.6, 0, 0 [equal], $cpsr, implicit $itstate :: (load 8 from constant-pool) + ; CHECK: $r0 = t2SUBri $r0, 12, 0 [equal], $cpsr, $noreg, implicit killed $itstate + ; CHECK: t2B %bb.7, 14 [always], $noreg + ; CHECK: bb.6 (align 8): + ; CHECK: successors: + ; CHECK: CONSTPOOL_ENTRY 7, %const.1, 8 + ; CHECK: bb.7 (align 2): + ; CHECK: successors: + ; CHECK: liveins: $r0, $cpsr, $d0, $s0, $s1, $d1, $s2, $s3, $d2, $s4, $s5 + ; CHECK: t2IT 0, 4, implicit-def $itstate + ; CHECK: $sp = tMOVr $r0, 0 [equal], $cpsr, implicit $itstate + ; CHECK: $sp = t2LDMIA_RET $sp, 0 [equal], killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate + ; CHECK: tBL 14 [always], $noreg, &__stack_chk_fail, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp + ; CHECK: bb.8 (align 8): + ; CHECK: successors: + ; CHECK: CONSTPOOL_ENTRY 6, %const.0, 8 + ; CHECK: bb.9 (align 2): + ; CHECK: successors: %bb.9(0x80000000) + ; CHECK: liveins: $r0 + ; CHECK: dead renamable $r0 = SPACE 4000, undef renamable $r0 + ; CHECK: t2B %bb.9, 14 [always], $noreg + ; CHECK: bb.10: bb.0: successors: %bb.1(0x80000000) @@ -83,11 +131,6 @@ renamable $r0 = t2MOVi 0, 14, _, _ t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr renamable $r0 = SPACE 200, undef renamable $r0 - ; CHECK: t2IT 0, 1, implicit-def $itstate - ; CHECK-NEXT: renamable $d0 = VLDRD %const.7, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) - ; CHECK-NEXT: renamable $d1 = VLDRD %const.5, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) - ; CHECK-NEXT: renamable $d2 = VLDRD %const.6, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) - ; CHECK-NEXT: $r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate t2IT 0, 1, implicit-def $itstate renamable $d0 = VLDRD %const.1, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) renamable $d1 = VLDRD %const.2, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool) Index: llvm/test/CodeGen/ARM/expand-pseudos.mir =================================================================== --- llvm/test/CodeGen/ARM/expand-pseudos.mir +++ llvm/test/CodeGen/ARM/expand-pseudos.mir @@ -67,9 +67,9 @@ ... # CHECK-LABEL: name: test1 -# CHECK: $r1 = MOVi16 500, 0, killed $cpsr, implicit killed $r1 +# CHECK: $r1 = MOVi16 500, 0 [equal], killed $cpsr, implicit killed $r1 # CHECK-LABEL: name: test2 -# CHECK: $r1 = MOVi16 2068, 0, $cpsr, implicit killed $r1 -# CHECK: $r1 = MOVTi16 $r1, 7637, 0, $cpsr +# CHECK: $r1 = MOVi16 2068, 0 [equal], $cpsr, implicit killed $r1 +# CHECK: $r1 = MOVTi16 $r1, 7637, 0 [equal], $cpsr # CHECK-LABEL: name: test3 -# CHECK: $r0 = MOVr killed $r1, 12, killed $cpsr, $noreg, implicit killed $r0 +# CHECK: $r0 = MOVr killed $r1, 12 [greater], killed $cpsr, $noreg, implicit killed $r0 Index: llvm/test/CodeGen/ARM/fpoffset_overflow.mir =================================================================== --- llvm/test/CodeGen/ARM/fpoffset_overflow.mir +++ llvm/test/CodeGen/ARM/fpoffset_overflow.mir @@ -1,12 +1,8 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -mtriple=thumbv7-- -run-pass=stack-protector -run-pass=prologepilog | FileCheck %s --- # This should trigger an emergency spill in the register scavenger because the # frame offset into the large argument is too large. -# CHECK-LABEL: name: func0 -# CHECK: t2STRi12 killed [[SPILLED:\$r[0-9]+]], $sp, 0, 14, $noreg :: (store 4 into %stack.0) -# CHECK: [[SPILLED]] = t2ADDri killed $sp, 4096, 14, $noreg, $noreg -# CHECK: $sp = t2LDRi12 killed [[SPILLED]], 40, 14, $noreg :: (load 4) -# CHECK: [[SPILLED]] = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.0) name: func0 tracksRegLiveness: true fixedStack: @@ -16,6 +12,53 @@ isAliased: false } body: | bb.0: + ; CHECK-LABEL: name: func0 + ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -16 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -20 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -36 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -40 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -44 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -48 + ; CHECK: $sp = frame-setup tSUBspi $sp, 4, 14 [always], $noreg + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 52 + ; CHECK: $r0 = IMPLICIT_DEF + ; CHECK: $r1 = IMPLICIT_DEF + ; CHECK: $r2 = IMPLICIT_DEF + ; CHECK: $r3 = IMPLICIT_DEF + ; CHECK: $r4 = IMPLICIT_DEF + ; CHECK: $r5 = IMPLICIT_DEF + ; CHECK: $r6 = IMPLICIT_DEF + ; CHECK: $r7 = IMPLICIT_DEF + ; CHECK: $r8 = IMPLICIT_DEF + ; CHECK: $r9 = IMPLICIT_DEF + ; CHECK: $r10 = IMPLICIT_DEF + ; CHECK: $r11 = IMPLICIT_DEF + ; CHECK: $r12 = IMPLICIT_DEF + ; CHECK: $lr = IMPLICIT_DEF + ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: $r0 = t2ADDri killed $sp, 4096, 14 [always], $noreg, $noreg + ; CHECK: $sp = t2LDRi12 killed $r0, 40, 14 [always], $noreg :: (load 4) + ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) + ; CHECK: KILL $r0 + ; CHECK: KILL $r1 + ; CHECK: KILL $r2 + ; CHECK: KILL $r3 + ; CHECK: KILL $r4 + ; CHECK: KILL $r5 + ; CHECK: KILL $r6 + ; CHECK: KILL $r7 + ; CHECK: KILL $r8 + ; CHECK: KILL $r9 + ; CHECK: KILL $r10 + ; CHECK: KILL $r11 + ; CHECK: KILL $r12 + ; CHECK: KILL $lr $r0 = IMPLICIT_DEF $r1 = IMPLICIT_DEF $r2 = IMPLICIT_DEF @@ -50,11 +93,6 @@ ... --- # This should not trigger an emergency spill yet. -# CHECK-LABEL: name: func1 -# CHECK-NOT: t2STRi12 -# CHECK-NOT: t2ADDri -# CHECK: $r11 = t2LDRi12 $sp, 4092, 14, $noreg :: (load 4) -# CHECK-NOT: t2LDRi12 name: func1 tracksRegLiveness: true fixedStack: @@ -64,6 +102,47 @@ isAliased: false } body: | bb.0: + ; CHECK-LABEL: name: func1 + ; CHECK: liveins: $r4, $r5, $r6, $r8, $r9, $r10, $r11, $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -16 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -20 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -36 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -40 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -44 + ; CHECK: $sp = frame-setup tSUBspi $sp, 4, 14 [always], $noreg + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 48 + ; CHECK: $r0 = IMPLICIT_DEF + ; CHECK: $r1 = IMPLICIT_DEF + ; CHECK: $r2 = IMPLICIT_DEF + ; CHECK: $r3 = IMPLICIT_DEF + ; CHECK: $r4 = IMPLICIT_DEF + ; CHECK: $r5 = IMPLICIT_DEF + ; CHECK: $r6 = IMPLICIT_DEF + ; CHECK: $r8 = IMPLICIT_DEF + ; CHECK: $r9 = IMPLICIT_DEF + ; CHECK: $r10 = IMPLICIT_DEF + ; CHECK: $r11 = IMPLICIT_DEF + ; CHECK: $r12 = IMPLICIT_DEF + ; CHECK: $lr = IMPLICIT_DEF + ; CHECK: $r11 = t2LDRi12 $sp, 4092, 14 [always], $noreg :: (load 4) + ; CHECK: KILL $r0 + ; CHECK: KILL $r1 + ; CHECK: KILL $r2 + ; CHECK: KILL $r3 + ; CHECK: KILL $r4 + ; CHECK: KILL $r5 + ; CHECK: KILL $r6 + ; CHECK: KILL $r8 + ; CHECK: KILL $r9 + ; CHECK: KILL $r10 + ; CHECK: KILL $r11 + ; CHECK: KILL $r12 + ; CHECK: KILL $lr $r0 = IMPLICIT_DEF $r1 = IMPLICIT_DEF $r2 = IMPLICIT_DEF Index: llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir +++ llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir @@ -1,11 +1,11 @@ # RUN: llc %s -o - -run-pass=if-converter -verify-machineinstrs | FileCheck %s # Make sure we correctly if-convert blocks containing an INLINEASM_BR. # CHECK: t2CMPri killed renamable $r2, 34 -# CHECK-NEXT: $r0 = t2MOVi 2, 1, $cpsr, $noreg -# CHECK-NEXT: $r0 = t2MOVi 3, 0, killed $cpsr, $noreg, implicit killed $r0 -# CHECK-NEXT: tBL 14, $noreg, @fn2 +# CHECK-NEXT: $r0 = t2MOVi 2, 1 [notequal], $cpsr, $noreg +# CHECK-NEXT: $r0 = t2MOVi 3, 0 [equal], killed $cpsr, $noreg, implicit killed $r0 +# CHECK-NEXT: tBL 14 [always], $noreg, @fn2 # CHECK-NEXT: INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes) -# CHECK-NEXT: t2B %bb.1, 14, $noreg +# CHECK-NEXT: t2B %bb.1, 14 [always], $noreg --- | target triple = "thumbv7-unknown-linux-gnueabi" Index: llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir +++ llvm/test/CodeGen/ARM/ifcvt_diamond_unanalyzable.mir @@ -24,7 +24,7 @@ # CHECK: body: | # CHECK: bb.0: -# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr -# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp -# CHECK: $sp = tADDspi $sp, 3, 14, $noreg -# CHECK: tBX_RET 14, $noreg +# CHECK: $sp = tADDspi $sp, 2, 1 [notequal], $cpsr +# CHECK: $sp = tADDspi $sp, 1, 0 [equal], $cpsr, implicit $sp +# CHECK: $sp = tADDspi $sp, 3, 14 [always], $noreg +# CHECK: tBX_RET 14 [always], $noreg Index: llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir +++ llvm/test/CodeGen/ARM/ifcvt_forked_diamond_unanalyzable.mir @@ -35,14 +35,14 @@ # CHECK: bb.0: # CHECK: successors: %bb.2(0x20000000), %bb.1(0x60000000) -# CHECK: $sp = tADDspi $sp, 2, 1, $cpsr -# CHECK: $sp = tADDspi $sp, 1, 0, $cpsr, implicit $sp -# CHECK: t2Bcc %bb.2, 1, $cpsr +# CHECK: $sp = tADDspi $sp, 2, 1 [notequal], $cpsr +# CHECK: $sp = tADDspi $sp, 1, 0 [equal], $cpsr, implicit $sp +# CHECK: t2Bcc %bb.2, 1 [notequal], $cpsr # CHECK: bb.1: -# CHECK: $sp = tADDspi $sp, 4, 14, $noreg -# CHECK: tBX_RET 14, $noreg +# CHECK: $sp = tADDspi $sp, 4, 14 [always], $noreg +# CHECK: tBX_RET 14 [always], $noreg # CHECK: bb.2: -# CHECK: $sp = tADDspi $sp, 3, 14, $noreg -# CHECK: tBX_RET 14, $noreg +# CHECK: $sp = tADDspi $sp, 3, 14 [always], $noreg +# CHECK: tBX_RET 14 [always], $noreg Index: llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir +++ llvm/test/CodeGen/ARM/ifcvt_simple_bad_zero_prob_succ.mir @@ -27,7 +27,7 @@ # CHECK: bb.1: # CHECK: successors: %bb.1(0x80000000) # CHECK-NOT: %bb.2(0x00000000) -# CHECK: tBRIND $r1, 1, $cpsr +# CHECK: tBRIND $r1, 1 [notequal], $cpsr # CHECK: t2B %bb.1 #CHECK-NOT: bb.2: Index: llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir +++ llvm/test/CodeGen/ARM/ifcvt_simple_unanalyzable.mir @@ -19,7 +19,7 @@ # CHECK: body: | # CHECK: bb.0: -# CHECK: $sp = tADDspi $sp, 2, 0, $cpsr -# CHECK: tBX_RET 0, $cpsr -# CHECK: tBX_RET 14, $noreg +# CHECK: $sp = tADDspi $sp, 2, 0 [equal], $cpsr +# CHECK: tBX_RET 0 [equal], $cpsr +# CHECK: tBX_RET 14 [always], $noreg Index: llvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir +++ llvm/test/CodeGen/ARM/ifcvt_triangleSameCvtNext.mir @@ -25,5 +25,5 @@ # CHECK: bb.3: # CHECK: successors: %bb.1 # CHECK-NOT: tADDspi -# CHECK: Bcc %bb.1, 1, $cpsr +# CHECK: Bcc %bb.1, 1 [notequal], $cpsr # CHECK: B %bb.1 Index: llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir =================================================================== --- llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir +++ llvm/test/CodeGen/ARM/ifcvt_triangleWoCvtToNextEdge.mir @@ -38,15 +38,15 @@ # CHECK: bb.0: # CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) -# CHECK: tBcc %bb.2, 1, $cpsr +# CHECK: tBcc %bb.2, 1 [notequal], $cpsr # CHECK: bb.1: # CHECK-NOT: successors: %bb -# CHECK: tBL 14, $cpsr, @__stack_chk_fail +# CHECK: tBL 14 [always], $cpsr, @__stack_chk_fail # CHECK: bb.2: # CHECK-NOT: successors: %bb -# CHECK: tBL 1, $cpsr, @__stack_chk_fail -# CHECK: $sp = tADDspi $sp, 2, 14, $noreg -# CHECK: $sp = tADDspi $sp, 2, 14, $noreg -# CHECK: tTAILJMPdND @bar, 14, $cpsr +# CHECK: tBL 1 [notequal], $cpsr, @__stack_chk_fail +# CHECK: $sp = tADDspi $sp, 2, 14 [always], $noreg +# CHECK: $sp = tADDspi $sp, 2, 14 [always], $noreg +# CHECK: tTAILJMPdND @bar, 14 [always], $cpsr Index: llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir =================================================================== --- llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir +++ llvm/test/CodeGen/ARM/load_store_opt_clobber_cpsr.mir @@ -5,12 +5,12 @@ # Make sure bb.1 is transformed, so the test doesn't accidentally break. # CHECK-LABEL: bb.0: -# CHECK: renamable $r0 = tLDRi renamable $r4, 0, 14, $noreg :: (load 4) -# CHECK: renamable $r1 = tLDRi renamable $r4, 1, 14, $noreg :: (load 4) +# CHECK: renamable $r0 = tLDRi renamable $r4, 0, 14 [always], $noreg :: (load 4) +# CHECK: renamable $r1 = tLDRi renamable $r4, 1, 14 [always], $noreg :: (load 4) # CHECK-LABEL: bb.1: -# CHECK: $r4 = tLDMIA_UPD $r4, 14, $noreg, def $r0, def $r1 -# CHECK: $r4, dead $cpsr = tSUBi8 $r4, 8, 14, $noreg +# CHECK: $r4 = tLDMIA_UPD $r4, 14 [always], $noreg, def $r0, def $r1 +# CHECK: $r4, dead $cpsr = tSUBi8 $r4, 8, 14 [always], $noreg name: foo tracksRegLiveness: true Index: llvm/test/CodeGen/ARM/load_store_opt_kill.mir =================================================================== --- llvm/test/CodeGen/ARM/load_store_opt_kill.mir +++ llvm/test/CodeGen/ARM/load_store_opt_kill.mir @@ -1,12 +1,13 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=armv7-none-eabi -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s --- -# CHECK-LABEL: name: f name: f # Make sure the load into $r0 doesn't clobber the base register before the second load uses it. -# CHECK: $r3 = LDRi12 $r0, 12, 14, $noreg -# CHECK-NEXT: $r0 = LDRi12 $r0, 8, 14, $noreg body: | bb.0: liveins: $r0, $r3 + ; CHECK-LABEL: name: f + ; CHECK: $r3 = LDRi12 $r0, 12, 14 [always], $noreg + ; CHECK: $r0 = LDRi12 $r0, 8, 14 [always], $noreg $r0, $r3 = LDRD $r0, $noreg, 8, 14, $noreg ... Index: llvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir =================================================================== --- llvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir +++ llvm/test/CodeGen/ARM/load_store_opt_reg_limit.mir @@ -1,9 +1,9 @@ # RUN: llc -mtriple=thumbv7--linux-android -verify-machineinstrs -run-pass=arm-ldst-opt %s -o - | FileCheck %s --check-prefix=CHECK-MERGE #CHECK-MERGE: foo name: foo -# CHECK-MERGE: VSTMDIA $r4, 14, $noreg, $d15, $d16, $d17, $d18, $d19, $d20, $d21, $d22, $d23, $d24, $d25, $d26, $d27, $d28, $d29, $d30 -# CHECK-MERGE-NEXT: VSTRD $d31, $r4, 32, 14, $noreg :: (store 8) -# CHECK-MERGE: VSTMDIA killed $r0, 14, $noreg, $d4, $d5, $d6, $d7, $d8, $d9, $d10, $d11, $d12, $d13, $d14 +# CHECK-MERGE: VSTMDIA $r4, 14 [always], $noreg, $d15, $d16, $d17, $d18, $d19, $d20, $d21, $d22, $d23, $d24, $d25, $d26, $d27, $d28, $d29, $d30 +# CHECK-MERGE-NEXT: VSTRD $d31, $r4, 32, 14 [always], $noreg :: (store 8) +# CHECK-MERGE: VSTMDIA killed $r0, 14 [always], $noreg, $d4, $d5, $d6, $d7, $d8, $d9, $d10, $d11, $d12, $d13, $d14 body: | bb.0: VSTRD $d15, $r4, 0, 14, $noreg :: (store 8) Index: llvm/test/CodeGen/ARM/machine-copyprop.mir =================================================================== --- llvm/test/CodeGen/ARM/machine-copyprop.mir +++ llvm/test/CodeGen/ARM/machine-copyprop.mir @@ -1,18 +1,19 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -mtriple=armv7s-- -run-pass=machine-cp | FileCheck %s --- # Test that machine copy prop recognizes the implicit-def operands on a COPY # as clobbering the register. -# CHECK-LABEL: name: func -# CHECK: $d2 = VMOVv2i32 2, 14, $noreg -# CHECK: $s5 = COPY $s0, implicit $q1, implicit-def $q1 -# CHECK: VST1q32 $r0, 0, $q1, 14, $noreg # The following two COPYs must not be removed -# CHECK: $s4 = COPY $s20, implicit-def $q1 -# CHECK: $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1 -# CHECK: VST1q32 $r2, 0, $q1, 14, $noreg name: func body: | bb.0: + ; CHECK-LABEL: name: func + ; CHECK: $d2 = VMOVv2i32 2, 14 [always], $noreg + ; CHECK: $s5 = COPY $s0, implicit $q1, implicit-def $q1 + ; CHECK: VST1q32 $r0, 0, $q1, 14 [always], $noreg + ; CHECK: $s4 = COPY $s20, implicit-def $q1 + ; CHECK: $s5 = COPY $s0, implicit killed $d0, implicit $q1, implicit-def $q1 + ; CHECK: VST1q32 $r2, 0, $q1, 14 [always], $noreg $d2 = VMOVv2i32 2, 14, $noreg $s5 = COPY $s0, implicit $q1, implicit-def $q1 VST1q32 $r0, 0, $q1, 14, $noreg Index: llvm/test/CodeGen/ARM/peephole-phi.mir =================================================================== --- llvm/test/CodeGen/ARM/peephole-phi.mir +++ llvm/test/CodeGen/ARM/peephole-phi.mir @@ -7,20 +7,20 @@ # CHECK-LABEL: name: func # CHECK: body: | # CHECK: bb.0: -# CHECK: Bcc %bb.2, 1, undef $cpsr +# CHECK: Bcc %bb.2, 1 [notequal], undef $cpsr # # CHECK: bb.1: # CHECK: %0:dpr = IMPLICIT_DEF -# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, $noreg +# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14 [always], $noreg # CHECK: B %bb.3 # # CHECK: bb.2: # CHECK: %3:spr = IMPLICIT_DEF -# CHECK: %4:gpr = VMOVRS %3, 14, $noreg +# CHECK: %4:gpr = VMOVRS %3, 14 [always], $noreg # # CHECK: bb.3: # CHECK: %5:gpr = PHI %1, %bb.1, %4, %bb.2 -# CHECK: %6:spr = VMOVSR %5, 14, $noreg +# CHECK: %6:spr = VMOVSR %5, 14 [always], $noreg --- name: func0 tracksRegLiveness: true @@ -71,18 +71,18 @@ # CHECK-LABEL: name: func-undefops # CHECK: body: | # CHECK: bb.0: -# CHECK: Bcc %bb.2, 1, undef $cpsr +# CHECK: Bcc %bb.2, 1 [notequal], undef $cpsr # # CHECK: bb.1: -# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, $noreg +# CHECK: %0:gpr = VMOVRS undef %1:spr, 14 [always], $noreg # CHECK: B %bb.3 # # CHECK: bb.2: -# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, $noreg +# CHECK: %2:gpr = VMOVRS undef %3:spr, 14 [always], $noreg # # CHECK: bb.3: # CHECK: %4:gpr = PHI %0, %bb.1, %2, %bb.2 -# CHECK: %5:spr = VMOVSR %4, 14, $noreg +# CHECK: %5:spr = VMOVSR %4, 14 [always], $noreg --- name: func-undefops tracksRegLiveness: true Index: llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir =================================================================== --- llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir +++ llvm/test/CodeGen/ARM/regcoal-invalid-subrange-update.mir @@ -65,7 +65,7 @@ ; CHECK: %4.dsub_3:qqqqpr_with_ssub_4 = COPY %4.dsub_1 ; CHECK: KILL implicit-def %4.dsub_2, implicit %4.qqsub_0 ; CHECK: %4.dsub_4:qqqqpr_with_ssub_4 = COPY %4.dsub_1 - ; CHECK: tBX_RET 14, $noreg, implicit %4.ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 + ; CHECK: tBX_RET 14 [always], $noreg, implicit %4.ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9 %3:dpr_vfp2 = COPY $d4 undef %0.ssub_0:dpr_vfp2 = COPY $s1 %1:dpr_vfp2 = COPY $d2 Index: llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir =================================================================== --- llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir +++ llvm/test/CodeGen/ARM/register-scavenger-exceptions.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -run-pass=prologepilog | FileCheck %s --- | @@ -18,8 +19,6 @@ # Check that the register scavenger does pick r5 (not preserved in prolog) for # materialising a stack frame address when the function ends in throwing an # exception. -# CHECK: $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r10, killed $r11, killed $lr -# CHECK-NOT: $r5 name: _Z3foov stack: - { id: 0, name: V1, type: default, offset: 0, size: 5000, alignment: 8, @@ -36,6 +35,25 @@ body: | bb.0.entry: + ; CHECK-LABEL: name: _Z3foov + ; CHECK: $sp = frame-setup STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r10, killed $r11, killed $lr + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -12 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 + ; CHECK: $r11 = frame-setup ADDri killed $sp, 8, 14 [always], $noreg, $noreg + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r11, 8 + ; CHECK: $sp = frame-setup SUBri killed $sp, 912, 14 [always], $noreg, $noreg + ; CHECK: $sp = frame-setup SUBri killed $sp, 4096, 14 [always], $noreg, $noreg + ; CHECK: $r0 = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $r1 = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $r2 = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $r3 = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $r4 = MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: $r10 = SUBri killed $r11, 4096, 14 [always], $noreg, $noreg + ; CHECK: STRi12 killed $lr, killed $r10, -916, 14 [always], $noreg :: (store 4 into %stack.2) + ; CHECK: BL @_Z3barv, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3, implicit killed $r4, implicit-def $sp $r0 = MOVi 0, 14, $noreg, $noreg $r1 = MOVi 0, 14, $noreg, $noreg $r2 = MOVi 0, 14, $noreg, $noreg Index: llvm/test/CodeGen/ARM/tail-dup-bundle.mir =================================================================== --- llvm/test/CodeGen/ARM/tail-dup-bundle.mir +++ llvm/test/CodeGen/ARM/tail-dup-bundle.mir @@ -1,18 +1,39 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -o - %s -run-pass=block-placement -mtriple=thumbv7k-apple-ios8.0.0 -verify-machineinstrs -O3 | FileCheck %s --- -# CHECK-LABEL: name: func # Make sure the bundle gets duplicated correctly -# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { -# CHECK: t2IT 1, 24, implicit-def $itstate -# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate -# CHECK: } -# CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { -# CHECK: t2IT 1, 24, implicit-def $itstate -# CHECK: t2CMPri killed $r0, 9, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate -# CHECK: } name: func tracksRegLiveness: true body: | + ; CHECK-LABEL: name: func + ; CHECK: bb.0: + ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: $r0, $lr, $r7 + ; CHECK: t2CMPri $r0, 32, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { + ; CHECK: t2IT 1, 24, implicit-def $itstate + ; CHECK: t2CMPri killed $r0, 9, 1 [notequal], killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate + ; CHECK: } + ; CHECK: t2Bcc %bb.3, 1 [notequal], killed $cpsr + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: $r0 = IMPLICIT_DEF + ; CHECK: t2CMPri $r0, 32, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { + ; CHECK: t2IT 1, 24, implicit-def $itstate + ; CHECK: t2CMPri killed $r0, 9, 1 [notequal], killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate + ; CHECK: } + ; CHECK: t2Bcc %bb.2, 0 [equal], killed $cpsr + ; CHECK: bb.3: + ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) + ; CHECK: $r0 = IMPLICIT_DEF + ; CHECK: t2CMPri $r0, 32, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $cpsr, implicit killed $r0, implicit killed $cpsr { + ; CHECK: t2IT 1, 24, implicit-def $itstate + ; CHECK: t2CMPri killed $r0, 9, 1 [notequal], killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate + ; CHECK: } + ; CHECK: t2Bcc %bb.3, 1 [notequal], killed $cpsr + ; CHECK: t2B %bb.2, 14 [always], $noreg bb.0: liveins: $r0, $lr, $r7 Index: llvm/test/CodeGen/ARM/tst-peephole.mir =================================================================== --- llvm/test/CodeGen/ARM/tst-peephole.mir +++ llvm/test/CodeGen/ARM/tst-peephole.mir @@ -4,12 +4,12 @@ # transform cases which aren't legal. # CHECK-LABEL: name: foo_transform -# CHECK: %2:gpr = ANDri %0, 1, 14, $noreg, def $cpsr -# CHECK-NEXT: %3:gpr = MOVCCi16 %1, 5, 0, $cpsr +# CHECK: %2:gpr = ANDri %0, 1, 14 [always], $noreg, def $cpsr +# CHECK-NEXT: %3:gpr = MOVCCi16 %1, 5, 0 [equal], $cpsr # CHECK-LABEL: name: foo_notransform -# CHECK: TSTri %0, 1, 14, $noreg, implicit-def $cpsr -# CHECK-NEXT: %2:gpr = MOVCCi16 %1, 5, 0, $cpsr +# CHECK: TSTri %0, 1, 14 [always], $noreg, implicit-def $cpsr +# CHECK-NEXT: %2:gpr = MOVCCi16 %1, 5, 0 [equal], $cpsr --- | target triple = "armv7-unknown-unknown" Index: llvm/test/CodeGen/ARM/vldm-liveness.mir =================================================================== --- llvm/test/CodeGen/ARM/vldm-liveness.mir +++ llvm/test/CodeGen/ARM/vldm-liveness.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -run-pass arm-ldst-opt -verify-machineinstrs %s -o - | FileCheck %s # ARM load store optimizer was dealing with a sequence like: # s1 = VLDRS [r0, 1], implicit-def Q0 @@ -26,15 +27,17 @@ bb.0 (%ir-block.0): liveins: $r0 + ; CHECK-LABEL: name: foo + ; CHECK: $s3 = VLDRS $r0, 2, 14 [always], $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4) + ; CHECK: VLDMSIA $r0, 14 [always], $noreg, def $s0, def $s1, implicit-def $noreg :: (load 4) + ; CHECK: $s2 = VLDRS killed $r0, 4, 14 [always], $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $s1 = VLDRS $r0, 1, 14, $noreg, implicit-def $q0 :: (load 4) $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) - ; CHECK: $s3 = VLDRS $r0, 2, 14, $noreg, implicit killed undef $q0, implicit-def $q0 :: (load 4) $s0 = VLDRS $r0, 0, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) - ; CHECK: VLDMSIA $r0, 14, $noreg, def $s0, def $s1, implicit-def $noreg $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) - ; CHECK: $s2 = VLDRS killed $r0, 4, 14, $noreg, implicit killed $q0, implicit-def $q0 :: (load 4) tBX_RET 14, $noreg, implicit $q0 ... Index: llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir =================================================================== --- llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir +++ llvm/test/CodeGen/MIR/ARM/bundled-instructions.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple thumbv7-apple-ios -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the bundled machine instructions # and 'internal' register flags correctly. @@ -28,14 +29,15 @@ bb.0.entry: liveins: $r0 ; CHECK-LABEL: name: test1 - ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr - ; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate - ; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate - ; CHECK-NEXT: } - ; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg - ; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: $r1 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMNri killed $r0, 78, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + ; CHECK: t2IT 12, 8, implicit-def $itstate + ; CHECK: $r1 = t2MOVi 1, 12 [greater], killed $cpsr, $noreg, implicit internal killed $itstate + ; CHECK: } + ; CHECK: $r0 = tMOVr killed $r1, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 $r1 = t2MOVi 0, 14, _, _ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { @@ -58,14 +60,15 @@ ; '{' or '}'. ; CHECK-LABEL: name: test2 - ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK-NEXT: t2CMNri killed $r0, 78, 14, $noreg, implicit-def $cpsr - ; CHECK-NEXT: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { - ; CHECK-NEXT: t2IT 12, 8, implicit-def $itstate - ; CHECK-NEXT: $r1 = t2MOVi 1, 12, killed $cpsr, $noreg, implicit internal killed $itstate - ; CHECK-NEXT: } - ; CHECK-NEXT: $r0 = tMOVr killed $r1, 14, $noreg - ; CHECK-NEXT: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: $r1 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMNri killed $r0, 78, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { + ; CHECK: t2IT 12, 8, implicit-def $itstate + ; CHECK: $r1 = t2MOVi 1, 12 [greater], killed $cpsr, $noreg, implicit internal killed $itstate + ; CHECK: } + ; CHECK: $r0 = tMOVr killed $r1, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 $r1 = t2MOVi 0, 14, _, _ t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr { t2IT 12, 8, implicit-def $itstate Index: llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir =================================================================== --- llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir +++ llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir @@ -1,7 +1,6 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py --- | ; RUN: llc --run-pass=prologepilog -o - %s | FileCheck %s - ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK-NEXT: $sp = frame-setup t2SUBspImm12 killed $sp, 4008, 14, $noreg target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7-none-none-eabi" @@ -77,6 +76,21 @@ machineFunctionInfo: {} body: | bb.0.entry: + ; CHECK-LABEL: name: foo + ; CHECK: liveins: $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 + ; CHECK: $r7 = frame-setup tMOVr killed $sp, 14 [always], $noreg + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 + ; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 4008, 14 [always], $noreg + ; CHECK: renamable $r0 = t2ADDri $sp, 8, 14 [always], $noreg, $noreg + ; CHECK: t2STRi12 killed renamable $r0, $sp, 4, 14 [always], $noreg :: (store 4 into %ir.s) + ; CHECK: renamable $r0 = t2LDRi12 $sp, 4, 14 [always], $noreg :: (dereferenceable load 4 from %ir.s) + ; CHECK: tBL 14 [always], $noreg, @bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp + ; CHECK: $sp = t2ADDspImm12 killed $sp, 4008, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r7, def $pc renamable $r0 = t2ADDri %stack.0.v, 0, 14, $noreg, $noreg t2STRi12 killed renamable $r0, %stack.1.s, 0, 14, $noreg :: (store 4 into %ir.s) renamable $r0 = t2LDRi12 %stack.1.s, 0, 14, $noreg :: (dereferenceable load 4 from %ir.s) Index: llvm/test/CodeGen/Thumb/peephole-cmp.mir =================================================================== --- llvm/test/CodeGen/Thumb/peephole-cmp.mir +++ llvm/test/CodeGen/Thumb/peephole-cmp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s --- | target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" @@ -18,6 +19,21 @@ - { reg: '$r0', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%2' } body: | + ; CHECK-LABEL: name: test_subrr + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 + ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 8 [higher], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %3 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -38,11 +54,6 @@ $r0 = COPY %3 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_subrr -# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1 -# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY0]], 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 8, $cpsr ... --- name: test_subrr_c @@ -50,6 +61,21 @@ - { reg: '$r0', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%2' } body: | + ; CHECK-LABEL: name: test_subrr_c + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 + ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %2:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 3 [lower], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %3 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -70,17 +96,26 @@ $r0 = COPY %3 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_subrr_c -# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1 -# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 3, $cpsr ... --- name: test_subri3 liveins: - { reg: '$r0', virtual-reg: '%1' } body: | + ; CHECK-LABEL: name: test_subri3 + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %1:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14 [always], $noreg + ; CHECK: tBcc %bb.2, 3 [lower], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY %1 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0 @@ -100,16 +135,26 @@ $r0 = COPY %2 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_subri3 -# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 3, $cpsr ... --- name: test_subri8 liveins: - { reg: '$r0', virtual-reg: '%1' } body: | + ; CHECK-LABEL: name: test_subri8 + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %1:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14 [always], $noreg + ; CHECK: tBcc %bb.2, 3 [lower], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY %1 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0 @@ -129,10 +174,6 @@ $r0 = COPY %2 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_subri8 -# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 3, $cpsr ... --- name: test_addrr @@ -140,6 +181,21 @@ - { reg: '$r0', virtual-reg: '%1' } - { reg: '$r1', virtual-reg: '%2' } body: | + ; CHECK-LABEL: name: test_addrr + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 + ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY]], [[COPY1]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 2 [highersame], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %3 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -160,17 +216,26 @@ $r0 = COPY %3 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_addrr -# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1 -# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY0]], 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 2, $cpsr ... --- name: test_addri3 liveins: - { reg: '$r0', virtual-reg: '%1' } body: | + ; CHECK-LABEL: name: test_addri3 + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %0:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14 [always], $noreg + ; CHECK: tBcc %bb.2, 2 [highersame], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0 @@ -190,16 +255,26 @@ $r0 = COPY %2 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_addri3 -# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 2, $cpsr ... --- name: test_addri8 liveins: - { reg: '$r0', virtual-reg: '%1' } body: | + ; CHECK-LABEL: name: test_addri8 + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 + ; CHECK: %0:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14 [always], $noreg + ; CHECK: tBcc %bb.2, 2 [highersame], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0 @@ -219,8 +294,4 @@ $r0 = COPY %2 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test_addri8 -# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 -# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14, $noreg -# CHECK-NEXT: tBcc %bb.2, 2, $cpsr ... Index: llvm/test/CodeGen/Thumb/peephole-mi.mir =================================================================== --- llvm/test/CodeGen/Thumb/peephole-mi.mir +++ llvm/test/CodeGen/Thumb/peephole-mi.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s --- | target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" @@ -24,12 +25,21 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_adc + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: [[tADC:%[0-9]+]]:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: %3:tgpr, $cpsr = tADC [[COPY1]], [[COPY]], 14 [always], $noreg, implicit $cpsr + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %4:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %3 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -58,14 +68,23 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_adc_mov + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: [[tADC:%[0-9]+]]:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr - ; CHECK: [[tMOVi8_:%[0-9]+]]:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tCMPi8 [[tADC]], 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: %3:tgpr, dead $cpsr = tADC [[COPY1]], [[COPY]], 14 [always], $noreg, implicit $cpsr + ; CHECK: %4:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tCMPi8 %3, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %5:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %3 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -95,12 +114,21 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_sbc + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tADDrr:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: [[tSBC:%[0-9]+]]:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14, $noreg, implicit $cpsr - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: %3:tgpr, $cpsr = tSBC [[COPY1]], [[COPY]], 14 [always], $noreg, implicit $cpsr + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %4:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %3 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -128,10 +156,19 @@ - { reg: '$r0', virtual-reg: '%0' } body: | ; CHECK-LABEL: name: test_rsb + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tRSB:%[0-9]+]]:tgpr, $cpsr = tRSB [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %1:tgpr, $cpsr = tRSB [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %1 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -158,11 +195,20 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_and + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tAND:%[0-9]+]]:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tAND [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -190,11 +236,20 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_orr + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tORR:%[0-9]+]]:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tORR [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -222,11 +277,20 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_eor + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tEOR:%[0-9]+]]:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tEOR [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -254,11 +318,20 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_bic + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tBIC:%[0-9]+]]:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tBIC [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -285,10 +358,19 @@ - { reg: '$r0', virtual-reg: '%0' } body: | ; CHECK-LABEL: name: test_mvn + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tMVN:%[0-9]+]]:tgpr, $cpsr = tMVN [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %1:tgpr, $cpsr = tMVN [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %1 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -315,11 +397,20 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_asrrr + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tASRrr:%[0-9]+]]:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tASRrr [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -346,10 +437,19 @@ - { reg: '$r0', virtual-reg: '%0' } body: | ; CHECK-LABEL: name: test_asrri + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tASRri:%[0-9]+]]:tgpr, $cpsr = tASRri [[COPY]], 1, 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %1:tgpr, $cpsr = tASRri [[COPY]], 1, 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %2:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %1 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 @@ -376,11 +476,20 @@ - { reg: '$r1', virtual-reg: '%1' } body: | ; CHECK-LABEL: name: test_ror + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 - ; CHECK: [[tROR:%[0-9]+]]:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14, $noreg - ; CHECK: tBcc %bb.2, 1, $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: %2:tgpr, $cpsr = tROR [[COPY1]], [[COPY]], 14 [always], $noreg + ; CHECK: tBcc %bb.2, 1 [notequal], $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[COPY1]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 + ; CHECK: bb.2: + ; CHECK: %3:tgpr, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $r0 = COPY %2 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1 Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir @@ -149,7 +149,7 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 24 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -8 @@ -157,19 +157,19 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -20 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -24 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14, $noreg :: (load 4 from %fixed-stack.6, align 8) - ; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14, $noreg + ; CHECK: renamable $r12 = t2LDRi12 $sp, 48, 14 [always], $noreg :: (load 4 from %fixed-stack.6, align 8) + ; CHECK: renamable $r5 = t2ADDri renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r7, dead $cpsr = tLSRri killed renamable $r5, 2, 14 [always], $noreg ; CHECK: dead $lr = t2WLS renamable $r7, %bb.3 ; CHECK: bb.1.for.body.lr.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $r12 - ; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) - ; CHECK: $r4 = tMOVr killed $r7, 14, $noreg - ; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) + ; CHECK: $r6, $r5 = t2LDRDi8 $sp, 40, 14 [always], $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) + ; CHECK: $r4 = tMOVr killed $r7, 14 [always], $noreg + ; CHECK: $r7, $r8 = t2LDRDi8 $sp, 24, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14, $noreg + ; CHECK: renamable $r5, dead $cpsr = tSUBi3 killed renamable $r7, 4, 14 [always], $noreg ; CHECK: bb.2.for.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r8, $r12 @@ -180,20 +180,20 @@ ; CHECK: renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 4, 1, renamable $vpr :: (load 16 from %ir.input_1_cast, align 4) ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r3, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q3 = MVE_VADD_qr_i32 killed renamable $q3, renamable $r2, 0, $noreg, undef renamable $q3 - ; CHECK: $lr = tMOVr $r4, 14, $noreg + ; CHECK: $lr = tMOVr $r4, 14 [always], $noreg ; CHECK: renamable $q2 = MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 - ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tSUBi8 killed $r4, 1, 14 [always], $noreg ; CHECK: renamable $q2 = MVE_VADD_qr_i32 killed renamable $q2, renamable $r8, 0, $noreg, undef renamable $q2 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $q2 = MVE_VMAXu32 killed renamable $q2, renamable $q1, 1, renamable $vpr, undef renamable $q2 ; CHECK: renamable $q2 = MVE_VMINu32 killed renamable $q2, renamable $q0, 1, killed renamable $vpr, undef renamable $q2 ; CHECK: renamable $r6 = MVE_VADDVu32no_acc killed renamable $q2, 0, $noreg - ; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: early-clobber renamable $r5 = t2STR_PRE killed renamable $r6, killed renamable $r5, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep2) ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir @@ -87,22 +87,22 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: $lr = t2DLS killed $r0 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg ; CHECK: bb.1.while.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep2) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.while.end: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir @@ -122,50 +122,50 @@ ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: tCBZ $r2, %bb.3 ; CHECK: bb.1.bb3: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14, $noreg - ; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg - ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14, $noreg - ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14, $noreg, $noreg - ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14, $noreg :: (dereferenceable load 2 from %ir.mask.gep9) - ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: $vpr = VMSR_P0 $r5, 14, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) + ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @mask, 14 [always], $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDi3 renamable $r2, 3, 14 [always], $noreg + ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @mask, 14 [always], $noreg + ; CHECK: renamable $r4 = t2BICri killed renamable $r4, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = t2LDRHi12 killed renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 2 from %ir.mask.gep9) + ; CHECK: renamable $r12 = t2SUBri killed renamable $r4, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: $vpr = VMSR_P0 $r5, 14 [always], $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r12, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 [always], $noreg, $noreg + ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q0 - ; CHECK: $r3 = tMOVr $r0, 14, $noreg + ; CHECK: $r3 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) ; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $r3, renamable $q2 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 [always], $noreg ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $r12, renamable $q2 = MVE_VLDRWU32_pre killed renamable $r12, 16, 0, $noreg :: (load 16 from %ir.scevgep2, align 8) ; CHECK: MVE_VPTv4u32 8, renamable $q0, killed renamable $q2, 2, implicit-def $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q1, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) - ; CHECK: $r0 = tMOVr $r3, 14, $noreg + ; CHECK: $r0 = tMOVr $r3, 14 [always], $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-ignore-vctp.mir @@ -96,12 +96,12 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14, $noreg - ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tLSLri killed renamable $r2, 1, 14 [always], $noreg + ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.do.body (align 4): @@ -110,11 +110,11 @@ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg - ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.do.end: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.3 (align 16): ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir @@ -105,21 +105,21 @@ ; CHECK-LABEL: name: use_before_def ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg + ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -128,14 +128,14 @@ ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update2.mir @@ -101,20 +101,20 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 renamable $r3 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg + ; CHECK: renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r4, def $pc, implicit killed $itstate ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv1416, align 4) ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 @@ -122,7 +122,7 @@ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: ; CHECK: t2IT 11, 8, implicit-def dead $itstate - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir @@ -127,53 +127,53 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg - ; CHECK: tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) - ; CHECK: tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2) - ; CHECK: tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3) - ; CHECK: tB %bb.3, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 [always], $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: tSTRspi killed $r1, $sp, 7, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: tSTRspi killed $r2, $sp, 6, 14 [always], $noreg :: (store 4 into %stack.1) + ; CHECK: tSTRspi killed $r0, $sp, 5, 14 [always], $noreg :: (store 4 into %stack.2) + ; CHECK: tSTRspi killed $r3, $sp, 4, 14 [always], $noreg :: (store 4 into %stack.3) + ; CHECK: tB %bb.3, 14 [always], $noreg ; CHECK: bb.1.for.body: ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000) - ; CHECK: $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4) - ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11) - ; CHECK: $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5) - ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) - ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg - ; CHECK: $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6) - ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3) - ; CHECK: $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7) - ; CHECK: $lr = tMOVr killed $r1, 14, $noreg - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr - ; CHECK: $r12 = tMOVr killed $lr, 14, $noreg - ; CHECK: tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1) - ; CHECK: tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2) - ; CHECK: t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3) - ; CHECK: tBcc %bb.3, 1, killed $cpsr - ; CHECK: tB %bb.2, 14, $noreg + ; CHECK: $r0 = tLDRspi $sp, 3, 14 [always], $noreg :: (load 4 from %stack.4) + ; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep11) + ; CHECK: $r2 = tLDRspi $sp, 2, 14 [always], $noreg :: (load 4 from %stack.5) + ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14 [always], $noreg + ; CHECK: $r3 = tLDRspi $sp, 1, 14 [always], $noreg :: (load 4 from %stack.6) + ; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, killed renamable $r3, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep3) + ; CHECK: $r1 = tLDRspi $sp, 0, 14 [always], $noreg :: (load 4 from %stack.7) + ; CHECK: $lr = tMOVr killed $r1, 14 [always], $noreg + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, def $cpsr + ; CHECK: $r12 = tMOVr killed $lr, 14 [always], $noreg + ; CHECK: tSTRspi killed $r0, $sp, 7, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: tSTRspi killed $r2, $sp, 6, 14 [always], $noreg :: (store 4 into %stack.1) + ; CHECK: tSTRspi killed $r3, $sp, 5, 14 [always], $noreg :: (store 4 into %stack.2) + ; CHECK: t2STRi12 killed $r12, $sp, 16, 14 [always], $noreg :: (store 4 into %stack.3) + ; CHECK: tBcc %bb.3, 1 [notequal], killed $cpsr + ; CHECK: tB %bb.2, 14 [always], $noreg ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: $sp = tADDspi $sp, 8, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: $sp = tADDspi $sp, 8, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.3.for.header: ; CHECK: successors: %bb.1(0x80000000) - ; CHECK: $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3) - ; CHECK: $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2) - ; CHECK: $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1) - ; CHECK: $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0) - ; CHECK: tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7) - ; CHECK: tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6) - ; CHECK: tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5) - ; CHECK: tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4) - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: $r0 = tLDRspi $sp, 4, 14 [always], $noreg :: (load 4 from %stack.3) + ; CHECK: $r1 = tLDRspi $sp, 5, 14 [always], $noreg :: (load 4 from %stack.2) + ; CHECK: $r2 = tLDRspi $sp, 6, 14 [always], $noreg :: (load 4 from %stack.1) + ; CHECK: $r3 = tLDRspi $sp, 7, 14 [always], $noreg :: (load 4 from %stack.0) + ; CHECK: tSTRspi killed $r0, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.7) + ; CHECK: tSTRspi killed $r1, $sp, 1, 14 [always], $noreg :: (store 4 into %stack.6) + ; CHECK: tSTRspi killed $r2, $sp, 2, 14 [always], $noreg :: (store 4 into %stack.5) + ; CHECK: tSTRspi killed $r3, $sp, 3, 14 [always], $noreg :: (store 4 into %stack.4) + ; CHECK: tB %bb.1, 14 [always], $noreg bb.0.entry: successors: %bb.3(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir @@ -98,18 +98,18 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -118,13 +118,13 @@ ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRHU16_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 7, 14 [always], $noreg ; CHECK: renamable $q0 = nsw MVE_VADDi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $r0 = MVE_VSTRHU16_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir @@ -106,18 +106,18 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -126,13 +126,13 @@ ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRWU32_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 5, 14 [always], $noreg ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir @@ -99,18 +99,18 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2ADDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -119,13 +119,13 @@ ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv13, align 4) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1416, align 4) - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 15, 14 [always], $noreg ; CHECK: renamable $q0 = nsw MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir @@ -132,27 +132,27 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.1) - ; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0, killed $cpsr + ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 [always], $noreg :: (load 4 from %fixed-stack.1) + ; CHECK: t2CMPri renamable $r12, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.3, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8) + ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr - ; CHECK: $r4 = tMOVr killed $lr, 14, $noreg + ; CHECK: $r4 = tMOVr killed $lr, 14 [always], $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 @@ -165,17 +165,17 @@ ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14, $noreg + ; CHECK: $lr = tMOVr $r4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4) ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir @@ -132,27 +132,27 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.1) - ; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0, killed $cpsr + ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 [always], $noreg :: (load 4 from %fixed-stack.1) + ; CHECK: t2CMPri renamable $r12, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.3, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8) + ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr - ; CHECK: $r4 = tMOVr killed $lr, 14, $noreg + ; CHECK: $r4 = tMOVr killed $lr, 14 [always], $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 @@ -165,17 +165,17 @@ ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14, $noreg + ; CHECK: $lr = tMOVr $r4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, killed renamable $vpr ; CHECK: renamable $r5 = MVE_VSTRWU32_post renamable $q0, killed renamable $r5, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.cast.e, align 4) ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir @@ -132,27 +132,27 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.1) - ; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0, killed $cpsr + ; CHECK: renamable $r12 = t2LDRi12 $sp, 20, 14 [always], $noreg :: (load 4 from %fixed-stack.1) + ; CHECK: t2CMPri renamable $r12, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.3, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = tLDRspi $sp, 4, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8) + ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr - ; CHECK: $r4 = tMOVr killed $lr, 14, $noreg + ; CHECK: $r4 = tMOVr killed $lr, 14 [always], $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r12 @@ -164,9 +164,9 @@ ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) - ; CHECK: $lr = tMOVr $r4, 14, $noreg - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: $lr = tMOVr $r4, 14 [always], $noreg + ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, renamable $vpr, undef renamable $q1 @@ -175,7 +175,7 @@ ; CHECK: dead renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir @@ -130,26 +130,26 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 0, killed $cpsr + ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8) + ; CHECK: t2CMPri renamable $r12, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.4, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg - ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 [always], $noreg, $noreg ; CHECK: dead $lr = t2DLS renamable $r5 - ; CHECK: $r4 = tMOVr killed $r5, 14, $noreg + ; CHECK: $r4 = tMOVr killed $r5, 14 [always], $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 @@ -162,20 +162,20 @@ ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv1820, align 2) ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14, $noreg + ; CHECK: $lr = tMOVr $r4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.middle.block: ; CHECK: liveins: $q0 ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: bb.4: - ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir @@ -132,26 +132,26 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.4(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) - ; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 0, killed $cpsr + ; CHECK: renamable $r12 = t2LDRi12 $sp, 16, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8) + ; CHECK: t2CMPri renamable $r12, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.4, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2ADDri renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $lr = t2BICri killed renamable $lr, 3, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg - ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg + ; CHECK: renamable $lr = t2SUBri killed renamable $lr, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14 [always], $noreg, $noreg ; CHECK: dead $lr = t2DLS renamable $r5 - ; CHECK: $r4 = tMOVr killed $r5, 14, $noreg + ; CHECK: $r4 = tMOVr killed $r5, 14 [always], $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r12 @@ -163,20 +163,20 @@ ; CHECK: renamable $r0, renamable $q4 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2) ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $q2 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q4, 0, $noreg, undef renamable $q2 - ; CHECK: $lr = tMOVr $r4, 14, $noreg + ; CHECK: $lr = tMOVr $r4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.middle.block: ; CHECK: liveins: $q0 ; CHECK: renamable $r0 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 ; CHECK: bb.4: - ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 + ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain.mir @@ -98,22 +98,22 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg - ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r3, 4, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2MOVi 4, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r3, 4, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: $r1 = t2ADDri renamable $r0, 3, 11, $noreg, $noreg, implicit $itstate - ; CHECK: $r3 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit renamable $r12, implicit $itstate - ; CHECK: $r12 = t2LSLri renamable $r3, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg - ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg + ; CHECK: $r1 = t2ADDri renamable $r0, 3, 11 [less], $noreg, $noreg, implicit $itstate + ; CHECK: $r3 = t2LSLri renamable $r2, 1, 11 [less], $cpsr, $noreg, implicit renamable $r12, implicit $itstate + ; CHECK: $r12 = t2LSLri renamable $r3, 1, 11 [less], killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate + ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.do.body (align 4): @@ -122,11 +122,11 @@ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg - ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.do.end: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.3 (align 16): ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-itercount.mir @@ -99,21 +99,21 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg - ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg - ; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2MOVi 4, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 renamable $r3, 4, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate - ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate - ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg - ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg + ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 [less], $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate + ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 [less], killed $cpsr, $noreg, implicit killed renamable $r12, implicit killed $itstate + ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.do.body (align 4): @@ -122,11 +122,11 @@ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg - ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.do.end: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.3 (align 16): ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-random.mir @@ -100,21 +100,21 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14, $noreg - ; CHECK: renamable $r12 = t2MOVi 4, 14, $noreg, $noreg - ; CHECK: tCMPi8 renamable $r3, 4, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r3, dead $cpsr = tLSLri renamable $r2, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2MOVi 4, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 renamable $r3, 4, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11, $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate - ; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11, killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate - ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14, $noreg, $noreg - ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14, $noreg, $noreg - ; CHECK: renamable $r2 = tLEApcrel %const.0, 14, $noreg + ; CHECK: $r12 = t2LSLri renamable $r2, 1, 11 [less], $cpsr, $noreg, implicit killed renamable $r12, implicit $itstate + ; CHECK: $r0 = t2ADDri killed renamable $r0, 42, 11 [less], killed $cpsr, $noreg, implicit killed renamable $r0, implicit killed $itstate + ; CHECK: renamable $r2 = t2RSBrs killed renamable $r12, killed renamable $r2, 10, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDri killed renamable $r2, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r2 = tLEApcrel %const.0, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg :: (load 16 from constant-pool) ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.do.body (align 4): @@ -123,11 +123,11 @@ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VLDRWU32 renamable $r0, 0, 0, $noreg ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMULf32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: MVE_VSTRWU32 killed renamable $q1, renamable $r1, 0, 0, killed $noreg - ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 16, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = nuw tADDi8 killed renamable $r1, 16, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.do.end: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.3 (align 16): ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 16 bb.0.entry: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir @@ -224,7 +224,7 @@ ; CHECK: bb.0.bb: ; CHECK: successors: %bb.8(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -235,112 +235,112 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 - ; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.8, 0, killed $cpsr + ; CHECK: tCMPi8 renamable $r3, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.8, 0 [equal], killed $cpsr ; CHECK: bb.1.bb4: ; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg - ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr - ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: tBcc %bb.3, 2, killed $cpsr + ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 [always], $noreg + ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r4, 3, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: tBcc %bb.3, 2 [highersame], killed $cpsr ; CHECK: bb.2: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tB %bb.5, 14, $noreg + ; CHECK: renamable $r8 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.5, 14 [always], $noreg ; CHECK: bb.3.bb12: ; CHECK: successors: %bb.4(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg - ; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg - ; CHECK: $r12 = tMOVr killed $r3, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg + ; CHECK: renamable $r8 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 [always], $noreg, $noreg + ; CHECK: $r12 = tMOVr killed $r3, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: bb.4.bb28: ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r8, $r12 - ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) - ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418) - ; CHECK: $lr = tMOVr killed $r12, 14, $noreg - ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg - ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg - ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219) - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg - ; CHECK: $r12 = tMOVr $lr, 14, $noreg - ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14, $noreg - ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14, $noreg :: (store 4 into %ir.scevgep219) - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg - ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14, $noreg :: (load 4 from %ir.scevgep11) - ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14, $noreg :: (load 4 from %ir.scevgep14) - ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14, $noreg, $noreg - ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg - ; CHECK: $r11 = t2ADDri $r6, 4, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14, $noreg - ; CHECK: t2LDMIA killed $r11, 14, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14, $noreg :: (store 4 into %ir.scevgep9) - ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14, $noreg :: (load 4 from %ir.scevgep12) - ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14, $noreg :: (load 4 from %ir.scevgep10) - ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14, $noreg, $noreg - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14, $noreg :: (store 4 into %ir.scevgep8) - ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14, $noreg :: (load 4 from %ir.scevgep5) - ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14, $noreg :: (load 4 from %ir.scevgep3) - ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14, $noreg - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14, $noreg :: (store 4 into %ir.scevgep1) - ; CHECK: t2CMPri killed $lr, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.4, 1, killed $cpsr - ; CHECK: tB %bb.5, 14, $noreg + ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep617) + ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep418) + ; CHECK: $lr = tMOVr killed $r12, 14 [always], $noreg + ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 [always], $noreg + ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep219) + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, $noreg + ; CHECK: $r12 = tMOVr $lr, 14 [always], $noreg + ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 [always], $noreg + ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 [always], $noreg :: (store 4 into %ir.scevgep219) + ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep11) + ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep14) + ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 [always], $noreg, $noreg + ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 [always], $noreg + ; CHECK: $r11 = t2ADDri $r6, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 [always], $noreg + ; CHECK: t2LDMIA killed $r11, 14 [always], $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 [always], $noreg :: (store 4 into %ir.scevgep9) + ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 [always], $noreg :: (load 4 from %ir.scevgep12) + ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 [always], $noreg :: (load 4 from %ir.scevgep10) + ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 [always], $noreg :: (store 4 into %ir.scevgep8) + ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 [always], $noreg :: (load 4 from %ir.scevgep5) + ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 [always], $noreg :: (load 4 from %ir.scevgep3) + ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 [always], $noreg + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 [always], $noreg :: (store 4 into %ir.scevgep1) + ; CHECK: t2CMPri killed $lr, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.4, 1 [notequal], killed $cpsr + ; CHECK: tB %bb.5, 14 [always], $noreg ; CHECK: bb.5.bb13: ; CHECK: successors: %bb.8(0x30000000), %bb.6(0x50000000) ; CHECK: liveins: $r0, $r1, $r2, $r8 - ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) ; CHECK: tCBZ $r5, %bb.8 ; CHECK: bb.6.bb16: ; CHECK: successors: %bb.8(0x40000000), %bb.7(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 - ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp17) - ; CHECK: tCMPi8 renamable $r5, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp19) - ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp22) - ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14, $noreg - ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14, $noreg :: (store 4 into %ir.tmp22) - ; CHECK: tBcc %bb.8, 0, killed $cpsr + ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp17) + ; CHECK: tCMPi8 renamable $r5, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp19) + ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp22) + ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 [always], $noreg :: (store 4 into %ir.tmp22) + ; CHECK: tBcc %bb.8, 0 [equal], killed $cpsr ; CHECK: bb.7.bb57: ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 - ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r5, 2, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp58) - ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp60) - ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14, $noreg, $noreg - ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp63) - ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14, $noreg - ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp63) - ; CHECK: tBcc %bb.9, 1, killed $cpsr + ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r5, 2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp58) + ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp60) + ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 [always], $noreg, $noreg + ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp63) + ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 [always], $noreg :: (store 4 into %ir.tmp63) + ; CHECK: tBcc %bb.9, 1 [notequal], killed $cpsr ; CHECK: bb.8.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc ; CHECK: bb.9.bb68: ; CHECK: liveins: $r0, $r1, $r2, $r8 - ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14, $noreg, $noreg - ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp69) - ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp71) - ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp74) - ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp74) - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 [always], $noreg, $noreg + ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp69) + ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp71) + ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp74) + ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 [always], $noreg :: (store 4 into %ir.tmp74) + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc bb.0.bb: successors: %bb.8(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir @@ -225,7 +225,7 @@ ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -236,122 +236,122 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: tCBZ $r3, %bb.3 ; CHECK: bb.1.bb4: ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg - ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr - ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: tBcc %bb.4, 2, killed $cpsr + ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 [always], $noreg + ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r4, 3, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: tBcc %bb.4, 2 [highersame], killed $cpsr ; CHECK: bb.2: ; CHECK: successors: %bb.6(0x80000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tB %bb.6, 14, $noreg + ; CHECK: renamable $r8 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.6, 14 [always], $noreg ; CHECK: bb.3: ; CHECK: successors: %bb.12(0x80000000) - ; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tB %bb.12, 14, $noreg + ; CHECK: renamable $lr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.12, 14 [always], $noreg ; CHECK: bb.4.bb12: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg - ; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg + ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg + ; CHECK: renamable $r8 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $r3 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: bb.5.bb28: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8 - ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) - ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418) - ; CHECK: dead $r12 = tMOVr $lr, 14, $noreg - ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg - ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg - ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219) - ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14, $noreg - ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14, $noreg :: (store 4 into %ir.scevgep219) - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg - ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14, $noreg :: (load 4 from %ir.scevgep11) - ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14, $noreg :: (load 4 from %ir.scevgep14) - ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14, $noreg, $noreg - ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg - ; CHECK: $r11 = t2ADDri $r6, 4, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14, $noreg - ; CHECK: t2LDMIA killed $r11, 14, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14, $noreg :: (store 4 into %ir.scevgep9) - ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14, $noreg :: (load 4 from %ir.scevgep12) - ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14, $noreg :: (load 4 from %ir.scevgep10) - ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14, $noreg, $noreg - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14, $noreg :: (store 4 into %ir.scevgep8) - ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14, $noreg :: (load 4 from %ir.scevgep5) - ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14, $noreg :: (load 4 from %ir.scevgep3) - ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14, $noreg - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14, $noreg :: (store 4 into %ir.scevgep1) + ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep617) + ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep418) + ; CHECK: dead $r12 = tMOVr $lr, 14 [always], $noreg + ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 [always], $noreg + ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep219) + ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 [always], $noreg + ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 [always], $noreg :: (store 4 into %ir.scevgep219) + ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep11) + ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep14) + ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 [always], $noreg, $noreg + ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 [always], $noreg + ; CHECK: $r11 = t2ADDri $r6, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 [always], $noreg + ; CHECK: t2LDMIA killed $r11, 14 [always], $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 [always], $noreg :: (store 4 into %ir.scevgep9) + ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 [always], $noreg :: (load 4 from %ir.scevgep12) + ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 [always], $noreg :: (load 4 from %ir.scevgep10) + ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 [always], $noreg :: (store 4 into %ir.scevgep8) + ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 [always], $noreg :: (load 4 from %ir.scevgep5) + ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 [always], $noreg :: (load 4 from %ir.scevgep3) + ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 [always], $noreg + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 [always], $noreg :: (store 4 into %ir.scevgep1) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 ; CHECK: bb.6.bb13: ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8 - ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) ; CHECK: tCBZ $r5, %bb.12 ; CHECK: bb.7.bb16: ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 - ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp17) - ; CHECK: tCMPi8 renamable $r5, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp19) - ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp22) - ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14, $noreg - ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14, $noreg :: (store 4 into %ir.tmp22) - ; CHECK: tBcc %bb.9, 1, killed $cpsr + ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp17) + ; CHECK: tCMPi8 renamable $r5, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp19) + ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp22) + ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 [always], $noreg :: (store 4 into %ir.tmp22) + ; CHECK: tBcc %bb.9, 1 [notequal], killed $cpsr ; CHECK: bb.8: ; CHECK: successors: %bb.12(0x80000000) - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: tB %bb.12, 14, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.12, 14 [always], $noreg ; CHECK: bb.9.bb57: ; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 - ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r5, 2, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp58) - ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp60) - ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14, $noreg, $noreg - ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp63) - ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14, $noreg - ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp63) - ; CHECK: tBcc %bb.11, 1, killed $cpsr + ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r5, 2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp58) + ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp60) + ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 [always], $noreg, $noreg + ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp63) + ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 [always], $noreg :: (store 4 into %ir.tmp63) + ; CHECK: tBcc %bb.11, 1 [notequal], killed $cpsr ; CHECK: bb.10: ; CHECK: successors: %bb.12(0x80000000) - ; CHECK: renamable $lr = t2MOVi 2, 14, $noreg, $noreg - ; CHECK: tB %bb.12, 14, $noreg + ; CHECK: renamable $lr = t2MOVi 2, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.12, 14 [always], $noreg ; CHECK: bb.11.bb68: ; CHECK: successors: %bb.12(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r8 - ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 3, 14, $noreg, $noreg - ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp69) - ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp71) - ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp74) - ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp74) + ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp69) + ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp71) + ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp74) + ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 [always], $noreg :: (store 4 into %ir.tmp74) ; CHECK: bb.12.bb27: ; CHECK: liveins: $lr - ; CHECK: $r0 = tMOVr killed $lr, 14, $noreg - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0 + ; CHECK: $r0 = tMOVr killed $lr, 14 [always], $noreg + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0 bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir @@ -225,7 +225,7 @@ ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -236,121 +236,121 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40 ; CHECK: tCBZ $r3, %bb.3 ; CHECK: bb.1.bb4: ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg - ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr - ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: tBcc %bb.4, 2, killed $cpsr + ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 [always], $noreg + ; CHECK: renamable $r7 = t2ANDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r4, 3, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tSTRspi killed renamable $r7, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: tBcc %bb.4, 2 [highersame], killed $cpsr ; CHECK: bb.2: ; CHECK: successors: %bb.6(0x80000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tB %bb.6, 14, $noreg + ; CHECK: renamable $r8 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.6, 14 [always], $noreg ; CHECK: bb.3: ; CHECK: successors: %bb.12(0x80000000) - ; CHECK: renamable $lr = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tB %bb.12, 14, $noreg + ; CHECK: renamable $lr = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.12, 14 [always], $noreg ; CHECK: bb.4.bb12: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg - ; CHECK: renamable $r8 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14, $noreg, $noreg + ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg + ; CHECK: renamable $r8 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r4, killed renamable $r3, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $r3 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: bb.5.bb28: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r8 - ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14, $noreg :: (load 4 from %ir.scevgep617) - ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14, $noreg :: (load 4 from %ir.scevgep418) - ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14, $noreg, $noreg - ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14, $noreg - ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14, $noreg :: (load 4 from %ir.scevgep219) - ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14, $noreg - ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14, $noreg :: (store 4 into %ir.scevgep219) - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg - ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14, $noreg :: (load 4 from %ir.scevgep11) - ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14, $noreg :: (load 4 from %ir.scevgep14) - ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14, $noreg, $noreg - ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg - ; CHECK: $r11 = t2ADDri $r6, 4, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14, $noreg - ; CHECK: t2LDMIA killed $r11, 14, $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14, $noreg :: (store 4 into %ir.scevgep9) - ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14, $noreg :: (load 4 from %ir.scevgep12) - ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14, $noreg :: (load 4 from %ir.scevgep10) - ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14, $noreg, $noreg - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14, $noreg :: (store 4 into %ir.scevgep8) - ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14, $noreg :: (load 4 from %ir.scevgep5) - ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14, $noreg :: (load 4 from %ir.scevgep3) - ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14, $noreg - ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14, $noreg - ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14, $noreg :: (store 4 into %ir.scevgep1) + ; CHECK: renamable $r5 = tLDRr renamable $r1, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep617) + ; CHECK: renamable $r7, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r6 = tLDRr renamable $r2, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep418) + ; CHECK: renamable $r8 = nuw t2ADDri killed renamable $r8, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5, dead $cpsr = tEOR killed renamable $r5, killed renamable $r6, 14 [always], $noreg + ; CHECK: renamable $r6 = tLDRr renamable $r0, $r3, 14 [always], $noreg :: (load 4 from %ir.scevgep219) + ; CHECK: renamable $r5 = nsw tADDhirr killed renamable $r5, killed renamable $r6, 14 [always], $noreg + ; CHECK: tSTRr killed renamable $r5, renamable $r0, $r3, 14 [always], $noreg :: (store 4 into %ir.scevgep219) + ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r4 = tLDRi renamable $r7, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep11) + ; CHECK: renamable $r6 = tLDRi renamable $r5, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep14) + ; CHECK: renamable $r9 = t2EORrr killed renamable $r4, killed renamable $r6, 14 [always], $noreg, $noreg + ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 [always], $noreg + ; CHECK: $r11 = t2ADDri $r6, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 16, 14 [always], $noreg + ; CHECK: t2LDMIA killed $r11, 14 [always], $noreg, def $r4, def $r10, def $r11 :: (load 4 from %ir.scevgep9), (load 4 from %ir.scevgep8), (load 4 from %ir.scevgep1) + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r9, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, renamable $r6, 1, 14 [always], $noreg :: (store 4 into %ir.scevgep9) + ; CHECK: renamable $r9 = t2LDRi12 renamable $r5, 8, 14 [always], $noreg :: (load 4 from %ir.scevgep12) + ; CHECK: renamable $r4 = tLDRi renamable $r7, 2, 14 [always], $noreg :: (load 4 from %ir.scevgep10) + ; CHECK: renamable $r4 = t2EORrr killed renamable $r4, killed renamable $r9, 14 [always], $noreg, $noreg + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r10, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, renamable $r6, 2, 14 [always], $noreg :: (store 4 into %ir.scevgep8) + ; CHECK: renamable $r4 = tLDRi killed renamable $r5, 3, 14 [always], $noreg :: (load 4 from %ir.scevgep5) + ; CHECK: renamable $r5 = tLDRi killed renamable $r7, 3, 14 [always], $noreg :: (load 4 from %ir.scevgep3) + ; CHECK: renamable $r4, dead $cpsr = tEOR killed renamable $r4, killed renamable $r5, 14 [always], $noreg + ; CHECK: renamable $r4 = nsw tADDhirr killed renamable $r4, killed renamable $r11, 14 [always], $noreg + ; CHECK: tSTRi killed renamable $r4, killed renamable $r6, 3, 14 [always], $noreg :: (store 4 into %ir.scevgep1) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.5 ; CHECK: bb.6.bb13: ; CHECK: successors: %bb.12(0x30000000), %bb.7(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r8 - ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: renamable $r5 = tLDRspi $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) ; CHECK: tCBZ $r5, %bb.12 ; CHECK: bb.7.bb16: ; CHECK: successors: %bb.8(0x40000000), %bb.9(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r5, $r8 - ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp17) - ; CHECK: tCMPi8 renamable $r5, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp19) - ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14, $noreg :: (load 4 from %ir.tmp22) - ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14, $noreg - ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14, $noreg :: (store 4 into %ir.tmp22) - ; CHECK: tBcc %bb.9, 1, killed $cpsr + ; CHECK: renamable $lr = t2LDRs renamable $r1, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp17) + ; CHECK: tCMPi8 renamable $r5, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r3 = t2LDRs renamable $r2, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp19) + ; CHECK: renamable $lr = t2EORrr killed renamable $lr, killed renamable $r3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2LDRs renamable $r0, renamable $r8, 2, 14 [always], $noreg :: (load 4 from %ir.tmp22) + ; CHECK: renamable $r3 = nsw tADDhirr killed renamable $r3, killed renamable $lr, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r3, renamable $r0, renamable $r8, 2, 14 [always], $noreg :: (store 4 into %ir.tmp22) + ; CHECK: tBcc %bb.9, 1 [notequal], killed $cpsr ; CHECK: bb.8: ; CHECK: successors: %bb.12(0x80000000) - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: tB %bb.12, 14, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.12, 14 [always], $noreg ; CHECK: bb.9.bb57: ; CHECK: successors: %bb.10(0x40000000), %bb.11(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r5, $r8 - ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r5, 2, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp58) - ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp60) - ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14, $noreg, $noreg - ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp63) - ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14, $noreg - ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp63) - ; CHECK: tBcc %bb.11, 1, killed $cpsr + ; CHECK: renamable $r3 = nuw t2ADDri renamable $r8, 1, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r5, 2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r7 = t2LDRs renamable $r1, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp58) + ; CHECK: renamable $r6 = t2LDRs renamable $r2, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp60) + ; CHECK: renamable $r7 = t2EORrr killed renamable $r7, killed renamable $r6, 14 [always], $noreg, $noreg + ; CHECK: renamable $r6 = t2LDRs renamable $r0, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp63) + ; CHECK: renamable $r7 = nsw tADDhirr killed renamable $r7, killed renamable $r6, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r7, renamable $r0, killed renamable $r3, 2, 14 [always], $noreg :: (store 4 into %ir.tmp63) + ; CHECK: tBcc %bb.11, 1 [notequal], killed $cpsr ; CHECK: bb.10: ; CHECK: successors: %bb.12(0x80000000) - ; CHECK: renamable $lr = t2MOVi 2, 14, $noreg, $noreg - ; CHECK: tB %bb.12, 14, $noreg + ; CHECK: renamable $lr = t2MOVi 2, 14 [always], $noreg, $noreg + ; CHECK: tB %bb.12, 14 [always], $noreg ; CHECK: bb.11.bb68: ; CHECK: successors: %bb.12(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r8 - ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 3, 14, $noreg, $noreg - ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp69) - ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp71) - ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14, $noreg :: (load 4 from %ir.tmp74) - ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14, $noreg :: (store 4 into %ir.tmp74) + ; CHECK: renamable $r3 = nuw t2ADDri killed renamable $r8, 2, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r1 = t2LDRs killed renamable $r1, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp69) + ; CHECK: renamable $r2 = t2LDRs killed renamable $r2, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp71) + ; CHECK: renamable $r1, dead $cpsr = tEOR killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: renamable $r2 = t2LDRs renamable $r0, renamable $r3, 2, 14 [always], $noreg :: (load 4 from %ir.tmp74) + ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: t2STRs killed renamable $r1, killed renamable $r0, killed renamable $r3, 2, 14 [always], $noreg :: (store 4 into %ir.tmp74) ; CHECK: bb.12.bb27: ; CHECK: liveins: $lr - ; CHECK: $r0 = tMOVr killed $lr, 14, $noreg - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0 + ; CHECK: $r0 = tMOVr killed $lr, 14 [always], $noreg + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $r0 bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir @@ -208,69 +208,69 @@ ; CHECK: DBG_VALUE $r1, $noreg, !24, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r2, $noreg, !25, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r3, $noreg, !26, !DIExpression(), debug-location !32 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg + ; CHECK: $r7 = frame-setup tADDrSPi $sp, 3, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10 + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r8, killed $r9, killed $r10 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 - ; CHECK: $r5 = tMOVr killed $r2, 14, $noreg + ; CHECK: $r5 = tMOVr killed $r2, 14 [always], $noreg ; CHECK: DBG_VALUE $r5, $noreg, !25, !DIExpression(), debug-location !32 - ; CHECK: $r2, dead $cpsr = tMOVi8 0, 14, $noreg, debug-location !33 - ; CHECK: $r8 = tMOVr killed $r3, 14, $noreg + ; CHECK: $r2, dead $cpsr = tMOVi8 0, 14 [always], $noreg, debug-location !33 + ; CHECK: $r8 = tMOVr killed $r3, 14 [always], $noreg ; CHECK: DBG_VALUE $r8, $noreg, !26, !DIExpression(), debug-location !32 - ; CHECK: $r9 = tMOVr $r1, 14, $noreg + ; CHECK: $r9 = tMOVr $r1, 14 [always], $noreg ; CHECK: DBG_VALUE $r9, $noreg, !24, !DIExpression(), debug-location !32 - ; CHECK: $r10 = tMOVr $r0, 14, $noreg + ; CHECK: $r10 = tMOVr $r0, 14 [always], $noreg ; CHECK: DBG_VALUE 0, $noreg, !29, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $r10, $noreg, !23, !DIExpression(), debug-location !32 - ; CHECK: tBL 14, $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33 + ; CHECK: tBL 14 [always], $noreg, @get_input, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit-def $sp, implicit-def dead $r0, debug-location !33 ; CHECK: DBG_VALUE 0, $noreg, !30, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE $noreg, $noreg, !28, !DIExpression(), debug-location !32 - ; CHECK: t2CMPri renamable $r10, 1, 14, $noreg, implicit-def $cpsr, debug-location !37 - ; CHECK: tBcc %bb.5, 11, killed $cpsr, debug-location !37 + ; CHECK: t2CMPri renamable $r10, 1, 14 [always], $noreg, implicit-def $cpsr, debug-location !37 + ; CHECK: tBcc %bb.5, 11 [less], killed $cpsr, debug-location !37 ; CHECK: bb.1.for.cond1.preheader.us.preheader: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r5, $r8, $r9, $r10 - ; CHECK: renamable $r12 = t2LSLri renamable $r10, 1, 14, $noreg, $noreg, debug-location !37 - ; CHECK: renamable $r1, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r12 = t2LSLri renamable $r10, 1, 14 [always], $noreg, $noreg, debug-location !37 + ; CHECK: renamable $r1, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: bb.2.for.cond1.preheader.us: ; CHECK: successors: %bb.3(0x80000000) ; CHECK: liveins: $r1, $r5, $r8, $r9, $r10, $r12 ; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32 ; CHECK: DBG_VALUE 0, $noreg, !31, !DIExpression(), debug-location !32 - ; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14, $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us) - ; CHECK: $r3 = tMOVr $r5, 14, $noreg, debug-location !32 - ; CHECK: $r0 = tMOVr $r8, 14, $noreg, debug-location !32 + ; CHECK: renamable $r2 = t2LDRs renamable $r9, renamable $r1, 2, 14 [always], $noreg, debug-location !41 :: (load 4 from %ir.arrayidx7.us) + ; CHECK: $r3 = tMOVr $r5, 14 [always], $noreg, debug-location !32 + ; CHECK: $r0 = tMOVr $r8, 14 [always], $noreg, debug-location !32 ; CHECK: $lr = t2DLS renamable $r10, debug-location !32 ; CHECK: bb.3.for.body3.us: ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r5, $r8, $r9, $r10, $r12 ; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(), debug-location !32 - ; CHECK: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14, $noreg, debug-location !43 :: (load 2 from %ir.lsr.iv5) - ; CHECK: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14, $noreg, debug-location !44 :: (load 2 from %ir.lsr.iv1) - ; CHECK: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14, $noreg, debug-location !41 + ; CHECK: renamable $r6, renamable $r3 = t2LDRSH_POST killed renamable $r3, 2, 14 [always], $noreg, debug-location !43 :: (load 2 from %ir.lsr.iv5) + ; CHECK: renamable $r4, renamable $r0 = t2LDRSH_POST killed renamable $r0, 2, 14 [always], $noreg, debug-location !44 :: (load 2 from %ir.lsr.iv1) + ; CHECK: renamable $r2 = nsw t2SMLABB killed renamable $r4, killed renamable $r6, killed renamable $r2, 14 [always], $noreg, debug-location !41 ; CHECK: DBG_VALUE $noreg, $noreg, !31, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !32 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3, debug-location !42 ; CHECK: bb.4.for.cond1.for.inc9_crit_edge.us: ; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000) ; CHECK: liveins: $r1, $r2, $r5, $r8, $r9, $r10, $r12 - ; CHECK: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14, $noreg, debug-location !41 :: (store 4 into %ir.8) - ; CHECK: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14, $noreg, debug-location !49 + ; CHECK: t2STRs killed renamable $r2, renamable $r9, renamable $r1, 2, 14 [always], $noreg, debug-location !41 :: (store 4 into %ir.8) + ; CHECK: renamable $r1, dead $cpsr = nuw nsw tADDi8 killed renamable $r1, 1, 14 [always], $noreg, debug-location !49 ; CHECK: DBG_VALUE $r1, $noreg, !30, !DIExpression(), debug-location !32 - ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14, $noreg, debug-location !37 - ; CHECK: tCMPhir renamable $r1, renamable $r10, 14, $noreg, implicit-def $cpsr, debug-location !37 - ; CHECK: tBcc %bb.2, 1, killed $cpsr, debug-location !37 + ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r12, 14 [always], $noreg, debug-location !37 + ; CHECK: tCMPhir renamable $r1, renamable $r10, 14 [always], $noreg, implicit-def $cpsr, debug-location !37 + ; CHECK: tBcc %bb.2, 1 [notequal], killed $cpsr, debug-location !37 ; CHECK: bb.5.for.end11: - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10, debug-location !52 - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52 + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r8, def $r9, def $r10, debug-location !52 + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !52 bb.0.entry: successors: %bb.1(0x50000000), %bb.5(0x30000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir @@ -216,7 +216,7 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x50000000), %bb.12(0x30000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -8 @@ -226,64 +226,64 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -32 - ; CHECK: tCMPi8 renamable $r0, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.12, 11, killed $cpsr + ; CHECK: tCMPi8 renamable $r0, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.12, 11 [less], killed $cpsr ; CHECK: bb.1.for.body.i.preheader: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r5 = tMOVr killed $r2, 14, $noreg - ; CHECK: $r8 = tMOVr killed $r3, 14, $noreg - ; CHECK: $r4 = tMOVr $r1, 14, $noreg - ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: $r5 = tMOVr killed $r2, 14 [always], $noreg + ; CHECK: $r8 = tMOVr killed $r3, 14 [always], $noreg + ; CHECK: $r4 = tMOVr $r1, 14 [always], $noreg + ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: renamable $r2 = IMPLICIT_DEF - ; CHECK: $r10 = tMOVr $r0, 14, $noreg + ; CHECK: $r10 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = t2DLS killed renamable $r0 ; CHECK: bb.2.for.body.i: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10 - ; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.lsr.iv15) - ; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14, $noreg - ; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.lsr.iv15) + ; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: tCMPi8 renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr - ; CHECK: tCMPi8 killed renamable $r3, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 killed renamable $r3, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr - ; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14, $noreg, $noreg + ; CHECK: tCMPi8 renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 [always], $noreg, $noreg ; CHECK: t2IT 12, 8, implicit-def $itstate - ; CHECK: $r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate - ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14, $noreg + ; CHECK: $r2 = tMOVi8 $noreg, 0, 12 [greater], killed $cpsr, implicit killed renamable $r2, implicit killed $itstate + ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 [always], $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.c.exit: ; CHECK: successors: %bb.4(0x50000000), %bb.14(0x30000000) ; CHECK: liveins: $r4, $r5, $r6, $r8, $r10 - ; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14, $noreg - ; CHECK: tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 - ; CHECK: $r12 = tMOVr killed $r0, 14, $noreg - ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: t2CMPri $r10, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.14, 11, killed $cpsr + ; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14 [always], $noreg + ; CHECK: tBL 14 [always], $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 + ; CHECK: $r12 = tMOVr killed $r0, 14 [always], $noreg + ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: t2CMPri $r10, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.14, 11 [less], killed $cpsr ; CHECK: bb.4.for.cond4.preheader.us.preheader: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12 - ; CHECK: renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg - ; CHECK: $lr = tMOVr $r10, 14, $noreg - ; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg - ; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg + ; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 [always], $noreg, $noreg + ; CHECK: $lr = tMOVr $r10, 14 [always], $noreg + ; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 [always], $noreg + ; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg - ; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg - ; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg + ; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 [always], $noreg + ; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 [always], $noreg, $noreg ; CHECK: bb.5.for.cond4.preheader.us: ; CHECK: successors: %bb.6(0x80000000) ; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 - ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load 4 from %ir.arrayidx12.us) + ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 [always], $noreg :: (load 4 from %ir.arrayidx12.us) ; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 - ; CHECK: $r2 = tMOVr killed $lr, 14, $noreg - ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg - ; CHECK: $r6 = tMOVr $r5, 14, $noreg - ; CHECK: $r1 = tMOVr $r8, 14, $noreg + ; CHECK: $r2 = tMOVr killed $lr, 14 [always], $noreg + ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 [always], $noreg + ; CHECK: $r6 = tMOVr $r5, 14 [always], $noreg + ; CHECK: $r1 = tMOVr $r8, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: bb.6.vector.body: ; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000) @@ -298,62 +298,62 @@ ; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000) ; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg - ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg + ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr - ; CHECK: $lr = tMOVr $r10, 14, $noreg + ; CHECK: $lr = tMOVr $r10, 14 [always], $noreg ; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg - ; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store 4 into %ir.27) - ; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg - ; CHECK: tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.5, 1, killed $cpsr + ; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 [always], $noreg :: (store 4 into %ir.27) + ; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 [always], $noreg + ; CHECK: tCMPhir renamable $r7, $r10, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.5, 1 [notequal], killed $cpsr ; CHECK: bb.8.for.end16: ; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000) ; CHECK: liveins: $lr, $r4, $r12 - ; CHECK: t2CMPri renamable $lr, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.13, 11, killed $cpsr + ; CHECK: t2CMPri renamable $lr, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.13, 11 [less], killed $cpsr ; CHECK: bb.9.for.body.i57.preheader: ; CHECK: successors: %bb.10(0x80000000) ; CHECK: liveins: $lr, $r4, $r12 - ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: renamable $r1 = IMPLICIT_DEF ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.10.for.body.i57: ; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r4, $r12 - ; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14, $noreg :: (load 4 from %ir.lsr.iv1) - ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14, $noreg - ; CHECK: tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 [always], $noreg :: (load 4 from %ir.lsr.iv1) + ; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 [always], $noreg + ; CHECK: tCMPi8 renamable $r1, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr - ; CHECK: tCMPi8 killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 killed renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr - ; CHECK: tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg + ; CHECK: tCMPi8 renamable $r1, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 [always], $noreg, $noreg ; CHECK: t2IT 12, 8, implicit-def $itstate - ; CHECK: $r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate - ; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg + ; CHECK: $r1 = tMOVi8 $noreg, 0, 12 [greater], killed $cpsr, implicit killed renamable $r1, implicit killed $itstate + ; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 [always], $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10 ; CHECK: bb.11.c.exit59.loopexit: ; CHECK: successors: %bb.14(0x80000000) ; CHECK: liveins: $r0, $r12 - ; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14, $noreg - ; CHECK: tB %bb.14, 14, $noreg + ; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14 [always], $noreg + ; CHECK: tB %bb.14, 14 [always], $noreg ; CHECK: bb.12.c.exit.thread: ; CHECK: successors: %bb.14(0x80000000) - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 - ; CHECK: $r12 = tMOVr killed $r0, 14, $noreg - ; CHECK: tB %bb.14, 14, $noreg + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBL 14 [always], $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0 + ; CHECK: $r12 = tMOVr killed $r0, 14 [always], $noreg + ; CHECK: tB %bb.14, 14 [always], $noreg ; CHECK: bb.13: ; CHECK: successors: %bb.14(0x80000000) ; CHECK: liveins: $r12 - ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: bb.14.c.exit59: ; CHECK: liveins: $r7, $r12 - ; CHECK: $r0 = tMOVr killed $r7, 14, $noreg - ; CHECK: $r1 = tMOVr killed $r12, 14, $noreg - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr - ; CHECK: tTAILJMPdND @crc16, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1 + ; CHECK: $r0 = tMOVr killed $r7, 14 [always], $noreg + ; CHECK: $r1 = tMOVr killed $r12, 14 [always], $noreg + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr + ; CHECK: tTAILJMPdND @crc16, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1 bb.0.entry: successors: %bb.1(0x50000000), %bb.12(0x30000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dls.mir @@ -87,22 +87,22 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: $lr = t2DLS killed $r0 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg ; CHECK: bb.1.while.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep2) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.while.end: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir @@ -101,30 +101,30 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: tPOP_RET 0 [equal], killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2LSRri killed renamable $r3, 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir @@ -106,31 +106,31 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: $r12 = t2MOVr killed $r3, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg + ; CHECK: tPOP_RET 0 [equal], killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK: $r12 = t2MOVr killed $r3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 [always], $noreg, $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir @@ -106,31 +106,35 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrs killed renamable $r12, renamable $r3, 11, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate - ; CHECK: $r12 = t2MOVr killed $r3, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14, $noreg, $noreg + ; CHECK: tPOP_RET 0 [equal], killed $cpsr, def $r4, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2MOVi 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = nuw t2ADDrs killed renamable $r12, renamable $r3, 11, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: dead renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: $r12 = t2MOVr killed $r3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 1, 14 [always], $noreg, $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r12 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r1, renamable $r3, 14 [always], $noreg ; CHECK: renamable $q0 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep45, align 1) - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 4, 14 [always], $noreg ; CHECK: renamable $q1 = MVE_VLDRBU32 killed renamable $r4, 0, 0, $noreg :: (load 4 from %ir.scevgep23, align 1) ; CHECK: renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir @@ -348,26 +348,26 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.6(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg + ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14, $noreg + ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 - ; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 0, killed $cpsr + ; CHECK: tCMPi8 renamable $r3, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.6, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r8 = tMOVr $r0, 14, $noreg - ; CHECK: $r5 = tMOVr $r2, 14, $noreg - ; CHECK: $r4 = tMOVr $r3, 14, $noreg - ; CHECK: $r6 = tMOVr $r1, 14, $noreg + ; CHECK: $r8 = tMOVr $r0, 14 [always], $noreg + ; CHECK: $r5 = tMOVr $r2, 14 [always], $noreg + ; CHECK: $r4 = tMOVr $r3, 14 [always], $noreg + ; CHECK: $r6 = tMOVr $r1, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) @@ -384,7 +384,7 @@ ; CHECK: bb.4.vector.ph39: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r12 = tMOVr $r0, 14, $noreg + ; CHECK: $r12 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.5.vector.body38: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) @@ -395,11 +395,11 @@ ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv5961, align 4) - ; CHECK: $r0 = tMOVr $r12, 14, $noreg + ; CHECK: $r0 = tMOVr $r12, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: bb.6.for.cond.cleanup6: - ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.6(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 @@ -551,28 +551,28 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg + ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14, $noreg + ; CHECK: early-clobber $sp = frame-setup t2STR_PRE killed $r8, $sp, -4, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -24 - ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: dead renamable $r12 = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.3, 0, killed $cpsr + ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: dead renamable $r12 = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.3, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14, $noreg - ; CHECK: $r8 = tMOVr $r0, 14, $noreg - ; CHECK: $r5 = tMOVr $r1, 14, $noreg - ; CHECK: $r6 = tMOVr $r2, 14, $noreg + ; CHECK: renamable $r4, dead $cpsr = tLSRri renamable $r3, 1, 14 [always], $noreg + ; CHECK: $r8 = tMOVr $r0, 14 [always], $noreg + ; CHECK: $r5 = tMOVr $r1, 14 [always], $noreg + ; CHECK: $r6 = tMOVr $r2, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) @@ -589,7 +589,7 @@ ; CHECK: bb.4.vector.ph39: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r4 = tMOVr $r0, 14, $noreg + ; CHECK: $r4 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.5.vector.body38: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) @@ -600,11 +600,11 @@ ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv5961, align 4) - ; CHECK: $r0 = tMOVr $r4, 14, $noreg + ; CHECK: $r0 = tMOVr $r4, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: bb.6.for.cond.cleanup6: - ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK: $r8, $sp = t2LDR_POST $sp, 4, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8 @@ -766,28 +766,28 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg + ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10 + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r8, killed $r9, killed $r10 ; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 - ; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.9, 0, killed $cpsr + ; CHECK: tCMPi8 renamable $r3, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.9, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r8 = tMOVr $r0, 14, $noreg - ; CHECK: $r5 = tMOVr $r2, 14, $noreg - ; CHECK: $r4 = tMOVr $r3, 14, $noreg - ; CHECK: $r6 = tMOVr $r1, 14, $noreg + ; CHECK: $r8 = tMOVr $r0, 14 [always], $noreg + ; CHECK: $r5 = tMOVr $r2, 14 [always], $noreg + ; CHECK: $r4 = tMOVr $r3, 14 [always], $noreg + ; CHECK: $r6 = tMOVr $r1, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r4 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) @@ -800,18 +800,18 @@ ; CHECK: bb.3.for.cond4.preheader: ; CHECK: successors: %bb.6(0x30000000), %bb.4(0x50000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: dead renamable $r8 = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 0, killed $cpsr + ; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: dead renamable $r8 = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrs killed renamable $r6, renamable $r3, 11, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.6, 0 [equal], killed $cpsr ; CHECK: bb.4.vector.ph66: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14, $noreg - ; CHECK: $r10 = tMOVr $r0, 14, $noreg - ; CHECK: $r9 = tMOVr $r2, 14, $noreg - ; CHECK: $r4 = tMOVr $r1, 14, $noreg - ; CHECK: $r6 = tMOVr $r0, 14, $noreg + ; CHECK: renamable $r5, dead $cpsr = tLSRri renamable $r3, 1, 14 [always], $noreg + ; CHECK: $r10 = tMOVr $r0, 14 [always], $noreg + ; CHECK: $r9 = tMOVr $r2, 14 [always], $noreg + ; CHECK: $r4 = tMOVr $r1, 14 [always], $noreg + ; CHECK: $r6 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r5 ; CHECK: bb.5.vector.body65: ; CHECK: successors: %bb.5(0x7c000000), %bb.6(0x04000000) @@ -822,7 +822,7 @@ ; CHECK: renamable $q0 = MVE_VEOR killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = nsw MVE_VADDi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r10, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv114116, align 4) - ; CHECK: $r10 = tMOVr $r6, 14, $noreg + ; CHECK: $r10 = tMOVr $r6, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 ; CHECK: bb.6.for.cond15.preheader: ; CHECK: successors: %bb.9(0x30000000), %bb.7(0x50000000) @@ -831,7 +831,7 @@ ; CHECK: bb.7.vector.ph85: ; CHECK: successors: %bb.8(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $r5 = tMOVr $r0, 14, $noreg + ; CHECK: $r5 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.8.vector.body84: ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) @@ -842,11 +842,11 @@ ; CHECK: renamable $q0 = MVE_VADDi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi32 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv105107, align 4) - ; CHECK: $r0 = tMOVr $r5, 14, $noreg + ; CHECK: $r0 = tMOVr $r5, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.8 ; CHECK: bb.9.for.cond.cleanup17: - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10 - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r8, def $r9, def $r10 + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.9(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10 Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir @@ -4,7 +4,7 @@ # CHECK-NOLOB-NOT: t2LE # CHECK-LOB: bb.3.land.rhs: -# CHECK-LOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg +# CHECK-LOB: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg # CHECK-LOB: tCBNZ $r0, %bb.8 # CHECK-LOB: t2LE %bb.3 # CHECK-LOB: bb.7.while.body19: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir @@ -109,25 +109,25 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 2, implicit-def $itstate - ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 0, $cpsr, implicit killed $r0, implicit $itstate - ; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit killed $itstate - ; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: renamable $r0 = tMOVi8 $noreg, 0, 0 [equal], $cpsr, implicit killed $r0, implicit $itstate + ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 0 [equal], $cpsr, implicit killed $r0, implicit $itstate + ; CHECK: tBX_RET 0 [equal], killed $cpsr, implicit $r0, implicit killed $itstate + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg + ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $r3 = t2ADDri renamable $r2, 15, 14, $noreg, $noreg + ; CHECK: renamable $r3 = t2ADDri renamable $r2, 15, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 15, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14, $noreg, $noreg + ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 15, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 16, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 35, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2LSRri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 34, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -137,7 +137,7 @@ ; CHECK: MVE_VPST 2, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r0, renamable $q2 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, $noreg :: (load 16 from %ir.lsr.iv19, align 1) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14, $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 16, 14 [always], $noreg ; CHECK: renamable $q2 = MVE_VADDi8 killed renamable $q2, renamable $q1, 0, $noreg, undef renamable $q2 ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 @@ -146,9 +146,9 @@ ; CHECK: renamable $vpr = MVE_VCTP8 killed renamable $r3, 0, $noreg ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr ; CHECK: renamable $r0 = MVE_VADDVu8no_acc killed renamable $q0, 0, $noreg - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: renamable $r0 = tUXTB killed renamable $r0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir @@ -101,26 +101,26 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14, $noreg + ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg + ; CHECK: tPOP_RET 0 [equal], killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r12 = t2ADDri renamable $r3, 15, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 15, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 16, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 ; CHECK: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 [always], $noreg ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv15, align 1) ; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv1618, align 1) @@ -128,7 +128,7 @@ ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, $noreg :: (store 16 into %ir.lsr.iv1921, align 1) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/out-of-range-cbz.mir @@ -162,125 +162,135 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.5(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $r0, $r1, $r7, $lr - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14, $noreg - ; CHECK: tBcc %bb.5, 0, killed $cpsr + ; CHECK: dead renamable $r1, $cpsr = tORR killed renamable $r1, renamable $r0, 14 [always], $noreg + ; CHECK: tBcc %bb.5, 0 [equal], killed $cpsr ; CHECK: bb.1.entry.split: ; CHECK: successors: %bb.15(0x30000000), %bb.2(0x50000000) ; CHECK: liveins: $r0 - ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.15, 0, killed $cpsr + ; CHECK: tCMPi8 renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.15, 0 [equal], killed $cpsr ; CHECK: bb.2.j.preheader: ; CHECK: successors: %bb.3(0x80000000) ; CHECK: liveins: $r0 - ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg - ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg - ; CHECK: tCMPr killed renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr - ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg + ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14 [always], $noreg + ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14 [always], $noreg + ; CHECK: tCMPr killed renamable $r0, killed renamable $r1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @d, 14 [always], $noreg ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr - ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14, $noreg - ; CHECK: renamable $r2 = tLDRi killed renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @d) - ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg - ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg - ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e) + ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @d, 14 [always], $noreg + ; CHECK: renamable $r2 = tLDRi killed renamable $r1, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) + ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14 [always], $noreg + ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14 [always], $noreg + ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 [always], $noreg :: (dereferenceable load 4 from @e) ; CHECK: bb.3.j (align 4): ; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r0, 14 [always], $noreg ; CHECK: tCBZ $r2, %bb.4 + ; CHECK: t2LE %bb.3 ; CHECK: bb.4.if.end: ; CHECK: liveins: $r1, $r3 - ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e) + ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 [always], $noreg :: (store 4 into @e) ; CHECK: INLINEASM &"", 1 - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.5.j.us.us.preheader: ; CHECK: successors: %bb.6(0x80000000) - ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg - ; CHECK: $lr = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg - ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14, $noreg - ; CHECK: $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) - ; CHECK: $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14, $noreg - ; CHECK: $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14, $noreg + ; CHECK: $r12 = t2MOVi16 target-flags(arm-lo16) @d, 14 [always], $noreg + ; CHECK: $lr = t2MOVi16 target-flags(arm-lo16) @a, 14 [always], $noreg + ; CHECK: $r12 = t2MOVTi16 killed $r12, target-flags(arm-hi16) @d, 14 [always], $noreg + ; CHECK: $r2 = t2MOVi16 target-flags(arm-lo16) @e, 14 [always], $noreg + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) + ; CHECK: $lr = t2MOVTi16 killed $lr, target-flags(arm-hi16) @a, 14 [always], $noreg + ; CHECK: $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @e, 14 [always], $noreg ; CHECK: bb.6.j.us.us (align 4): ; CHECK: successors: %bb.7(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r3, $r12 - ; CHECK: tCMPhir renamable $r3, renamable $lr, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r1 = tLDRi renamable $r2, 0, 14, $noreg :: (dereferenceable load 4 from @e) + ; CHECK: tCMPhir renamable $r3, renamable $lr, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r1 = tLDRi renamable $r2, 0, 14 [always], $noreg :: (dereferenceable load 4 from @e) ; CHECK: renamable $r0 = t2CSINC $zr, $zr, 10, implicit killed $cpsr - ; CHECK: renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14, $noreg, $noreg - ; CHECK: tSTRi killed renamable $r0, renamable $r2, 0, 14, $noreg :: (store 4 into @e) + ; CHECK: renamable $r0 = t2ANDrr killed renamable $r0, killed renamable $r1, 14 [always], $noreg, $noreg + ; CHECK: tSTRi killed renamable $r0, renamable $r2, 0, 14 [always], $noreg :: (store 4 into @e) ; CHECK: tCBZ $r3, %bb.7 + ; CHECK: t2LE %bb.6 ; CHECK: bb.7.if.end.us.us.us: ; CHECK: successors: %bb.8(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.8 + ; CHECK: t2LE %bb.6 ; CHECK: bb.8.if.end.us.us.us.1: ; CHECK: successors: %bb.9(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.9 + ; CHECK: t2LE %bb.6 ; CHECK: bb.9.if.end.us.us.us.2: ; CHECK: successors: %bb.10(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.10 + ; CHECK: t2LE %bb.6 ; CHECK: bb.10.if.end.us.us.us.3: ; CHECK: successors: %bb.11(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.11 + ; CHECK: t2LE %bb.6 ; CHECK: bb.11.if.end.us.us.us.4: ; CHECK: successors: %bb.12(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.12 + ; CHECK: t2LE %bb.6 ; CHECK: bb.12.if.end.us.us.us.5: ; CHECK: successors: %bb.13(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.13 + ; CHECK: t2LE %bb.6 ; CHECK: bb.13.if.end.us.us.us.6: ; CHECK: successors: %bb.14(0x04000000), %bb.6(0x7c000000) ; CHECK: liveins: $lr, $r2, $r12 ; CHECK: INLINEASM &"", 1 - ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14, $noreg :: (dereferenceable load 4 from @d) + ; CHECK: renamable $r3 = t2LDRi12 renamable $r12, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) ; CHECK: tCBZ $r3, %bb.14 + ; CHECK: t2LE %bb.6 ; CHECK: bb.14.if.end.us.us.us.7: ; CHECK: INLINEASM &"", 1 - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc ; CHECK: bb.15.j.us27.preheader: ; CHECK: successors: %bb.16(0x80000000) - ; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14, $noreg - ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14, $noreg - ; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14, $noreg - ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14, $noreg - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (dereferenceable load 4 from @d) - ; CHECK: tCMPr renamable $r0, killed renamable $r1, 14, $noreg, implicit-def $cpsr - ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14, $noreg - ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14, $noreg + ; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @d, 14 [always], $noreg + ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @a, 14 [always], $noreg + ; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @d, 14 [always], $noreg + ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @a, 14 [always], $noreg + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (dereferenceable load 4 from @d) + ; CHECK: tCMPr renamable $r0, killed renamable $r1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $r1 = t2MOVi16 target-flags(arm-lo16) @e, 14 [always], $noreg + ; CHECK: $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @e, 14 [always], $noreg ; CHECK: renamable $r2 = t2CSINC $zr, $zr, 10, implicit killed $cpsr - ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (dereferenceable load 4 from @e) + ; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 [always], $noreg :: (dereferenceable load 4 from @e) ; CHECK: bb.16.j.us27 (align 4): ; CHECK: successors: %bb.17(0x04000000), %bb.16(0x7c000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tAND killed renamable $r3, renamable $r2, 14 [always], $noreg ; CHECK: tCBZ $r0, %bb.17 + ; CHECK: t2LE %bb.16 ; CHECK: bb.17.if.end.us38: ; CHECK: liveins: $r1, $r3 - ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14, $noreg :: (store 4 into @e) + ; CHECK: tSTRi killed renamable $r3, killed renamable $r1, 0, 14 [always], $noreg :: (store 4 into @e) ; CHECK: INLINEASM &"", 1 - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x30000000), %bb.11(0x50000000) liveins: $r0, $r1, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir @@ -144,83 +144,83 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.9(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.9, 0, killed $cpsr + ; CHECK: tCMPi8 renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.9, 0 [equal], killed $cpsr ; CHECK: bb.1.while.body.preheader: ; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: tCMPi8 renamable $r2, 4, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 3, killed $cpsr + ; CHECK: tCMPi8 renamable $r2, 4, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.6, 3 [lower], killed $cpsr ; CHECK: bb.2.vector.memcheck: ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14, $noreg, $noreg - ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r3 = t2ADDrs renamable $r0, renamable $r2, 18, 14 [always], $noreg, $noreg + ; CHECK: tCMPr killed renamable $r3, renamable $r1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 8, 4, implicit-def $itstate - ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8, $cpsr, $noreg, implicit $itstate - ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8, killed $cpsr, implicit-def $cpsr, implicit killed $itstate - ; CHECK: tBcc %bb.6, 8, killed $cpsr + ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r2, 18, 8 [higher], $cpsr, $noreg, implicit $itstate + ; CHECK: tCMPr killed renamable $r3, renamable $r0, 8 [higher], killed $cpsr, implicit-def $cpsr, implicit killed $itstate + ; CHECK: tBcc %bb.6, 8 [higher], killed $cpsr ; CHECK: bb.3.vector.ph: ; CHECK: successors: %bb.4(0x80000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14, $noreg, $noreg - ; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14, $noreg - ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14, $noreg, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14, $noreg - ; CHECK: $r5 = tMOVr killed $r3, 14, $noreg - ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14, $noreg, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14, $noreg + ; CHECK: renamable $r4 = t2BICri renamable $r2, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2SUBri renamable $r4, 4, 14 [always], $noreg, $noreg + ; CHECK: renamable $r7, dead $cpsr = tSUBrr renamable $r2, renamable $r4, 14 [always], $noreg + ; CHECK: renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDrs renamable $r0, renamable $r4, 18, 14 [always], $noreg, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 16, 14 [always], $noreg + ; CHECK: $r5 = tMOVr killed $r3, 14 [always], $noreg + ; CHECK: renamable $r3 = t2ADDrs renamable $r1, renamable $r4, 18, 14 [always], $noreg, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 16, 14 [always], $noreg ; CHECK: bb.4.vector.body: ; CHECK: successors: %bb.4(0x7c000000), %bb.5(0x04000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r7, $r12 ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_pre killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.scevgep18, align 4) - ; CHECK: $lr = tMOVr killed $r5, 14, $noreg + ; CHECK: $lr = tMOVr killed $r5, 14 [always], $noreg ; CHECK: renamable $q0 = nnan ninf nsz arcp contract afn reassoc MVE_VABSf32 killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r1 = MVE_VSTRBU8_pre killed renamable $q0, killed renamable $r1, 16, 0, $noreg :: (store 16 into %ir.scevgep13, align 4) - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr - ; CHECK: $r5 = tMOVr killed $lr, 14, $noreg - ; CHECK: tBcc %bb.4, 1, killed $cpsr - ; CHECK: tB %bb.5, 14, $noreg + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, def $cpsr + ; CHECK: $r5 = tMOVr killed $lr, 14 [always], $noreg + ; CHECK: tBcc %bb.4, 1 [notequal], killed $cpsr + ; CHECK: tB %bb.5, 14 [always], $noreg ; CHECK: bb.5.middle.block: ; CHECK: successors: %bb.7(0x80000000) ; CHECK: liveins: $r2, $r3, $r4, $r7, $r12 - ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14, $noreg, implicit-def $cpsr - ; CHECK: $lr = tMOVr killed $r7, 14, $noreg + ; CHECK: tCMPr killed renamable $r4, killed renamable $r2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $lr = tMOVr killed $r7, 14 [always], $noreg ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0, killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate - ; CHECK: tB %bb.7, 14, $noreg + ; CHECK: tPOP_RET 0 [equal], killed $cpsr, def $r4, def $r5, def $r7, def $pc, implicit killed $itstate + ; CHECK: tB %bb.7, 14 [always], $noreg ; CHECK: bb.6: ; CHECK: successors: %bb.7(0x80000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $lr = tMOVr killed $r2, 14, $noreg - ; CHECK: $r12 = tMOVr killed $r0, 14, $noreg - ; CHECK: $r3 = tMOVr killed $r1, 14, $noreg + ; CHECK: $lr = tMOVr killed $r2, 14 [always], $noreg + ; CHECK: $r12 = tMOVr killed $r0, 14 [always], $noreg + ; CHECK: $r3 = tMOVr killed $r1, 14 [always], $noreg ; CHECK: bb.7.while.body.preheader19: ; CHECK: successors: %bb.8(0x80000000) ; CHECK: liveins: $lr, $r3, $r12 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14, $noreg - ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r3, 4, 14 [always], $noreg + ; CHECK: renamable $r1 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.8.while.body: ; CHECK: successors: %bb.8(0x7c000000), %bb.9(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14, $noreg :: (load 4 from %ir.scevgep3) - ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14, $noreg - ; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14, $noreg :: (store 4 into %ir.scevgep7) - ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg + ; CHECK: renamable $s0 = VLDRS renamable $r1, 1, 14 [always], $noreg :: (load 4 from %ir.scevgep3) + ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VABSS killed renamable $s0, 14 [always], $noreg + ; CHECK: VSTRS killed renamable $s0, renamable $r0, 1, 14 [always], $noreg :: (store 4 into %ir.scevgep7) + ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 [always], $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.8 ; CHECK: bb.9.while.end: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r7, def $pc bb.0.entry: successors: %bb.9(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir @@ -1,9 +1,9 @@ # RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s # CHECK-NOT: t2DLS # CHECK: bb.5.for.inc16: -# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr +# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, def $cpsr # CHECK-NOT: t2CMPri $lr -# CHECK: tBcc %bb.6, 1 +# CHECK: tBcc %bb.6, 1 [notequal] # CHECK: tB %bb.2 # CHECK: bb.6.for.cond4.preheader: Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir @@ -98,30 +98,30 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: liveins: $lr, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: t2CMPri $r3, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.3, 0, killed $cpsr - ; CHECK: tB %bb.1, 14, $noreg + ; CHECK: t2CMPri $r3, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.3, 0 [equal], killed $cpsr + ; CHECK: tB %bb.1, 14 [always], $noreg ; CHECK: bb.1.do.body.preheader: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r1, $r2, $r3 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg - ; CHECK: $lr = tMOVr killed $r3, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: $lr = tMOVr killed $r3, 14 [always], $noreg ; CHECK: bb.2.do.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 ; CHECK: dead renamable $r2 = SPACE 4096, undef renamable $r0 - ; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep) - ; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep1) - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr - ; CHECK: t2Bcc %bb.2, 1, killed $cpsr - ; CHECK: tB %bb.3, 14, $noreg + ; CHECK: renamable $r2, renamable $r0 = t2LDR_PRE killed renamable $r0, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep) + ; CHECK: early-clobber renamable $r1 = t2STR_PRE killed renamable $r2, killed renamable $r1, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep1) + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, def $cpsr + ; CHECK: t2Bcc %bb.2, 1 [notequal], killed $cpsr + ; CHECK: tB %bb.3, 14 [always], $noreg ; CHECK: bb.3.if.end: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-def-no-mov.mir @@ -92,26 +92,26 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: dead $lr = t2DLS killed $r0 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg ; CHECK: bb.1.preheader: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: $lr = tMOVr $r0, 14, $noreg + ; CHECK: $lr = tMOVr $r0, 14 [always], $noreg ; CHECK: bb.2.while.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep2) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.while.end: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir @@ -110,28 +110,28 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 $r3, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tPOP_RET 0, killed $cpsr, def $r7, def $pc, implicit killed $itstate - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg + ; CHECK: tPOP_RET 0 [equal], killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 [always], $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 [always], $noreg ; CHECK: $lr = t2DLS killed $r3 ; CHECK: bb.1.for.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: dead renamable $r3 = SPACE 4070, undef renamable $r0 - ; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep3) - ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7) - ; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14, $noreg - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep11) + ; CHECK: renamable $r12, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep3) + ; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE killed renamable $r2, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: renamable $r3 = nsw t2MUL killed renamable $r3, killed renamable $r12, 14 [always], $noreg + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep11) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir @@ -175,31 +175,31 @@ ; CHECK: DBG_VALUE $r1, $noreg, !18, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23 ; CHECK: DBG_VALUE $r2, $noreg, !19, !DIExpression(), debug-location !23 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 16 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -16 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg + ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 2, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14, $noreg, debug-location !24 :: (load 4 from %ir.a) + ; CHECK: renamable $r12 = t2LDRi12 renamable $r0, 0, 14 [always], $noreg, debug-location !24 :: (load 4 from %ir.a) ; CHECK: DBG_VALUE 0, $noreg, !21, !DIExpression(), debug-location !25 ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23 ; CHECK: tCBZ $r2, %bb.4, debug-location !28 ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r12 - ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg, debug-location !28 - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg, debug-location !28 - ; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg, debug-location !28 + ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 [always], $noreg, debug-location !28 + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 [always], $noreg, $noreg, debug-location !28 + ; CHECK: renamable $r4, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg, debug-location !28 ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q0, debug-location !28 - ; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14, $noreg, debug-location !28 - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14, $noreg, $noreg, debug-location !28 - ; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14, $noreg, debug-location !28 - ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14, $noreg, $noreg, debug-location !28 + ; CHECK: renamable $q0 = MVE_VMOV_to_lane_32 killed renamable $q0, killed renamable $r12, 0, 14 [always], $noreg, debug-location !28 + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, renamable $r3, 19, 14 [always], $noreg, $noreg, debug-location !28 + ; CHECK: renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 2, 14 [always], $noreg, debug-location !28 + ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r3, 18, 14 [always], $noreg, $noreg, debug-location !28 ; CHECK: $lr = t2DLS killed renamable $lr, debug-location !28 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) @@ -209,7 +209,7 @@ ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 ; CHECK: MVE_VPST 8, implicit $vpr, debug-location !30 ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRHU32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !30 :: (load 8 from %ir.lsr.iv14, align 2) - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !30 + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 [always], $noreg, debug-location !30 ; CHECK: renamable $q0 = MVE_VMOVLs16bh killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !30 ; CHECK: renamable $q0 = MVE_VSUBi32 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0, debug-location !32 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !29 @@ -222,8 +222,8 @@ ; CHECK: bb.4.for.cond.cleanup: ; CHECK: liveins: $r0, $r12 ; CHECK: DBG_VALUE $r12, $noreg, !20, !DIExpression(), debug-location !23 - ; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14, $noreg, debug-location !33 :: (store 4 into %ir.a) - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34 + ; CHECK: t2STRi12 killed renamable $r12, killed renamable $r0, 0, 14 [always], $noreg, debug-location !33 :: (store 4 into %ir.a) + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r6, def $r7, def $pc, debug-location !34 bb.0.entry: successors: %bb.4(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r4, $r6, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir @@ -233,54 +233,54 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.11(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg + ; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8 - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r11 + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r8, killed $r9, killed $r11 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -24 ; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32 - ; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.11, 0, killed $cpsr + ; CHECK: tCMPi8 renamable $r3, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.11, 0 [equal], killed $cpsr ; CHECK: bb.1.vector.memcheck: ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: tCMPr renamable $r4, renamable $r2, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg + ; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: tCMPr renamable $r4, renamable $r2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg ; CHECK: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: tCMPr killed renamable $r4, renamable $r1, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg + ; CHECK: tCMPr killed renamable $r4, renamable $r1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 [always], $noreg, $noreg ; CHECK: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPr killed renamable $r5, renamable $r0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr - ; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14, $noreg - ; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14, $noreg + ; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 [always], $noreg + ; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 [always], $noreg ; CHECK: t2IT 0, 4, implicit-def $itstate - ; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0, $cpsr, $noreg, implicit killed $r6, implicit $itstate - ; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate - ; CHECK: tBcc %bb.4, 0, killed $cpsr + ; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 [equal], $cpsr, $noreg, implicit killed $r6, implicit $itstate + ; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 [equal], killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate + ; CHECK: tBcc %bb.4, 0 [equal], killed $cpsr ; CHECK: bb.2.for.body.preheader: ; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg - ; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.6, 2, killed $cpsr + ; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 [always], $noreg + ; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: tCMPi8 killed renamable $r4, 3, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.6, 2 [highersame], killed $cpsr ; CHECK: bb.3: ; CHECK: successors: %bb.8(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r12 - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tB %bb.8, 14, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tB %bb.8, 14 [always], $noreg ; CHECK: bb.4.vector.ph: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 @@ -293,75 +293,75 @@ ; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv5052, align 1) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5 - ; CHECK: tB %bb.11, 14, $noreg + ; CHECK: tB %bb.11, 14 [always], $noreg ; CHECK: bb.6.for.body.preheader.new: ; CHECK: successors: %bb.7(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14, $noreg, $noreg - ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg + ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 [always], $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 [always], $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14 [always], $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.7.for.body: ; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.scevgep2453) - ; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg - ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.scevgep2854) - ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg - ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14, $noreg - ; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.scevgep3255) - ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14, $noreg :: (load 1 from %ir.scevgep40) - ; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14, $noreg :: (load 1 from %ir.scevgep42) - ; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14, $noreg - ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg - ; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14, $noreg :: (store 1 into %ir.scevgep44) - ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14, $noreg :: (load 1 from %ir.scevgep34) - ; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14, $noreg :: (load 1 from %ir.scevgep36) - ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14, $noreg - ; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14, $noreg :: (store 1 into %ir.scevgep38) - ; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14, $noreg :: (load 1 from %ir.scevgep22) - ; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14, $noreg :: (load 1 from %ir.scevgep26) - ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14, $noreg - ; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14, $noreg :: (store 1 into %ir.scevgep30) + ; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14 [always], $noreg :: (load 1 from %ir.scevgep2453) + ; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 [always], $noreg, $noreg + ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 [always], $noreg :: (load 1 from %ir.scevgep2854) + ; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 [always], $noreg + ; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14 [always], $noreg :: (store 1 into %ir.scevgep3255) + ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 [always], $noreg :: (load 1 from %ir.scevgep40) + ; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14 [always], $noreg :: (load 1 from %ir.scevgep42) + ; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 [always], $noreg + ; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 [always], $noreg + ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 [always], $noreg + ; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 [always], $noreg :: (store 1 into %ir.scevgep44) + ; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 [always], $noreg :: (load 1 from %ir.scevgep34) + ; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14 [always], $noreg :: (load 1 from %ir.scevgep36) + ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 [always], $noreg + ; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14 [always], $noreg :: (store 1 into %ir.scevgep38) + ; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 [always], $noreg :: (load 1 from %ir.scevgep22) + ; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14 [always], $noreg :: (load 1 from %ir.scevgep26) + ; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 [always], $noreg + ; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 [always], $noreg :: (store 1 into %ir.scevgep30) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.7 ; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa: ; CHECK: successors: %bb.11(0x30000000), %bb.9(0x50000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.11, 0, killed $cpsr + ; CHECK: t2CMPri renamable $r12, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.11, 0 [equal], killed $cpsr ; CHECK: bb.9.for.body.epil: ; CHECK: successors: %bb.11(0x40000000), %bb.10(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil) - ; CHECK: t2CMPri renamable $r12, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil) - ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14, $noreg - ; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil) - ; CHECK: tBcc %bb.11, 0, killed $cpsr + ; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14 [always], $noreg :: (load 1 from %ir.arrayidx.epil) + ; CHECK: t2CMPri renamable $r12, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14 [always], $noreg :: (load 1 from %ir.arrayidx1.epil) + ; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 [always], $noreg + ; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14 [always], $noreg :: (store 1 into %ir.arrayidx4.epil) + ; CHECK: tBcc %bb.11, 0 [equal], killed $cpsr ; CHECK: bb.10.for.body.epil.1: ; CHECK: successors: %bb.11(0x40000000), %bb.12(0x40000000) ; CHECK: liveins: $r0, $r1, $r2, $r3, $r12 - ; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14, $noreg - ; CHECK: t2CMPri killed renamable $r12, 2, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14, $noreg :: (load 1 from %ir.arrayidx.epil.1) - ; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.1) - ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14, $noreg - ; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.1) - ; CHECK: tBcc %bb.12, 1, killed $cpsr + ; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 [always], $noreg + ; CHECK: t2CMPri killed renamable $r12, 2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14 [always], $noreg :: (load 1 from %ir.arrayidx.epil.1) + ; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14 [always], $noreg :: (load 1 from %ir.arrayidx1.epil.1) + ; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 [always], $noreg + ; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 [always], $noreg :: (store 1 into %ir.arrayidx4.epil.1) + ; CHECK: tBcc %bb.12, 1 [notequal], killed $cpsr ; CHECK: bb.11.for.cond.cleanup: - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11 - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r8, def $r9, def $r11 + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc ; CHECK: bb.12.for.body.epil.2: ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14, $noreg - ; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil.2) - ; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.2) - ; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg - ; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.2) - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11 - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc + ; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 [always], $noreg + ; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 [always], $noreg :: (load 1 from %ir.arrayidx.epil.2) + ; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 [always], $noreg :: (load 1 from %ir.arrayidx1.epil.2) + ; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 [always], $noreg + ; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 [always], $noreg :: (store 1 into %ir.arrayidx4.epil.2) + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r8, def $r9, def $r11 + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc bb.0.entry: successors: %bb.11(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11 Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-def.mir @@ -95,29 +95,29 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r7, $lr - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $lr = tMOVr killed $r0, 14, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg - ; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14, $noreg, $noreg + ; CHECK: $lr = tMOVr killed $r0, 14 [always], $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg + ; CHECK: renamable $r2 = t2LSRri renamable $lr, 1, 14 [always], $noreg, $noreg ; CHECK: bb.1.while.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) - ; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg + ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, $noreg ; CHECK: t2IT 2, 8, implicit-def $itstate - ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit renamable $r3, implicit killed $itstate - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) - ; CHECK: t2CMPri renamable $lr, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.1, 4, killed $cpsr - ; CHECK: tB %bb.2, 14, $noreg + ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 [highersame], killed $cpsr, implicit renamable $r3, implicit killed $itstate + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep4) + ; CHECK: t2CMPri renamable $lr, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.1, 4 [minus], killed $cpsr + ; CHECK: tB %bb.2, 14 [always], $noreg ; CHECK: bb.2.while.end: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-cpsr-loop-use.mir @@ -95,30 +95,30 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg - ; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14, $noreg, $noreg - ; CHECK: $lr = tMOVr $r0, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg + ; CHECK: renamable $r2 = t2LSRri renamable $r0, 1, 14 [always], $noreg, $noreg + ; CHECK: $lr = tMOVr $r0, 14 [always], $noreg ; CHECK: bb.1.while.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep7) - ; CHECK: tCMPhir renamable $lr, renamable $r2, 14, $noreg, implicit-def $cpsr - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, $noreg + ; CHECK: renamable $r3, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep7) + ; CHECK: tCMPhir renamable $lr, renamable $r2, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, $noreg ; CHECK: t2IT 2, 8, implicit-def $itstate - ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep4) - ; CHECK: renamable $lr = tMOVr killed $lr, 14, $noreg - ; CHECK: t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: tBcc %bb.1, 1, killed $cpsr - ; CHECK: tB %bb.2, 14, $noreg + ; CHECK: renamable $r3 = tLSRri $noreg, killed renamable $r3, 1, 2 [highersame], killed $cpsr, implicit killed renamable $r3, implicit killed $itstate + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r3, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep4) + ; CHECK: renamable $lr = tMOVr killed $lr, 14 [always], $noreg + ; CHECK: t2CMPri $lr, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.1, 1 [notequal], killed $cpsr + ; CHECK: tB %bb.2, 14 [always], $noreg ; CHECK: bb.2.while.end: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-use-after.mir @@ -90,27 +90,27 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r0 = t2SUBri killed renamable $lr, 4, 14, $noreg, def dead $cpsr - ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r0 = t2SUBri killed renamable $lr, 4, 14 [always], $noreg, def dead $cpsr + ; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 [always], $noreg ; CHECK: bb.1.preheader: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: $lr = tMOVr $r0, 14, $noreg + ; CHECK: $lr = tMOVr $r0, 14 [always], $noreg ; CHECK: bb.2.while.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6) - ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2) - ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr - ; CHECK: tBcc %bb.2, 1, killed $cpsr - ; CHECK: tB %bb.3, 14, $noreg + ; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 [always], $noreg :: (load 4 from %ir.scevgep6) + ; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 [always], $noreg :: (store 4 into %ir.scevgep2) + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 [always], $noreg, def $cpsr + ; CHECK: tBcc %bb.2, 1 [notequal], killed $cpsr + ; CHECK: tB %bb.3, 14 [always], $noreg ; CHECK: bb.3.while.end: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir @@ -107,46 +107,46 @@ ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $r7 = frame-setup tMOVr $sp, 14, $noreg + ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 [always], $noreg ; CHECK: tCBZ $r2, %bb.3 ; CHECK: bb.1.bb3: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14, $noreg, $noreg - ; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14, $noreg, $noreg - ; CHECK: $vpr = VMSR_P0 killed $r3, 14, $noreg - ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14, $noreg - ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDri renamable $r2, 3, 14 [always], $noreg, $noreg + ; CHECK: renamable $lr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2BICri killed renamable $r12, 3, 14 [always], $noreg, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r3, 14 [always], $noreg + ; CHECK: renamable $r12 = t2SUBri killed renamable $r12, 4, 14 [always], $noreg, $noreg + ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: $r3 = tMOVr $r0, 14 [always], $noreg + ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 19, 14 [always], $noreg, $noreg ; CHECK: $lr = t2DLS killed renamable $lr ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 [always], $noreg ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $vpr = MVE_VCMPi32r renamable $q0, $zr, 1, 1, killed renamable $vpr ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) - ; CHECK: $r0 = tMOVr $r3, 14, $noreg + ; CHECK: $r0 = tMOVr $r3, 14 [always], $noreg ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir @@ -104,36 +104,36 @@ ; CHECK: bb.0.bb: ; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $r7 = frame-setup tMOVr $sp, 14, $noreg + ; CHECK: dead $r7 = frame-setup tMOVr $sp, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 1, 14 [always], $noreg ; CHECK: tCBZ $r2, %bb.3 ; CHECK: bb.1.bb3: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2, $r3 - ; CHECK: $vpr = VMSR_P0 killed $r3, 14, $noreg - ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14, $noreg :: (store 4 into %stack.0) - ; CHECK: $r3 = tMOVr $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r3, 14 [always], $noreg + ; CHECK: VSTR_P0_off killed renamable $vpr, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.0) + ; CHECK: $r3 = tMOVr $r0, 14 [always], $noreg ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2 ; CHECK: bb.2.bb9: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1, $r3 - ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14, $noreg :: (load 4 from %stack.0) + ; CHECK: renamable $vpr = VLDR_P0_off $sp, 0, 14 [always], $noreg :: (load 4 from %stack.0) ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r1, renamable $q0 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $r3, renamable $q1 = MVE_VLDRWU32_post killed renamable $r3, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv1, align 4) ; CHECK: renamable $q0 = nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4) - ; CHECK: $r0 = tMOVr $r3, 14, $noreg + ; CHECK: $r0 = tMOVr $r3, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.bb27: - ; CHECK: $sp = tADDspi $sp, 1, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: $sp = tADDspi $sp, 1, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.bb: successors: %bb.3(0x30000000), %bb.1(0x50000000) liveins: $r0, $r1, $r2, $r3, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir @@ -101,13 +101,13 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -118,7 +118,7 @@ ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir @@ -100,13 +100,13 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -117,7 +117,7 @@ ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir @@ -100,13 +100,13 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: tCMPi8 renamable $r3, 1, 14, $noreg, implicit-def $cpsr + ; CHECK: tCMPi8 renamable $r3, 1, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 11, 8, implicit-def $itstate - ; CHECK: tPOP_RET 11, killed $cpsr, def $r7, def $pc, implicit killed $itstate + ; CHECK: tPOP_RET 11 [less], killed $cpsr, def $r7, def $pc, implicit killed $itstate ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r3 ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) @@ -117,7 +117,7 @@ ; CHECK: renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1719, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir @@ -142,20 +142,20 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: renamable $r12 = t2LDRi12 $sp, 44, 14, $noreg :: (load 4 from %fixed-stack.6, align 8) + ; CHECK: renamable $r12 = t2LDRi12 $sp, 44, 14 [always], $noreg :: (load 4 from %fixed-stack.6, align 8) ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r12, %bb.3 ; CHECK: bb.1.for.body.lr.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: $r7, $r6 = t2LDRDi8 $sp, 36, 14, $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) - ; CHECK: $r5, $r4 = t2LDRDi8 $sp, 20, 14, $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) + ; CHECK: $r7, $r6 = t2LDRDi8 $sp, 36, 14 [always], $noreg :: (load 4 from %fixed-stack.4, align 8), (load 4 from %fixed-stack.5) + ; CHECK: $r5, $r4 = t2LDRDi8 $sp, 20, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8), (load 4 from %fixed-stack.1) ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r6, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r7, 0, $noreg, undef renamable $q1 ; CHECK: bb.2.for.body: @@ -172,8 +172,8 @@ ; CHECK: renamable $r5 = MVE_VSTRWU32_post killed renamable $q2, killed renamable $r5, 4, 0, killed $noreg :: (store 16 into %ir.output_cast, align 4) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir @@ -139,24 +139,24 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20 - ; CHECK: renamable $r7 = tLDRspi $sp, 10, 14, $noreg :: (load 4 from %fixed-stack.5) - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg + ; CHECK: renamable $r7 = tLDRspi $sp, 10, 14 [always], $noreg :: (load 4 from %fixed-stack.5) + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg ; CHECK: $lr = MVE_WLSTP_32 killed renamable $r7, %bb.3 ; CHECK: bb.1.for.body.lr.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3 - ; CHECK: $r5, $r12 = t2LDRDi8 $sp, 32, 14, $noreg :: (load 4 from %fixed-stack.3), (load 4 from %fixed-stack.4, align 8) - ; CHECK: renamable $r4 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %fixed-stack.0, align 8) + ; CHECK: $r5, $r12 = t2LDRDi8 $sp, 32, 14 [always], $noreg :: (load 4 from %fixed-stack.3), (load 4 from %fixed-stack.4, align 8) + ; CHECK: renamable $r4 = tLDRspi $sp, 5, 14 [always], $noreg :: (load 4 from %fixed-stack.0, align 8) ; CHECK: renamable $q0 = MVE_VDUP32 killed renamable $r12, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q1 = MVE_VDUP32 killed renamable $r5, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg ; CHECK: bb.2.for.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r12 @@ -172,8 +172,8 @@ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: ; CHECK: liveins: $r12 - ; CHECK: $r0 = tMOVr killed $r12, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0 = tMOVr killed $r12, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir @@ -92,7 +92,7 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 @@ -100,17 +100,17 @@ ; CHECK: bb.1.while.body.preheader: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14, $noreg - ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14, $noreg - ; CHECK: $lr = tMOVr killed $r2, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 2, 14 [always], $noreg + ; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 2, 14 [always], $noreg + ; CHECK: $lr = tMOVr killed $r2, 14 [always], $noreg ; CHECK: bb.2.while.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) ; CHECK: liveins: $lr, $r0, $r1 - ; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14, $noreg :: (load 2 from %ir.scevgep4) - ; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14, $noreg :: (store 2 into %ir.scevgep7) + ; CHECK: renamable $r2, renamable $r1 = t2LDRH_PRE killed renamable $r1, 2, 14 [always], $noreg :: (load 2 from %ir.scevgep4) + ; CHECK: early-clobber renamable $r0 = t2STRH_PRE killed renamable $r2, killed renamable $r0, 2, 14 [always], $noreg :: (store 2 into %ir.scevgep7) ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.while.end: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.1(0x40000000), %bb.3(0x40000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir @@ -191,30 +191,30 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 ; CHECK: $lr = MVE_WLSTP_8 killed renamable $r3, %bb.1 - ; CHECK: tB %bb.3, 14, $noreg + ; CHECK: tB %bb.3, 14 [always], $noreg ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r12 - ; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg + ; CHECK: renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep45, align 1) - ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg + ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14 [always], $noreg, $noreg ; CHECK: renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg :: (load 16 from %ir.scevgep23, align 1) - ; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg - ; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg + ; CHECK: renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14 [always], $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDri killed renamable $r12, 16, 14 [always], $noreg, $noreg ; CHECK: renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg :: (store 16 into %ir.scevgep1, align 1) ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r4, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r4, def $pc bb.0.entry: successors: %bb.3(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1, $r2, $r3, $r4, $lr @@ -313,12 +313,12 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1 - ; CHECK: tB %bb.2, 14, $noreg + ; CHECK: tB %bb.2, 14 [always], $noreg ; CHECK: bb.1.vector.body: ; CHECK: successors: %bb.2(0x04000000), %bb.1(0x7c000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 @@ -326,12 +326,12 @@ ; CHECK: renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 2) ; CHECK: renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 2) - ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg - ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg - ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg + ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 [always], $noreg + ; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 [always], $noreg + ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 [always], $noreg ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 ; CHECK: bb.2.for.cond.cleanup: - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc bb.0.entry: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1, $r2, $r3, $r7, $lr @@ -421,13 +421,13 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.4(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $lr, $r0, $r1, $r2, $r7 - ; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup tPUSH 14 [always], $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: renamable $r12 = t2MOVi 0, 14, $noreg, $noreg + ; CHECK: renamable $r12 = t2MOVi 0, 14 [always], $noreg, $noreg ; CHECK: $lr = MVE_WLSTP_32 $r2, %bb.1 - ; CHECK: tB %bb.4, 14, $noreg + ; CHECK: tB %bb.4, 14 [always], $noreg ; CHECK: bb.1.vector.ph: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 @@ -438,11 +438,11 @@ ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, $noreg :: (load 16 from %ir.lsr.iv24, align 4) ; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 0, killed $noreg :: (load 16 from %ir.lsr.iv1, align 4) - ; CHECK: $r3 = tMOVr $r2, 14, $noreg + ; CHECK: $r3 = tMOVr $r2, 14 [always], $noreg ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 - ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg - ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg - ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg + ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 [always], $noreg + ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 [always], $noreg + ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 [always], $noreg ; CHECK: renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2 ; CHECK: bb.3.middle.block: @@ -453,8 +453,8 @@ ; CHECK: renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg ; CHECK: bb.4.for.cond.cleanup: ; CHECK: liveins: $r12 - ; CHECK: $r0 = tMOVr killed $r12, 14, $noreg - ; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0 + ; CHECK: $r0 = tMOVr killed $r12, 14 [always], $noreg + ; CHECK: tPOP_RET 14 [always], $noreg, def $r7, def $pc, implicit killed $r0 bb.0.entry: successors: %bb.4(0x40000000), %bb.1(0x40000000) liveins: $r0, $r1, $r2, $r7, $lr Index: llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir =================================================================== --- llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir +++ llvm/test/CodeGen/Thumb2/constant-islands-cbz.mir @@ -23,13 +23,15 @@ ; CHECK-LABEL: name: test_simple ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) + ; CHECK: liveins: $r0, $r1 ; CHECK: tCBZ $r0, %bb.2 ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -58,15 +60,17 @@ ; CHECK-LABEL: name: test_notfirst ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14, $noreg - ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + ; CHECK: liveins: $r0, $r1 + ; CHECK: renamable $r0, $cpsr = tADDrr killed renamable $r0, renamable $r1, 14 [always], $noreg + ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14 [always], $noreg, $noreg ; CHECK: tCBZ $r0, %bb.2 ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -97,15 +101,17 @@ ; CHECK-LABEL: name: test_redefined ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg - ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: liveins: $r0, $r1 + ; CHECK: tCMPi8 renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r1, 18, 14 [always], $noreg, $noreg + ; CHECK: tBcc %bb.2, 0 [equal], killed $cpsr ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -135,14 +141,16 @@ ; CHECK-LABEL: name: test_notredefined ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14, $noreg, $noreg + ; CHECK: liveins: $r0, $r1 + ; CHECK: renamable $r1 = t2ADDrs renamable $r0, killed renamable $r1, 18, 14 [always], $noreg, $noreg ; CHECK: tCBZ $r0, %bb.2 ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -172,15 +180,17 @@ ; CHECK-LABEL: name: test_notcmp ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14, $noreg - ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: liveins: $r0, $r1 + ; CHECK: tCMPi8 renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: renamable $r1, $cpsr = tADDrr renamable $r0, killed renamable $r1, 14 [always], $noreg + ; CHECK: tBcc %bb.2, 0 [equal], killed $cpsr ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -210,14 +220,16 @@ ; CHECK-LABEL: name: test_killflag_1 ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14, $noreg, $noreg + ; CHECK: liveins: $r0, $r1 + ; CHECK: renamable $r0 = t2ADDrs killed renamable $r0, killed renamable $r0, 18, 14 [always], $noreg, $noreg ; CHECK: tCBZ killed $r1, %bb.2 ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -247,14 +259,16 @@ ; CHECK-LABEL: name: test_killflag_2 ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: renamable $r0 = t2ADDrs renamable $r1, killed renamable $r0, 18, 14, $noreg, $noreg + ; CHECK: liveins: $r0, $r1 + ; CHECK: renamable $r0 = t2ADDrs renamable $r1, killed renamable $r0, 18, 14 [always], $noreg, $noreg ; CHECK: tCBZ killed $r1, %bb.2 ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 @@ -284,16 +298,18 @@ ; CHECK-LABEL: name: test_cpsr ; CHECK: bb.0: ; CHECK: successors: %bb.2(0x30000000), %bb.1(0x50000000) - ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: liveins: $r0, $r1 + ; CHECK: tCMPi8 renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: renamable $r1 = t2ADDri killed renamable $r1, 1, 1, $cpsr, $noreg, implicit killed $itstate - ; CHECK: tBcc %bb.2, 0, killed $cpsr + ; CHECK: renamable $r1 = t2ADDri killed renamable $r1, 1, 1 [notequal], $cpsr, $noreg, implicit killed $itstate + ; CHECK: tBcc %bb.2, 0 [equal], killed $cpsr ; CHECK: bb.1: - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.x) - ; CHECK: tTAILJMPdND @c, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0 + ; CHECK: liveins: $r0 + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.x) + ; CHECK: tTAILJMPdND @c, 14 [always], $noreg, implicit $sp, implicit $sp, implicit killed $r0 ; CHECK: bb.2: - ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 [always], $noreg + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0: successors: %bb.1(0x30000000), %bb.2(0x50000000) liveins: $r0, $r1 Index: llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir =================================================================== --- llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir +++ llvm/test/CodeGen/Thumb2/fp16-stacksplot.mir @@ -16,7 +16,7 @@ bb.0: ; CHECK-LABEL: name: func0 ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -27,7 +27,7 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 - ; CHECK: $sp = frame-setup t2SUBspImm killed $sp, 1208, 14, $noreg, $noreg + ; CHECK: $sp = frame-setup t2SUBspImm killed $sp, 1208, 14 [always], $noreg, $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1244 ; CHECK: $r0 = IMPLICIT_DEF ; CHECK: $r1 = IMPLICIT_DEF @@ -43,10 +43,10 @@ ; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF - ; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2) - ; CHECK: $r0 = t2ADDri killed $sp, 1024, 14, $noreg, $noreg + ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.2) + ; CHECK: $r0 = t2ADDri killed $sp, 1024, 14 [always], $noreg, $noreg ; CHECK: renamable $s4 = VLDRH killed $r0, 91, 14, $noreg :: (dereferenceable load 2 from %stack.0) - ; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2) + ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 [always], $noreg :: (load 4 from %stack.2) ; CHECK: KILL $r0 ; CHECK: KILL $r1 ; CHECK: KILL $r2 Index: llvm/test/CodeGen/Thumb2/high-reg-spill.mir =================================================================== --- llvm/test/CodeGen/Thumb2/high-reg-spill.mir +++ llvm/test/CodeGen/Thumb2/high-reg-spill.mir @@ -42,9 +42,9 @@ ... # CHECK: bb.0.entry: -# CHECK-NEXT: renamable $r0 = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i) +# CHECK-NEXT: renamable $r0 = tLDRspi %stack.0.i, 0, 14 [always], $noreg :: (dereferenceable load 4 from %ir.i) # CHECK-NEXT: renamable $r12 = COPY killed renamable $r0 -# CHECK-NEXT: t2STRi12 killed $r12, %stack.1, 0, 14, $noreg :: (store 4 into %stack.1) -# CHECK-NEXT: $r8 = t2LDRi12 %stack.1, 0, 14, $noreg :: (load 4 from %stack.1) +# CHECK-NEXT: t2STRi12 killed $r12, %stack.1, 0, 14 [always], $noreg :: (store 4 into %stack.1) +# CHECK-NEXT: $r8 = t2LDRi12 %stack.1, 0, 14 [always], $noreg :: (load 4 from %stack.1) # CHECK-NEXT: INLINEASM &"@ $0", 1, 589833, renamable $r8, 12, implicit-def early-clobber $r12 -# CHECK-NEXT: tBX_RET 14, $noreg +# CHECK-NEXT: tBX_RET 14 [always], $noreg Index: llvm/test/CodeGen/Thumb2/ifcvt-cbz.mir =================================================================== --- llvm/test/CodeGen/Thumb2/ifcvt-cbz.mir +++ llvm/test/CodeGen/Thumb2/ifcvt-cbz.mir @@ -26,16 +26,16 @@ ; CHECK-LABEL: name: f1 ; CHECK: bb.0: ; CHECK: liveins: $r0, $lr, $r7 - ; CHECK: t2CMPri killed renamable $r0, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: tBX_RET 1, killed $cpsr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: t2CMPri killed renamable $r0, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: tBX_RET 1 [notequal], killed $cpsr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $r0 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tBL 14, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: tBX_RET 14, $noreg + ; CHECK: $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tBL 14 [always], $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: tBX_RET 14 [always], $noreg bb.0: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0, $lr, $r7 @@ -78,21 +78,21 @@ ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $r0, $lr, $r7 - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.2, 1, killed $cpsr + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.2, 1 [notequal], killed $cpsr ; CHECK: bb.1: ; CHECK: liveins: $r7, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $r0 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tBL 14, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: tBX_RET 14, $noreg + ; CHECK: $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tBL 14 [always], $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: tBX_RET 14 [always], $noreg ; CHECK: bb.2: ; CHECK: liveins: $lr, $r7 - ; CHECK: tBX_RET 14, $noreg + ; CHECK: tBX_RET 14 [always], $noreg bb.0: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0, $lr, $r7 @@ -135,22 +135,22 @@ ; CHECK: bb.0: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $r0, $lr, $r7 - ; CHECK: t2CMPri killed renamable $r0, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: $r1 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: t2Bcc %bb.2, 1, killed $cpsr + ; CHECK: t2CMPri killed renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: $r1 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: t2Bcc %bb.2, 1 [notequal], killed $cpsr ; CHECK: bb.1: ; CHECK: liveins: $r7, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $r0 = t2MOVi 0, 14, $noreg, $noreg - ; CHECK: tBL 14, $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 - ; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r7, def $lr - ; CHECK: tBX_RET 14, $noreg + ; CHECK: $r0 = t2MOVi 0, 14 [always], $noreg, $noreg + ; CHECK: tBL 14 [always], $noreg, @fn, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def dead $r0 + ; CHECK: $sp = t2LDMIA_UPD $sp, 14 [always], $noreg, def $r7, def $lr + ; CHECK: tBX_RET 14 [always], $noreg ; CHECK: bb.2: ; CHECK: liveins: $lr, $r7 - ; CHECK: tBX_RET 14, $noreg + ; CHECK: tBX_RET 14 [always], $noreg bb.0: successors: %bb.1(0x40000000), %bb.2(0x40000000) liveins: $r0, $lr, $r7 Index: llvm/test/CodeGen/Thumb2/mve-stacksplot.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-stacksplot.mir +++ llvm/test/CodeGen/Thumb2/mve-stacksplot.mir @@ -12,7 +12,7 @@ bb.0: ; CHECK-LABEL: name: func0 ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -23,7 +23,7 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 - ; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14, $noreg + ; CHECK: $sp = frame-setup tSUBspi $sp, 5, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 56 ; CHECK: $r0 = IMPLICIT_DEF ; CHECK: $r1 = IMPLICIT_DEF @@ -39,10 +39,10 @@ ; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF - ; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.1) - ; CHECK: $r0 = tMOVr killed $sp, 14, $noreg + ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.1) + ; CHECK: $r0 = tMOVr killed $sp, 14 [always], $noreg ; CHECK: renamable $q2 = MVE_VLDRBU32 killed $r0, 16, 0, $noreg :: (load 4 from %stack.0 + 12) - ; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.1) + ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 [always], $noreg :: (load 4 from %stack.1) ; CHECK: KILL $r0 ; CHECK: KILL $r1 ; CHECK: KILL $r2 @@ -105,7 +105,7 @@ bb.0: ; CHECK-LABEL: name: func1 ; CHECK: liveins: $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $r11, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 36 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -8 @@ -116,7 +116,7 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -28 ; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -32 ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -36 - ; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14, $noreg + ; CHECK: $sp = frame-setup t2SUBspImm12 killed $sp, 1220, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 1256 ; CHECK: $r0 = IMPLICIT_DEF ; CHECK: $r1 = IMPLICIT_DEF @@ -132,10 +132,10 @@ ; CHECK: $r11 = IMPLICIT_DEF ; CHECK: $r12 = IMPLICIT_DEF ; CHECK: $lr = IMPLICIT_DEF - ; CHECK: t2STRi12 killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.2) - ; CHECK: $r0 = t2ADDri killed $sp, 1152, 14, $noreg, $noreg + ; CHECK: t2STRi12 killed $r0, $sp, 0, 14 [always], $noreg :: (store 4 into %stack.2) + ; CHECK: $r0 = t2ADDri killed $sp, 1152, 14 [always], $noreg, $noreg ; CHECK: renamable $q2 = MVE_VLDRBU8 killed $r0, 52, 0, $noreg :: (load 4 from %stack.0) - ; CHECK: $r0 = t2LDRi12 $sp, 0, 14, $noreg :: (load 4 from %stack.2) + ; CHECK: $r0 = t2LDRi12 $sp, 0, 14 [always], $noreg :: (load 4 from %stack.2) ; CHECK: KILL $r0 ; CHECK: KILL $r1 ; CHECK: KILL $r2 Index: llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-1-pred.mir @@ -67,18 +67,18 @@ ; CHECK-LABEL: name: vpt_2_blocks_1_pred ; CHECK: successors: %bb.0(0x80000000) ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 - ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg + ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 [always], $noreg, $noreg ; CHECK: BUNDLE implicit-def $vpr, implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $q1, implicit $q5, implicit killed $r4 { ; CHECK: MVE_VPTv4u32 8, renamable $q1, renamable $q5, 2, implicit-def $vpr ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, internal renamable $vpr ; CHECK: } - ; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14, $noreg, $noreg + ; CHECK: renamable $r4 = t2ADDrr renamable $r11, renamable $r10, 14 [always], $noreg, $noreg ; CHECK: BUNDLE implicit-def $q7, implicit-def $d14, implicit-def $s28, implicit-def $s29, implicit-def $d15, implicit-def $s30, implicit-def $s31, implicit killed $vpr, implicit killed $r4 { ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $q7 = MVE_VLDRBU32 killed renamable $r4, 0, 1, killed renamable $vpr ; CHECK: } ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr - ; CHECK: t2B %bb.0, 14, $noreg + ; CHECK: t2B %bb.0, 14 [always], $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr Index: llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir @@ -66,18 +66,18 @@ ; CHECK-LABEL: name: vpt_2_blocks_2_preds ; CHECK: liveins: $q0, $q1, $q2, $r0, $r1 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit killed $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 ; CHECK: } - ; CHECK: $vpr = VMSR_P0 killed $r1, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r1, 14 [always], $noreg ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q3, implicit killed $q2, implicit killed $q0 { ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: } - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, killed renamable $vpr, killed renamable $q3 Index: llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir @@ -67,7 +67,7 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $q0, $q1, $q2, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: MVE_VPST 4, implicit $vpr @@ -81,7 +81,7 @@ ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: } - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 bb.0.entry: liveins: $q0, $q1, $q2, $r0 Index: llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir @@ -67,7 +67,7 @@ ; CHECK-LABEL: name: vpt_2_blocks_non_consecutive_ins ; CHECK: liveins: $q0, $q1, $q2, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: BUNDLE implicit-def dead $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: MVE_VPST 4, implicit $vpr @@ -80,7 +80,7 @@ ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: } - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 Index: llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir @@ -68,7 +68,7 @@ ; CHECK-LABEL: name: vpt_2_blocks ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $vpr, implicit killed $q2, implicit $q3, implicit killed $q0 { ; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 @@ -81,7 +81,7 @@ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: } ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2 Index: llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir @@ -66,7 +66,7 @@ ; CHECK-LABEL: name: vpt_3_blocks_kill_vpr ; CHECK: liveins: $q0, $q1, $q2, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 ; CHECK: BUNDLE implicit-def $q3, implicit-def $d6, implicit-def $s12, implicit-def $s13, implicit-def $d7, implicit-def $s14, implicit-def $s15, implicit $vpr, implicit killed $q1, implicit $q2, implicit killed $q3 { ; CHECK: MVE_VPST 8, implicit $vpr @@ -83,7 +83,7 @@ ; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: } - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg $q3 = MVE_VORR $q0, $q0, 0, $noreg, undef $q3 renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, killed renamable $q3 Index: llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir @@ -64,12 +64,12 @@ ; CHECK-LABEL: name: vpt_block_1_ins ; CHECK: liveins: $q0, $q1, $q2, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 { ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: } - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 tBX_RET 14, $noreg, implicit $q0 Index: llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir @@ -66,14 +66,14 @@ ; CHECK-LABEL: name: vpt_block_2_ins ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: BUNDLE implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 { ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: } ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, killed renamable $q0 renamable $q1 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 Index: llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir @@ -67,7 +67,7 @@ ; CHECK-LABEL: name: vpt_block_4_ins ; CHECK: liveins: $q0, $q1, $q2, $q3, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: BUNDLE implicit-def dead $q2, implicit-def $d4, implicit-def $s8, implicit-def $s9, implicit-def $d5, implicit-def $s10, implicit-def $s11, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit-def $q1, implicit-def $d2, implicit-def $s4, implicit-def $s5, implicit-def $d3, implicit-def $s6, implicit-def $s7, implicit killed $vpr, implicit killed $q2, implicit killed $q3, implicit killed $q0, implicit killed $q1 { ; CHECK: MVE_VPST 1, implicit $vpr ; CHECK: renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 @@ -76,7 +76,7 @@ ; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q0, killed renamable $q3, 1, killed renamable $vpr, killed renamable $q1 ; CHECK: } ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q3, 1, renamable $vpr, undef renamable $q2 renamable $q2 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q2, renamable $q2, 1, renamable $vpr, undef renamable $q2 Index: llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-block-fold-vcmp.mir @@ -98,15 +98,15 @@ ; CHECK-LABEL: name: foo ; CHECK: liveins: $q0, $r0, $r1, $r2, $lr - ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr + ; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 [always], $noreg, killed $r7, killed $lr ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 - ; CHECK: $r7 = frame-setup tMOVr killed $sp, 14, $noreg + ; CHECK: $r7 = frame-setup tMOVr killed $sp, 14 [always], $noreg ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_register $r7 - ; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14, $noreg :: (load 4 from %fixed-stack.2) - ; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14, $noreg :: (load 4 from %fixed-stack.1) - ; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14, $noreg :: (load 4 from %fixed-stack.0) + ; CHECK: renamable $r12 = t2LDRi12 $r7, 16, 14 [always], $noreg :: (load 4 from %fixed-stack.2) + ; CHECK: renamable $lr = t2LDRi12 $r7, 12, 14 [always], $noreg :: (load 4 from %fixed-stack.1) + ; CHECK: renamable $r3 = t2LDRi12 $r7, 8, 14 [always], $noreg :: (load 4 from %fixed-stack.0) ; CHECK: BUNDLE implicit-def $vpr, implicit-def dead $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit $q0, implicit $zr, implicit killed $r0, implicit killed $r3, implicit killed $r1, implicit killed $lr { ; CHECK: MVE_VPTv4f32r 1, renamable $q0, $zr, 10, implicit-def $vpr ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r0, 0, 1, internal renamable $vpr :: (load 16 from %ir.src, align 4) @@ -119,7 +119,7 @@ ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r2, 0, 1, renamable $vpr :: (load 16 from %ir.src3, align 4) ; CHECK: MVE_VSTRWU32 internal renamable $q0, killed renamable $r12, 0, 1, killed renamable $vpr :: (store 16 into %ir.dest3, align 4) ; CHECK: } - ; CHECK: $sp = t2LDMIA_RET $sp, 14, $noreg, def $r7, def $pc, implicit $q0 + ; CHECK: $sp = t2LDMIA_RET $sp, 14 [always], $noreg, def $r7, def $pc, implicit $q0 $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r7, killed $lr frame-setup CFI_INSTRUCTION def_cfa_offset 8 frame-setup CFI_INSTRUCTION offset $lr, -4 Index: llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-block-optnone.mir @@ -65,12 +65,12 @@ ; CHECK-LABEL: name: test_vminnmq_m_f32_v2 ; CHECK: liveins: $q0, $q1, $q2, $r0 - ; CHECK: $vpr = VMSR_P0 killed $r0, 14, $noreg + ; CHECK: $vpr = VMSR_P0 killed $r0, 14 [always], $noreg ; CHECK: BUNDLE implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $s1, implicit-def $d1, implicit-def $s2, implicit-def $s3, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q0 { ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 ; CHECK: } - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 $vpr = VMSR_P0 killed $r0, 14, $noreg renamable $q0 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, killed renamable $q0 tBX_RET 14, $noreg, implicit $q0 Index: llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir @@ -71,7 +71,7 @@ ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: } ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg @@ -105,7 +105,7 @@ ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: } ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 bb.0.entry: liveins: $q0, $q1, $q2 @@ -146,7 +146,7 @@ ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: } ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg @@ -184,7 +184,7 @@ ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, killed renamable $vpr ; CHECK: } ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg @@ -219,7 +219,7 @@ ; CHECK: renamable $vpr = MVE_VCMPi32r killed renamable $q2, $zr, 0, 1, internal killed renamable $vpr ; CHECK: } ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr @@ -255,7 +255,7 @@ ; CHECK: } ; CHECK: renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg ; CHECK: renamable $q0 = MVE_VPSEL killed renamable $q0, killed renamable $q1, 0, killed renamable $vpr - ; CHECK: tBX_RET 14, $noreg, implicit $q0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $q0 renamable $vpr = MVE_VCMPs32r renamable $q0, $zr, 11, 0, $noreg renamable $vpr = MVE_VPNOT killed renamable $vpr, 0, $noreg renamable $vpr = MVE_VCMPs32r renamable $q1, $zr, 12, 1, killed renamable $vpr Index: llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir =================================================================== --- llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir +++ llvm/test/CodeGen/Thumb2/mve-vpt-preuse.mir @@ -65,14 +65,14 @@ ; CHECK: successors: %bb.0(0x80000000) ; CHECK: liveins: $lr, $q0, $q1, $q2, $q3, $q4, $q5, $r0, $r1, $r2, $r7, $r8, $r9, $r10, $r11, $r12 ; CHECK: renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg - ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg - ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg + ; CHECK: renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14 [always], $noreg, $noreg + ; CHECK: VSTR_P0_off renamable $vpr, $sp, 0, 14 [always], $noreg ; CHECK: BUNDLE implicit-def $q6, implicit-def $d12, implicit-def $s24, implicit-def $s25, implicit-def $d13, implicit-def $s26, implicit-def $s27, implicit $vpr, implicit killed $r4 { ; CHECK: MVE_VPST 8, implicit $vpr ; CHECK: renamable $q6 = MVE_VLDRBU32 killed renamable $r4, 0, 1, renamable $vpr ; CHECK: } ; CHECK: t2LoopEnd renamable $lr, %bb.0, implicit-def dead $cpsr - ; CHECK: t2B %bb.0, 14, $noreg + ; CHECK: t2B %bb.0, 14 [always], $noreg renamable $vpr = MVE_VCMPu32 renamable $q1, renamable $q5, 2, 0, $noreg renamable $r4 = t2ADDrr renamable $r2, renamable $r10, 14, $noreg, $noreg VSTR_P0_off renamable $vpr, $sp, 0, 14, $noreg Index: llvm/test/CodeGen/Thumb2/peephole-addsub.mir =================================================================== --- llvm/test/CodeGen/Thumb2/peephole-addsub.mir +++ llvm/test/CodeGen/Thumb2/peephole-addsub.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s --- | target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" @@ -18,6 +19,16 @@ bb.0 (%ir-block.0): liveins: $r0, $r1 + ; CHECK-LABEL: name: test + ; CHECK: liveins: $r0, $r1 + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 1, 14 [always], $noreg, $noreg + ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY1]], [[COPY]], 14 [always], $noreg, $noreg + ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[t2ADDrr]], 0, 14 [always], $noreg, def $cpsr + ; CHECK: [[t2MOVCCi:%[0-9]+]]:rgpr = t2MOVCCi [[t2MOVi]], 0, 7 [nooverflow], $cpsr + ; CHECK: $r0 = COPY [[t2MOVCCi]] + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 %1:rgpr = COPY $r1 %0:rgpr = COPY $r0 %2:rgpr = t2MOVi 1, 14, $noreg, $noreg @@ -28,8 +39,4 @@ $r0 = COPY %5 tBX_RET 14, $noreg, implicit $r0 -# CHECK-LABEL: name: test -# CHECK: %3:gprnopc = t2ADDrr %0, %1, 14, $noreg, $noreg -# CHECK-NEXT: %4:rgpr = t2SUBri %3, 0, 14, $noreg, def $cpsr -# CHECK-NEXT: %5:rgpr = t2MOVCCi %2, 0, 7, $cpsr ... Index: llvm/test/CodeGen/Thumb2/peephole-cmp.mir =================================================================== --- llvm/test/CodeGen/Thumb2/peephole-cmp.mir +++ llvm/test/CodeGen/Thumb2/peephole-cmp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s --- | target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" @@ -18,6 +19,20 @@ local-offset: -4, debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } body: | + ; CHECK-LABEL: name: test_addir_frameindex + ; CHECK: bb.0: + ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) + ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0 + ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %stack.0.f, 0, 14 [always], $noreg, $noreg + ; CHECK: t2CMPrr [[t2ADDri]], [[COPY]], 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.2, 3 [lower], $cpsr + ; CHECK: t2B %bb.1, 14 [always], $noreg + ; CHECK: bb.1: + ; CHECK: $r0 = COPY [[t2ADDri]] + ; CHECK: tBX_RET 14 [always], $noreg + ; CHECK: bb.2: + ; CHECK: $r0 = COPY [[COPY]] + ; CHECK: tBX_RET 14 [always], $noreg bb.0: successors: %bb.2(0x40000000), %bb.1(0x40000000) liveins: $r0 @@ -36,8 +51,4 @@ $r0 = COPY %0 tBX_RET 14, $noreg -# CHECK-LABEL: name: test_addir_frameindex -# CHECK: %1:rgpr = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg -# CHECK-NEXT: t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr -# CHECK-NEXT: t2Bcc %bb.2, 3, $cpsr ... Index: llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir =================================================================== --- llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir +++ llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir @@ -100,38 +100,38 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: t2B %bb.2, 14, $noreg + ; CHECK: t2B %bb.2, 14 [always], $noreg ; CHECK: bb.1.while.body.end: ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i.14) - ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.next.i.14) + ; CHECK: tCMPi8 renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: BUNDLE implicit-def dead $itstate, implicit killed $cpsr, implicit $r0 { ; CHECK: t2IT 0, 8, implicit-def $itstate - ; CHECK: tBX_RET 0, killed $cpsr, implicit $r0, implicit internal killed $itstate + ; CHECK: tBX_RET 0 [equal], killed $cpsr, implicit $r0, implicit internal killed $itstate ; CHECK: } ; CHECK: bb.2.while.begin: ; CHECK: successors: %bb.4(0x04000000), %bb.3(0x7c000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14, $noreg :: (load 4 from %ir.info.i) - ; CHECK: renamable $r2 = tLDRHi killed renamable $r2, 0, 14, $noreg :: (load 2 from %ir.data16.i1) - ; CHECK: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14, $noreg - ; CHECK: t2Bcc %bb.4, 0, killed $cpsr + ; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 14 [always], $noreg :: (load 4 from %ir.info.i) + ; CHECK: renamable $r2 = tLDRHi killed renamable $r2, 0, 14 [always], $noreg :: (load 2 from %ir.data16.i1) + ; CHECK: dead renamable $r2, $cpsr = tEOR killed renamable $r2, renamable $r1, 14 [always], $noreg + ; CHECK: t2Bcc %bb.4, 0 [equal], killed $cpsr ; CHECK: bb.3.while.body.a: ; CHECK: successors: %bb.4(0x4207fef8), %bb.1(0x3df80108) ; CHECK: liveins: $r0, $r1 - ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg :: (load 4 from %ir.next.i2) - ; CHECK: tCMPi8 renamable $r0, 0, 14, $noreg, implicit-def $cpsr + ; CHECK: renamable $r0 = tLDRi killed renamable $r0, 0, 14 [always], $noreg :: (load 4 from %ir.next.i2) + ; CHECK: tCMPi8 renamable $r0, 0, 14 [always], $noreg, implicit-def $cpsr ; CHECK: BUNDLE implicit-def dead $itstate, implicit-def dead $r2, implicit-def $cpsr, implicit $r0, implicit killed $cpsr, implicit $r1 { ; CHECK: t2IT 1, 30, implicit-def $itstate - ; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 1, $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1) - ; CHECK: renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1, $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13) - ; CHECK: t2TEQrr internal killed renamable $r2, renamable $r1, 1, killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate + ; CHECK: renamable $r2 = tLDRi renamable $r0, 1, 1 [notequal], $cpsr, implicit internal $itstate :: (load 4 from %ir.info.i.1) + ; CHECK: renamable $r2 = tLDRHi internal killed renamable $r2, 0, 1 [notequal], $cpsr, implicit internal killed $r2, implicit internal $itstate :: (load 2 from %ir.data16.i.13) + ; CHECK: t2TEQrr internal killed renamable $r2, renamable $r1, 1 [notequal], killed $cpsr, implicit-def $cpsr, implicit internal killed $itstate ; CHECK: } - ; CHECK: t2Bcc %bb.1, 1, killed $cpsr + ; CHECK: t2Bcc %bb.1, 1 [notequal], killed $cpsr ; CHECK: bb.4.exit: ; CHECK: liveins: $r0 - ; CHECK: tBX_RET 14, $noreg, implicit killed $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit killed $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1 @@ -189,36 +189,36 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x80000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: $r2 = tMOVr $r0, 14, $noreg + ; CHECK: $r2 = tMOVr $r0, 14 [always], $noreg ; CHECK: bb.1.while.begin: ; CHECK: successors: %bb.5(0x04000000), %bb.2(0x7c000000) ; CHECK: liveins: $r1, $r2 - ; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14, $noreg :: (load 4 from %ir.info.i) - ; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i1) - ; CHECK: t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.5, 0, killed $cpsr + ; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14 [always], $noreg :: (load 4 from %ir.info.i) + ; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14 [always], $noreg :: (load 2 from %ir.data16.i1) + ; CHECK: t2TEQrr renamable $r0, renamable $r1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.5, 0 [equal], killed $cpsr ; CHECK: bb.2.while.body.a: ; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i2) - ; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.5, 0, killed $cpsr + ; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14 [always], $noreg :: (load 4 from %ir.next.i2) + ; CHECK: tCMPi8 renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.5, 0 [equal], killed $cpsr ; CHECK: bb.3.it.block: ; CHECK: successors: %bb.5(0x04000000), %bb.4(0x7c000000) ; CHECK: liveins: $r1, $r2 - ; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14, $noreg :: (load 4 from %ir.info.i.1) - ; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14, $noreg :: (load 2 from %ir.data16.i.13) - ; CHECK: t2TEQrr renamable $r0, renamable $r1, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.5, 0, killed $cpsr + ; CHECK: renamable $r0 = tLDRi renamable $r2, 1, 14 [always], $noreg :: (load 4 from %ir.info.i.1) + ; CHECK: renamable $r0 = tLDRHi killed renamable $r0, 0, 14 [always], $noreg :: (load 2 from %ir.data16.i.13) + ; CHECK: t2TEQrr renamable $r0, renamable $r1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.5, 0 [equal], killed $cpsr ; CHECK: bb.4.while.body.end: ; CHECK: successors: %bb.5(0x04000000), %bb.1(0x7c000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14, $noreg :: (load 4 from %ir.next.i.14) - ; CHECK: tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.1, 1, killed $cpsr + ; CHECK: renamable $r2 = tLDRi killed renamable $r2, 0, 14 [always], $noreg :: (load 4 from %ir.next.i.14) + ; CHECK: tCMPi8 renamable $r2, 0, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.1, 1 [notequal], killed $cpsr ; CHECK: bb.5.exit: ; CHECK: liveins: $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0.entry: successors: %bb.1(0x80000000) liveins: $r0, $r1 Index: llvm/test/CodeGen/Thumb2/t2sizereduction.mir =================================================================== --- llvm/test/CodeGen/Thumb2/t2sizereduction.mir +++ llvm/test/CodeGen/Thumb2/t2sizereduction.mir @@ -43,20 +43,20 @@ ; CHECK: bb.0.entry: ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK: liveins: $r0, $r1 - ; CHECK: $r2 = tMOVr $r0, 14, $noreg - ; CHECK: $r0, dead $cpsr = tMOVi8 1, 14, $noreg - ; CHECK: tCMPi8 $r1, 1, 14, $noreg, implicit-def $cpsr - ; CHECK: t2Bcc %bb.2, 11, killed $cpsr + ; CHECK: $r2 = tMOVr $r0, 14 [always], $noreg + ; CHECK: $r0, dead $cpsr = tMOVi8 1, 14 [always], $noreg + ; CHECK: tCMPi8 $r1, 1, 14 [always], $noreg, implicit-def $cpsr + ; CHECK: t2Bcc %bb.2, 11 [less], killed $cpsr ; CHECK: bb.1.for.body: ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) ; CHECK: liveins: $r0, $r1, $r2 - ; CHECK: $r0, dead $cpsr = tMUL $r2, killed $r0, 14, $noreg - ; CHECK: $r2, dead $cpsr = tADDi8 killed $r2, 1, 14, $noreg - ; CHECK: $r1, $cpsr = tSUBi8 killed $r1, 1, 14, $noreg - ; CHECK: t2Bcc %bb.1, 1, killed $cpsr + ; CHECK: $r0, dead $cpsr = tMUL $r2, killed $r0, 14 [always], $noreg + ; CHECK: $r2, dead $cpsr = tADDi8 killed $r2, 1, 14 [always], $noreg + ; CHECK: $r1, $cpsr = tSUBi8 killed $r1, 1, 14 [always], $noreg + ; CHECK: t2Bcc %bb.1, 1 [notequal], killed $cpsr ; CHECK: bb.2.for.cond.cleanup: ; CHECK: liveins: $r0 - ; CHECK: tBX_RET 14, $noreg, implicit $r0 + ; CHECK: tBX_RET 14 [always], $noreg, implicit $r0 bb.0.entry: successors: %bb.1.for.body, %bb.2.for.cond.cleanup liveins: $r0, $r1 Index: llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir =================================================================== --- llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir +++ llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir @@ -6,7 +6,7 @@ # # CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1" # CHECK: DBG_VALUE $r4, $noreg, ![[ARG1]], !DIExpression(), debug-location -# CHECK: $r5 = MOVr killed $r4, 14, $noreg, $noreg, debug-location +# CHECK: $r5 = MOVr killed $r4, 14 [always], $noreg, $noreg, debug-location # CHECK-NEXT: DBG_VALUE $r5, $noreg, ![[ARG1]], !DIExpression(), debug-location --- | ; ModuleID = 'live-debug-values-reg-copy.ll'