Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6964,47 +6964,70 @@
MachineFunction &MF = DAG.getMachineFunction();
CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
+ const EVT PtrVT = getPointerTy(MF.getDataLayout());
// Reserve space for the linkage area on the stack.
const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
- // On AIX a minimum of 8 words is saved to the parameter save area.
- const unsigned MinParameterSaveArea = 8 * PtrByteSize;
- CCInfo.AllocateStack(LinkageSize + MinParameterSaveArea, PtrByteSize);
+ CCInfo.AllocateStack(LinkageSize, PtrByteSize);
CCInfo.AnalyzeFormalArguments(Ins, CC_AIX);
for (CCValAssign &VA : ArgLocs) {
-
- if (VA.isMemLoc()) {
- // For compatibility with the AIX XL compiler, the float args in the
- // parameter save area are initialized even if the argument is available
- // in register. The caller is required to initialize both the register
- // and memory, however, the callee can choose to expect it in either. The
- // memloc is dismissed here because the argument is retrieved from the
- // register.
- if (VA.needsCustom())
- continue;
- report_fatal_error(
- "Handling of formal arguments on the stack is unimplemented!");
- }
-
- assert(VA.isRegLoc() && "Unexpected argument location.");
-
EVT ValVT = VA.getValVT();
MVT LocVT = VA.getLocVT();
- MVT::SimpleValueType SVT = ValVT.getSimpleVT().SimpleTy;
- unsigned VReg =
- MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
- SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
- if (ValVT.isScalarInteger() &&
- (ValVT.getSizeInBits() < LocVT.getSizeInBits())) {
- ISD::ArgFlagsTy Flags = Ins[VA.getValNo()].Flags;
- ArgValue =
- truncateScalarIntegerArg(Flags, ValVT, DAG, ArgValue, LocVT, dl);
+ ISD::ArgFlagsTy Flags = Ins[VA.getValNo()].Flags;
+ assert(!Flags.isByVal() &&
+ "Passing structure by value is unimplemented for formal arguments.");
+ assert((VA.isRegLoc() || VA.isMemLoc()) &&
+ "Unexpected location for function call argument.");
+
+ // For compatibility with the AIX XL compiler, the float args in the
+ // parameter save area are initialized even if the argument is available
+ // in register. The caller is required to initialize both the register
+ // and memory, however, the callee can choose to expect it in either.
+ // The memloc is dismissed here because the argument is retrieved from
+ // the register.
+ if (VA.isMemLoc() && VA.needsCustom())
+ continue;
+
+ if (VA.isRegLoc()) {
+ MVT::SimpleValueType SVT = ValVT.getSimpleVT().SimpleTy;
+ unsigned VReg =
+ MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+ SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
+ if (ValVT.isScalarInteger() &&
+ (ValVT.getSizeInBits() < LocVT.getSizeInBits())) {
+ ArgValue =
+ truncateScalarIntegerArg(Flags, ValVT, DAG, ArgValue, LocVT, dl);
+ }
+ InVals.push_back(ArgValue);
+ } else {
+ assert(VA.isMemLoc());
+ // Get the extended size of the argument type in stack.
+ const unsigned ArgSize = VA.getLocVT().getStoreSize();
+ // Get the actual size of the argument type.
+ const unsigned ObjSize = VA.getValVT().getStoreSize();
+ assert(ObjSize <= ArgSize);
+ int CurArgOffset = VA.getLocMemOffset();
+ // Objects in AIX are right justified.
+ if (ArgSize < ObjSize)
+ CurArgOffset += ArgSize - ObjSize;
+ MachineFrameInfo &MFI = MF.getFrameInfo();
+ // Potential tail calls could cause overwriting of argument stack slots.
+ const bool IsImmutable =
+ !(getTargetMachine().Options.GuaranteedTailCallOpt &&
+ (CallConv == CallingConv::Fast));
+ int FI = MFI.CreateFixedObject(ArgSize, CurArgOffset, IsImmutable);
+ SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
+ SDValue ArgValue =
+ DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo());
+ InVals.push_back(ArgValue);
}
- InVals.push_back(ArgValue);
}
+ // On AIX a minimum of 8 words is saved to the parameter save area.
+ const unsigned MinParameterSaveArea = 8 * PtrByteSize;
// Area that is at least reserved in the caller of this function.
- unsigned MinReservedArea = CCInfo.getNextStackOffset();
+ unsigned MinReservedArea =
+ std::max(CCInfo.getNextStackOffset(), LinkageSize + MinParameterSaveArea);
// Set the size that is at least reserved in caller of this function. Tail
// call optimized function's reserved stack space needs to be aligned so
Index: llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1266,3 +1266,996 @@
; ASM64PWR4-NEXT: bl .test_stackarg_float3
; ASM64PWR4-NEXT: nop
; ASM64PWR4-NEXT: addi 1, 1, 128
+
+
+define i32 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i64 %ll9, i16 signext %s10, i8 zeroext %c11, i32 %ui12, i32 %si13, i64 %ll14, i8 zeroext %uc15, i32 %i16) {
+entry:
+ %add = add nsw i32 %i1, %i2
+ %add1 = add nsw i32 %add, %i3
+ %add2 = add nsw i32 %add1, %i4
+ %add3 = add nsw i32 %add2, %i5
+ %add4 = add nsw i32 %add3, %i6
+ %add5 = add nsw i32 %add4, %i7
+ %add6 = add nsw i32 %add5, %i8
+ %conv = sext i32 %add6 to i64
+ %add7 = add nsw i64 %conv, %ll9
+ %conv8 = sext i16 %s10 to i64
+ %add9 = add nsw i64 %add7, %conv8
+ %conv10 = zext i8 %c11 to i64
+ %add11 = add nsw i64 %add9, %conv10
+ %conv12 = zext i32 %ui12 to i64
+ %add13 = add nsw i64 %add11, %conv12
+ %conv14 = sext i32 %si13 to i64
+ %add15 = add nsw i64 %add13, %conv14
+ %add16 = add nsw i64 %add15, %ll14
+ %conv17 = zext i8 %uc15 to i64
+ %add18 = add nsw i64 %add16, %conv17
+ %conv19 = sext i32 %i16 to i64
+ %add20 = add nsw i64 %add18, %conv19
+ %conv21 = trunc i64 %add20 to i32
+ ret i32 %conv21
+}
+
+; CHECK-LABEL: name: test_ints_stack
+
+; 32BIT-DAG: liveins:
+; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' }
+
+; 32BIT-DAG: fixedStack:
+; 32BIT-DAG: - { id: 9, type: default, offset: 56, size: 4
+; 32BIT-DAG: - { id: 8, type: default, offset: 60, size: 4
+; 32BIT-DAG: - { id: 7, type: default, offset: 64, size: 4
+; 32BIT-DAG: - { id: 6, type: default, offset: 68, size: 4
+; 32BIT-DAG: - { id: 5, type: default, offset: 72, size: 4
+; 32BIT-DAG: - { id: 4, type: default, offset: 76, size: 4
+; 32BIT-DAG: - { id: 3, type: default, offset: 80, size: 4
+; 32BIT-DAG: - { id: 2, type: default, offset: 84, size: 4
+; 32BIT-DAG: - { id: 1, type: default, offset: 88, size: 4
+; 32BIT-DAG: - { id: 0, type: default, offset: 92, size: 4
+
+; 32BIT-DAG: body: |
+; 32BIT-DAG: bb.0.entry:
+; 32BIT-NEXT: liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+
+; 64BIT-DAG: liveins:
+; 64BIT-DAG: - { reg: '$x3', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x5', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x6', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x10', virtual-reg: '' }
+
+; 64BIT-DAG: fixedStack:
+; 64BIT-DAG: - { id: 7, type: default, offset: 112, size: 8
+; 64BIT-DAG: - { id: 6, type: default, offset: 120, size: 8
+; 64BIT-DAG: - { id: 5, type: default, offset: 128, size: 8
+; 64BIT-DAG: - { id: 4, type: default, offset: 136, size: 8
+; 64BIT-DAG: - { id: 3, type: default, offset: 144, size: 8
+; 64BIT-DAG: - { id: 2, type: default, offset: 152, size: 8
+; 64BIT-DAG: - { id: 1, type: default, offset: 160, size: 8
+; 64BIT-DAG: - { id: 0, type: default, offset: 168, size: 8
+; 64BIT-DAG: body: |
+; 64BIT-DAG: bb.0.entry:
+; 64BIT-NEXT: liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+
+; ASM32PWR4-DAG: add 3, 3, 4
+; ASM32PWR4-DAG: lwz [[REG1:[0-9]+]], 60(1)
+; ASM32PWR4-DAG: add 3, 3, 5
+; ASM32PWR4-DAG: add 3, 3, 6
+; ASM32PWR4-DAG: add 3, 3, 7
+; ASM32PWR4-DAG: lwz [[REG2:[0-9]+]], 64(1)
+; ASM32PWR4-DAG: add 3, 3, 8
+; ASM32PWR4-DAG: add 3, 3, 9
+; ASM32PWR4-DAG: lwz [[REG3:[0-9]+]], 68(1)
+; ASM32PWR4-DAG: add 3, 3, 10
+; ASM32PWR4-DAG: add 3, 3, [[REG1]]
+; ASM32PWR4-DAG: add 3, 3, [[REG2]]
+; ASM32PWR4-DAG: lwz [[REG4:[0-9]+]], 72(1)
+; ASM32PWR4-DAG: add 3, 3, [[REG3]]
+; ASM32PWR4-DAG: lwz [[REG5:[0-9]+]], 76(1)
+; ASM32PWR4-DAG: add 3, 3, [[REG4]]
+; ASM32PWR4-DAG: lwz [[REG6:[0-9]+]], 84(1)
+; ASM32PWR4-DAG: add 3, 3, [[REG5]]
+; ASM32PWR4-DAG: lwz [[REG7:[0-9]+]], 88(1)
+; ASM32PWR4-DAG: add 3, 3, [[REG6]]
+; ASM32PWR4-DAG: lwz [[REG8:[0-9]+]], 92(1)
+; ASM32PWR4-DAG: add 3, 3, [[REG7]]
+; ASM32PWR4-DAG: add 3, 3, [[REG8]]
+
+; ASM64PWR4-DAG: add 3, 3, 4
+; ASM64PWR4-DAG: ld [[REG1:[0-9]+]], 112(1)
+; ASM64PWR4-DAG: add 3, 3, 5
+; ASM64PWR4-DAG: add 3, 3, 6
+; ASM64PWR4-DAG: add 3, 3, 7
+; ASM64PWR4-DAG: ld [[REG2:[0-9]+]], 120(1)
+; ASM64PWR4-DAG: add 3, 3, 8
+; ASM64PWR4-DAG: add 3, 3, 9
+; ASM64PWR4-DAG: add 3, 3, 10
+; ASM64PWR4-DAG: std 30, -8(1)
+; ASM64PWR4-DAG: extsw 3, 3
+; ASM64PWR4-DAG: add 3, 3, [[REG1]]
+; ASM64PWR4-DAG: ld [[REG3:[0-9]+]], 128(1)
+; ASM64PWR4-DAG: add 3, 3, [[REG2]]
+; ASM64PWR4-DAG: lwz [[REG4:[0-9]+]], 140(1)
+; ASM64PWR4-DAG: add 3, 3, [[REG3]]
+; ASM64PWR4-DAG: lwa [[REG5:[0-9]+]], 148(1)
+; ASM64PWR4-DAG: add 3, 3, [[REG4]]
+; ASM64PWR4-DAG: add 3, 3, [[REG5]]
+; ASM64PWR4-DAG: ld [[REG6:[0-9]+]], 152(1)
+; ASM64PWR4-DAG: ld [[REG7:[0-9]+]], 160(1)
+; ASM64PWR4-DAG: add 3, 3, [[REG6]]
+; ASM64PWR4-DAG: lwa [[REG8:[0-9]+]], 172(1)
+; ASM64PWR4-DAG: add 3, 3, [[REG7]]
+; ASM64PWR4-DAG: add 3, 3, [[REG8]]
+; ASM64PWR4-DAG: ld 30, -8(1)
+
+@ll1 = common global i64 0, align 8
+@si1 = common global i16 0, align 2
+@ch = common global i8 0, align 1
+@ui = common global i32 0, align 4
+@sint = common global i32 0, align 4
+@ll2 = common global i64 0, align 8
+@uc1 = common global i8 0, align 1
+@i1 = common global i32 0, align 4
+
+define void @caller_ints_stack() {
+entry:
+ %0 = load i64, i64* @ll1, align 8
+ %1 = load i16, i16* @si1, align 2
+ %2 = load i8, i8* @ch, align 1
+ %3 = load i32, i32* @ui, align 4
+ %4 = load i32, i32* @sint, align 4
+ %5 = load i64, i64* @ll2, align 8
+ %6 = load i8, i8* @uc1, align 1
+ %7 = load i32, i32* @i1, align 4
+ %call = call i32 @test_ints_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i64 %0, i16 signext %1, i8 zeroext %2, i32 %3, i32 %4, i64 %5, i8 zeroext %6, i32 %7)
+ ret void
+}
+
+; CHECK-LABEL: name: caller_ints_stack
+
+; 32BIT-DAG: renamable $r[[REGLL1ADDR:[0-9]+]] = LWZtoc @ll1, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGSADDR:[0-9]+]] = LWZtoc @si1, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGCADDR:[0-9]+]] = LWZtoc @ch, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGUIADDR:[0-9]+]] = LWZtoc @ui, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGSIADDR:[0-9]+]] = LWZtoc @sint, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGLL2ADDR:[0-9]+]] = LWZtoc @ll2, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGUCADDR:[0-9]+]] = LWZtoc @uc1, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r[[REGIADDR:[0-9]+]] = LWZtoc @i1, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r11 = LWZ 0, renamable $r[[REGLL1ADDR]] :: (dereferenceable load 4 from @ll1, align 8)
+; 32BIT-DAG: renamable $r3 = LWZ 4, killed renamable $r[[REGLL1ADDR]] :: (dereferenceable load 4 from @ll1 + 4)
+; 32BIT-DAG: renamable $r4 = LHA 0, killed renamable $r[[REGSADDR]] :: (dereferenceable load 2 from @si1)
+; 32BIT-DAG: renamable $r5 = LBZ 0, killed renamable $r[[REGCADDR]] :: (dereferenceable load 1 from @ch)
+; 32BIT-DAG: renamable $r6 = LWZ 0, killed renamable $r[[REGUIADDR]] :: (dereferenceable load 4 from @ui)
+; 32BIT-DAG: renamable $r7 = LWZ 0, killed renamable $r[[REGSIADDR]] :: (dereferenceable load 4 from @sint)
+; 32BIT-DAG: renamable $r12 = LWZ 0, renamable $r[[REGLL2ADDR]] :: (dereferenceable load 4 from @ll2, align 8)
+; 32BIT-DAG: renamable $r8 = LWZ 4, killed renamable $r[[REGLL2ADDR]] :: (dereferenceable load 4 from @ll2 + 4)
+; 32BIT-DAG: renamable $r9 = LBZ 0, killed renamable $r[[REGUCADDR]] :: (dereferenceable load 1 from @uc1)
+; 32BIT-DAG: renamable $r10 = LWZ 0, killed renamable $r[[REGIADDR]] :: (dereferenceable load 4 from @i1)
+; 32BIT-NEXT: ADJCALLSTACKDOWN 96, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-DAG: STW killed renamable $r11, 56, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r3, 60, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r4, 64, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r5, 68, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r6, 72, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r7, 76, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r12, 80, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 84, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r9, 88, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r10, 92, $r1 :: (store 4)
+; 32BIT-DAG: $r3 = LI 1
+; 32BIT-DAG: $r4 = LI 2
+; 32BIT-DAG: $r5 = LI 3
+; 32BIT-DAG: $r6 = LI 4
+; 32BIT-DAG: $r7 = LI 5
+; 32BIT-DAG: $r8 = LI 6
+; 32BIT-DAG: $r9 = LI 7
+; 32BIT-DAG: $r10 = LI 8
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_ints_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1, implicit-def dead $r3
+; 32BIT-NEXT: ADJCALLSTACKUP 96, 0, implicit-def dead $r1, implicit $r1
+
+; CHECKASM-LABEL: .caller_ints_stack:
+
+; ASM32PWR4: mflr 0
+; ASM32PWR4-DAG: stw 0, 8(1)
+; ASM32PWR4-DAG: stwu 1, -96(1)
+; ASM32PWR4-DAG: lwz [[REG1:[0-9]+]], LC10(2)
+; ASM32PWR4-DAG: lwz [[REG2:[0-9]+]], LC11(2)
+; ASM32PWR4-DAG: lwz [[REG3:[0-9]+]], LC12(2)
+; ASM32PWR4-DAG: lwz [[REG4:[0-9]+]], LC13(2)
+; ASM32PWR4-DAG: lwz [[REG5:[0-9]+]], LC14(2)
+; ASM32PWR4-DAG: lwz [[REG6:[0-9]+]], LC15(2)
+; ASM32PWR4-DAG: lwz [[REG7:[0-9]+]], LC16(2)
+; ASM32PWR4-DAG: lwz [[REG8:[0-9]+]], LC17(2)
+; ASM32PWR4-DAG: lha 5, 0([[REG1]])
+; ASM32PWR4-DAG: lwz 11, 0([[REG7]])
+; ASM32PWR4-DAG: lwz 7, 4([[REG7]])
+; ASM32PWR4-DAG: lbz 4, 0([[REG2]])
+; ASM32PWR4-DAG: lwz 3, 0([[REG8]])
+; ASM32PWR4-DAG: lwz 6, 0([[REG3]])
+; ASM32PWR4-DAG: lwz 9, 0([[REG4]])
+; ASM32PWR4-DAG: lwz 8, 4([[REG4]])
+; ASM32PWR4-DAG: lbz 10, 0([[REG5]])
+; ASM32PWR4-DAG: lwz 12, 0([[REG6]])
+; ASM32PWR4-DAG: stw 11, 56(1)
+; ASM32PWR4-DAG: stw 7, 60(1)
+; ASM32PWR4-DAG: stw 5, 64(1)
+; ASM32PWR4-DAG: stw 4, 68(1)
+; ASM32PWR4-DAG: stw 3, 72(1)
+; ASM32PWR4-DAG: stw 6, 76(1)
+; ASM32PWR4-DAG: stw 9, 80(1)
+; ASM32PWR4-DAG: stw 8, 84(1)
+; ASM32PWR4-DAG: stw 10, 88(1)
+; ASM32PWR4-DAG: stw 12, 92(1)
+; ASM32PWR4-DAG: li 3, 1
+; ASM32PWR4-DAG: li 4, 2
+; ASM32PWR4-DAG: li 5, 3
+; ASM32PWR4-DAG: li 6, 4
+; ASM32PWR4-DAG: li 7, 5
+; ASM32PWR4-DAG: li 9, 7
+; ASM32PWR4-DAG: li 8, 6
+; ASM32PWR4-DAG: li 10, 8
+; ASM32PWR4-DAG: bl .test_ints_stack
+; ASM32PWR4-DAG: nop
+; ASM32PWR4-DAG: addi 1, 1, 96
+; ASM32PWR4-DAG: lwz 0, 8(1)
+; ASM32PWR4-NEXT: mtlr 0
+; ASM32PWR4-NEXT: blr
+
+; ASM64PWR4: mflr 0
+; ASM64PWR4-DAG: std 0, 16(1)
+; ASM64PWR4-DAG: stdu 1, -176(1)
+; ASM64PWR4-DAG: ld [[REG1:[0-9]+]], LC9(2)
+; ASM64PWR4-DAG: ld [[REG2:[0-9]+]], LC10(2)
+; ASM64PWR4-DAG: ld [[REG3:[0-9]+]], LC11(2)
+; ASM64PWR4-DAG: ld [[REG4:[0-9]+]], LC12(2)
+; ASM64PWR4-DAG: ld [[REG5:[0-9]+]], LC13(2)
+; ASM64PWR4-DAG: ld [[REG6:[0-9]+]], LC14(2)
+; ASM64PWR4-DAG: ld [[REG7:[0-9]+]], LC15(2)
+; ASM64PWR4-DAG: ld [[REG8:[0-9]+]], LC16(2)
+; ASM64PWR4-DAG: lha 7, 0([[REG1]])
+; ASM64PWR4-DAG: lbz 5, 0([[REG2]])
+; ASM64PWR4-DAG: ld 6, 0([[REG3]])
+; ASM64PWR4-DAG: lbz 8, 0([[REG4]])
+; ASM64PWR4-DAG: lwz 9, 0([[REG5]])
+; ASM64PWR4-DAG: ld 11, 0([[REG6]])
+; ASM64PWR4-DAG: lwz 3, 0([[REG7]])
+; ASM64PWR4-DAG: lwz 4, 0([[REG8]])
+; ASM64PWR4-DAG: std 11, 112(1)
+; ASM64PWR4-DAG: stw 7, 120(1)
+; ASM64PWR4-DAG: stw 5, 128(1)
+; ASM64PWR4-DAG: stw 3, 136(1)
+; ASM64PWR4-DAG: stw 4, 144(1)
+; ASM64PWR4-DAG: std 6, 152(1)
+; ASM64PWR4-DAG: stw 8, 160(1)
+; ASM64PWR4-DAG: stw 9, 168(1)
+; ASM64PWR4-DAG: li 3, 1
+; ASM64PWR4-DAG: li 4, 2
+; ASM64PWR4-DAG: li 5, 3
+; ASM64PWR4-DAG: li 6, 4
+; ASM64PWR4-DAG: li 7, 5
+; ASM64PWR4-DAG: li 8, 6
+; ASM64PWR4-DAG: li 9, 7
+; ASM64PWR4-DAG: li 10, 8
+; ASM64PWR4-NEXT: bl .test_ints_stack
+; ASM64PWR4-NEXT: nop
+; ASM64PWR4-NEXT: addi 1, 1, 176
+; ASM64PWR4-NEXT: ld 0, 16(1)
+; ASM64PWR4-NEXT: mtlr 0
+; ASM64PWR4-NEXT: blr
+
+define double @test_fpr_stack(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %s10, double %l11, double %d12, double %d13, float %f14, double %d15, float %f16) {
+ entry:
+ %add = fadd double %d1, %d2
+ %add1 = fadd double %add, %d3
+ %add2 = fadd double %add1, %d4
+ %add3 = fadd double %add2, %d5
+ %add4 = fadd double %add3, %d6
+ %add5 = fadd double %add4, %d7
+ %add6 = fadd double %add5, %d8
+ %add7 = fadd double %add6, %d9
+ %add8 = fadd double %add7, %s10
+ %add9 = fadd double %add8, %l11
+ %add10 = fadd double %add9, %d12
+ %add11 = fadd double %add10, %d13
+ %add12 = fadd double %add11, %d13
+ %conv = fpext float %f14 to double
+ %add13 = fadd double %add12, %conv
+ %add14 = fadd double %add13, %d15
+ %conv15 = fpext float %f16 to double
+ %add16 = fadd double %add14, %conv15
+ ret double %add16
+ }
+
+; CHECK-LABEL: name: test_fpr_stack{{.*}}
+
+; CHECK-DAG: liveins:
+; CHECK-DAG: - { reg: '$f1', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f2', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f3', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f4', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f5', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f6', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f7', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f8', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f9', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f10', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f11', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f12', virtual-reg: '' }
+; CHECK-DAG: - { reg: '$f13', virtual-reg: '' }
+
+; CHECK: fixedStack:
+; 32BIT-DAG: - { id: 2, type: default, offset: 128, size: 4
+; 32BIT-DAG: - { id: 1, type: default, offset: 132, size: 8
+; 32BIT-DAG: - { id: 0, type: default, offset: 140, size: 4
+
+; 64BIT-DAG: - { id: 2, type: default, offset: 152, size: 4
+; 64BIT-DAG: - { id: 1, type: default, offset: 160, size: 8
+; 64BIT-DAG: - { id: 0, type: default, offset: 168, size: 4
+
+; CHECK: body: |
+; CHECK-DAG: bb.0.entry:
+; CHECK-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
+
+; CHECKASM-LABEL: .test_fpr_stack:
+; ASM32PWR4: fadd 0, 1, 2
+; ASM32PWR4-DAG: lfs [[REG1:[0-9]+]], 128(1)
+; ASM32PWR4-DAG: fadd 0, 0, 3
+; ASM32PWR4-DAG: lfd [[REG2:[0-9]+]], 132(1)
+; ASM32PWR4-DAG: fadd 0, 0, 4
+; ASM32PWR4-DAG: fadd 0, 0, 5
+; ASM32PWR4-DAG: fadd 0, 0, 6
+; ASM32PWR4-DAG: fadd 0, 0, 7
+; ASM32PWR4-DAG: fadd 0, 0, 8
+; ASM32PWR4-DAG: fadd 0, 0, 9
+; ASM32PWR4-DAG: fadd 0, 0, 10
+; ASM32PWR4-DAG: fadd 0, 0, 11
+; ASM32PWR4-DAG: fadd 0, 0, 12
+; ASM32PWR4-DAG: fadd 0, 0, 13
+; ASM32PWR4-DAG: fadd 0, 0, 13
+; ASM32PWR4-DAG: fadd 0, 0, [[REG1]]
+; ASM32PWR4-DAG: lfs [[REG3:[0-9]+]], 140(1)
+; ASM32PWR4-DAG: fadd 0, 0, [[REG2]]
+; ASM32PWR4-DAG: fadd 1, 0, [[REG3]]
+
+; ASM64PWR4: fadd 0, 1, 2
+; ASM64PWR4-DAG: lfs [[REG1:[0-9]+]], 152(1)
+; ASM64PWR4-DAG: fadd 0, 0, 3
+; ASM64PWR4-DAG: lfd [[REG2:[0-9]+]], 160(1)
+; ASM64PWR4-DAG: fadd 0, 0, 4
+; ASM64PWR4-DAG: fadd 0, 0, 5
+; ASM64PWR4-DAG: fadd 0, 0, 6
+; ASM64PWR4-DAG: fadd 0, 0, 7
+; ASM64PWR4-DAG: fadd 0, 0, 8
+; ASM64PWR4-DAG: fadd 0, 0, 9
+; ASM64PWR4-DAG: fadd 0, 0, 10
+; ASM64PWR4-DAG: fadd 0, 0, 11
+; ASM64PWR4-DAG: fadd 0, 0, 12
+; ASM64PWR4-DAG: fadd 0, 0, 13
+; ASM64PWR4-DAG: fadd 0, 0, 13
+; ASM64PWR4-DAG: fadd 0, 0, [[REG1]]
+; ASM64PWR4-DAG: lfs [[REG3:[0-9]+]], 168(1)
+; ASM64PWR4-DAG: fadd 0, 0, [[REG2]]
+; ASM64PWR4-DAG: fadd 1, 0, [[REG3]]
+
+@f14 = common global float 0.000000e+00, align 4
+@d15 = common global double 0.000000e+00, align 8
+@f16 = common global float 0.000000e+00, align 4
+
+define void @caller_fpr_stack() {
+entry:
+ %0 = load float, float* @f14, align 4
+ %1 = load double, double* @d15, align 8
+ %2 = load float, float* @f16, align 4
+ %call = call double @test_fpr_stack(double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 0x3FE6666666666666, double 8.000000e-01, double 9.000000e-01, double 1.000000e-01, double 1.100000e-01, double 1.200000e-01, double 1.300000e-01, float %0, double %1, float %2)
+ ret void
+}
+
+; 32BIT-DAG: ADJCALLSTACKDOWN 144, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-DAG: STW killed renamable $r6, 56, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r5, 60, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 64, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r7, 68, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r6, 72, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r5, 76, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 80, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r7, 84, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r6, 88, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r5, 92, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 96, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r7, 100, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r6, 104, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r5, 108, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 112, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r7, 116, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r5, 120, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r5, 124, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r3, 128, $r1 :: (store 4)
+; 32BIT-DAG: renamable $r[[REGF1:[0-9]+]] = LWZtoc @f14, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r3 = LWZ 0, killed renamable $r[[REGF1]] :: (load 4 from @f14)
+; 32BIT-DAG: STFD killed renamable $f0, 132, $r1 :: (store 8)
+; 32BIT-DAG: renamable $r[[REGD:[0-9]+]] = LWZtoc @d15, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $f0 = LFD 0, killed renamable $r[[REGD]] :: (dereferenceable load 8 from @d15)
+; 32BIT-DAG: STW killed renamable $r4, 140, $r1 :: (store 4)
+; 32BIT-DAG: renamable $r[[REGF2:[0-9]+]] = LWZtoc @f16, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r4 = LWZ 0, killed renamable $r[[REGF2]] :: (load 4 from @f16)
+; 32BIT-DAG: renamable $r6 = LWZtoc %const.0, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r7 = LWZtoc %const.1, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r8 = LWZtoc %const.2, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r5 = LWZtoc %const.3, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r6 = LWZtoc %const.4, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r7 = LWZtoc %const.5, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r8 = LWZtoc %const.6, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r5 = LWZtoc %const.7, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r6 = LWZtoc %const.8, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r7 = LWZtoc %const.9, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r8 = LWZtoc %const.10, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r5 = LWZtoc %const.11, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $f1 = LFD 0, killed renamable $r5 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f2 = LFD 0, killed renamable $r6 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f3 = LFD 0, killed renamable $r7 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f4 = LFD 0, killed renamable $r8 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f5 = LFS 0, killed renamable $r5 :: (load 4 from constant-pool)
+; 32BIT-DAG: renamable $f6 = LFD 0, killed renamable $r5 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f7 = LFD 0, killed renamable $r6 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f8 = LFD 0, killed renamable $r7 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f9 = LFD 0, killed renamable $r8 :: (load 8 from constant-pool)
+; 32BIT-DAG: $f10 = COPY renamable $f1
+; 32BIT-DAG: renamable $f11 = LFD 0, killed renamable $r6 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f12 = LFD 0, killed renamable $r7 :: (load 8 from constant-pool)
+; 32BIT-DAG: renamable $f13 = LFD 0, killed renamable $r8 :: (load 8 from constant-pool)
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_stack>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $f1
+; 32BIT-NEXT: ADJCALLSTACKUP 144, 0, implicit-def dead $r1, implicit $r1
+
+; CHECKASM-LABEL: .caller_fpr_stack:
+
+; ASM32PWR4: mflr 0
+; ASM32PWR4-DAG: stw 0, 8(1)
+; ASM32PWR4-DAG: stwu 1, -144(1)
+; ASM32PWR4-DAG: lwz [[REGD:[0-9]+]], LC18(2)
+; ASM32PWR4-DAG: lwz [[REGF1:[0-9]+]], LC19(2)
+; ASM32PWR4-DAG: lwz [[REGF2:[0-9]+]], LC20(2)
+; ASM32PWR4-DAG: lfd [[REGDNEW:[0-9]+]], 0([[REGD]])
+; ASM32PWR4-DAG: lwz [[REGF1NEW:[0-9]+]], 0([[REGF1]])
+; ASM32PWR4-DAG: lwz [[REGF2NEW:[0-9]+]], 0([[REGF2]])
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 56(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 60(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 64(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 68(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 72(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 76(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 80(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 84(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 88(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 92(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 96(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 100(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 108(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 104(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 112(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 116(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 120(1)
+; ASM32PWR4-DAG: stw [[SCRATCHREG:[0-9]+]], 124(1)
+; ASM32PWR4-DAG: stw [[REGF1NEW]], 128(1)
+; ASM32PWR4-DAG: stfd [[REGDNEW]], 132(1)
+; ASM32PWR4-DAG: stw [[REGF2NEW]], 140(1)
+; ASM32PWR4-NEXT: bl .test_fpr_stack
+
+; ASM64PWR4: mflr 0
+; ASM64PWR4-DAG: std 0, 16(1)
+; ASM64PWR4-DAG: stdu 1, -176(1)
+; ASM64PWR4-DAG: ld [[REGF1:[0-9]+]], LC17(2)
+; ASM64PWR4-DAG: ld [[REGD:[0-9]+]], LC18(2)
+; ASM64PWR4-DAG: ld [[REGF2:[0-9]+]], LC19(2)
+; ASM64PWR4-DAG: lwz [[REGF1NEW:[0-9]+]], 0([[REGF1]])
+; ASM64PWR4-DAG: ld [[REGDNEW:[0-9]+]], 0([[REGD]])
+; ASM64PWR4-DAG: lwz [[REGF2NEW:[0-9]+]], 0([[REGF2]])
+; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 112(1)
+; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 120(1)
+; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 128(1)
+; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 136(1)
+; ASM64PWR4-DAG: std [[SCRATCHREG:[0-9]+]], 144(1)
+; ASM64PWR4-DAG: stw [[REGF1NEW]], 152(1)
+; ASM64PWR4-DAG: std [[REGDNEW]], 160(1)
+; ASM64PWR4-DAG: stw [[REGF2NEW]], 168(1)
+; ASM64PWR4-NEXT: bl .test_fpr_stack
+
+define i32 @mix_callee(double %d1, double %d2, double %d3, double %d4, i8 zeroext %c1, i16 signext %s1, i64 %ll1, i32 %i1, i32 %i2, i32 %i3) {
+ entry:
+ %add = fadd double %d1, %d2
+ %add1 = fadd double %add, %d3
+ %add2 = fadd double %add1, %d4
+ %conv = zext i8 %c1 to i32
+ %conv3 = sext i16 %s1 to i32
+ %add4 = add nsw i32 %conv, %conv3
+ %conv5 = sext i32 %add4 to i64
+ %add6 = add nsw i64 %conv5, %ll1
+ %conv7 = sext i32 %i1 to i64
+ %add8 = add nsw i64 %add6, %conv7
+ %conv9 = sext i32 %i2 to i64
+ %add10 = add nsw i64 %add8, %conv9
+ %conv11 = sext i32 %i3 to i64
+ %add12 = add nsw i64 %add10, %conv11
+ %conv13 = trunc i64 %add12 to i32
+ %conv14 = sitofp i32 %conv13 to double
+ %add15 = fadd double %conv14, %add2
+ %conv16 = fptosi double %add15 to i32
+ ret i32 %conv16
+ }
+
+; 32BIT-DAG: liveins:
+; 32BIT-DAG: - { reg: '$f1', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f2', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f3', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f4', virtual-reg: '' }
+
+; 32BIT-DAG: fixedStack:
+; 32BIT-DAG: - { id: 6, type: default, offset: 56, size: 4
+; 32BIT-DAG: - { id: 5, type: default, offset: 60, size: 4
+; 32BIT-DAG: - { id: 4, type: default, offset: 64, size: 4
+; 32BIT-DAG: - { id: 3, type: default, offset: 68, size: 4
+; 32BIT-DAG: - { id: 2, type: default, offset: 72, size: 4
+; 32BIT-DAG: - { id: 1, type: default, offset: 76, size: 4
+; 32BIT-DAG: - { id: 0, type: default, offset: 80, size: 4
+
+; 32BIT-DAG: body: |
+; 32BIT-DAG: bb.0.entry:
+; 32BIT-NEXT: liveins: $f1, $f2, $f3, $f4
+
+; 64BIT: liveins:
+; 64BIT: - { reg: '$f1', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f2', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f3', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f4', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x10', virtual-reg: '' }
+
+; 64BIT: fixedStack:
+; 64BIT-DAG: - { id: 1, type: default, offset: 112, size: 8
+; 64BIT-DAG: - { id: 0, type: default, offset: 120, size: 8
+
+; 64BIT: body: |
+; 64BIT-NEXT: bb.0.entry:
+; 64BIT-NEXT: liveins: $f1, $f2, $f3, $f4, $x7, $x8, $x9, $x10
+
+; CHECKASM-LABEL: .mix_callee
+
+; ASM32PWR4: stwu 1, -48(1)
+; ASM32PWR4-DAG: lwz [[REG1:[0-9]+]], 104(1)
+; ASM32PWR4-DAG: lwz [[REG2:[0-9]+]], 108(1)
+; ASM32PWR4-DAG: lwz [[REG3:[0-9]+]], 116(1)
+; ASM32PWR4-DAG: lwz [[REG4:[0-9]+]], 120(1)
+; ASM32PWR4-DAG: lwz [[REG5:[0-9]+]], 124(1)
+; ASM32PWR4-DAG: lwz [[REG6:[0-9]+]], 128(1)
+; ASM32PWR4-DAG: lwz 5, LC33(2)
+; ASM32PWR4-DAG: lis 8, 17200
+; ASM32PWR4-DAG: lfs 0, 0(5)
+; ASM32PWR4-DAG: fadd 1, 1, 2
+; ASM32PWR4-DAG: fadd 1, 1, 3
+; ASM32PWR4-DAG: add 4, 5, 4
+; ASM32PWR4-DAG: fadd 1, 1, 4
+; ASM32PWR4-DAG: add 3, 4, 3
+; ASM32PWR4-DAG: add 3, 3, 6
+; ASM32PWR4-DAG: stw 8, 32(1)
+; ASM32PWR4-DAG: add 3, 3, 7
+; ASM32PWR4-DAG: add 3, 3, 8
+; ASM32PWR4-DAG: xoris 3, 3, 32768
+; ASM32PWR4-DAG: stw 3, 36(1)
+; ASM32PWR4-DAG: addi 3, 1, 44
+; ASM32PWR4-DAG: lfd 2, 32(1)
+; ASM32PWR4-DAG: fsub 0, 2, 0
+; ASM32PWR4-DAG: fadd 0, 0, 1
+; ASM32PWR4-DAG: fctiwz 0, 0
+; ASM32PWR4-DAG: stfiwx 0, 0, 3
+; ASM32PWR4-DAG: lwz 3, 44(1)
+; ASM32PWR4-NEXT: addi 1, 1, 48
+; ASM32PWR4-NEXT: blr
+
+; ASM64PWR-DAG: ld [[REG1:[0-9]+]], 112(1)
+; ASM64PWR-DAG: ld [[REG2:[0-9]+]], 120(1)
+; ASM64PWR-DAG: add 4, 7, 8
+; ASM64PWR-DAG: fadd 0, 1, 2
+; ASM64PWR-DAG: add 4, 4, 9
+; ASM64PWR-DAG: fadd 0, 0, [[REG1]]
+; ASM64PWR-DAG: add 4, 4, 10
+; ASM64PWR-DAG: add 3, 4, 3
+; ASM64PWR-DAG: add 3, 3, [[REG2]]
+; ASM64PWR-DAG: fadd 0, 0, 4
+; ASM64PWR-DAG: extsw 3, 3
+; ASM64PWR-DAG: std 3, -16(1)
+; ASM64PWR-DAG: addi 3, 1, -4
+; ASM64PWR-DAG: lfd 1, -16(1)
+; ASM64PWR-DAG: fcfid 1, 1
+; ASM64PWR-DAG: fadd 0, 1, 0
+; ASM64PWR-DAG: fctiwz 0, 0
+; ASM64PWR-DAG: stfiwx 0, 0, 3
+; ASM64PWR-DAG: lwz 3, -4(1)
+; ASM64PWR-DAG: blr
+
+define void @caller_mix() {
+ entry:
+%call = call i32 @mix_callee(double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, i8 zeroext 1, i16 signext 2, i64 30000000, i32 40, i32 50, i32 60)
+ ret void
+ }
+
+; CHECK-LABEL: name: caller_mix
+; 64BIT: ADJCALLSTACKDOWN 128, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-DAG: STW8 killed renamable $x[[REG1ADDR: [0-9]+]], 112, $x1 :: (store 4)
+; 64BIT-DAG: STW8 killed renamable $x[[REG2ADDR: [0-9]+]], 120, $x1 :: (store 4)
+; 64BIT-DAG: renamable $x3 = LDtocCPT %const.0, $x2 :: (load 8 from got)
+; 64BIT-DAG: renamable $x4 = LDtocCPT %const.1, $x2 :: (load 8 from got)
+; 64BIT-DAG: renamable $x3 = LDtocCPT %const.2, $x2 :: (load 8 from got)
+; 64BIT-DAG: renamable $x4 = LDtocCPT %const.3, $x2 :: (load 8 from got)
+; 64BIT-DAG: renamable $f1 = LFD 0, killed renamable $x[[REG1ADDR]] :: (load 8 from constant-pool)
+; 64BIT-DAG: renamable $f2 = LFD 0, killed renamable $x[[REG2ADDR]] :: (load 8 from constant-pool)
+; 64BIT-DAG: renamable $f3 = LFD 0, killed renamable $x3 :: (load 8 from constant-pool)
+; 64BIT-DAG: renamable $f4 = LFD 0, killed renamable $x4 :: (load 8 from constant-pool)
+; 64BIT-DAG: renamable $x[[SCRATCHREG: [0-9]+]] = LI8 50
+; 64BIT-DAG: renamable $x[[SCRATCHREG: [0-9]+]] = LI8 60
+; 64BIT-DAG: renamable $x[[SCRATCHREG: [0-9]+]] = LIS8 457
+; 64BIT-DAG: $x7 = LI8 1
+; 64BIT-DAG: $x8 = LI8 2
+; 64BIT-DAG: $x10 = LI8 40
+; 64BIT-DAG: renamable $x[[SCRATCHREG: [0-9]+]] = ORI8 killed renamable $x[[SCRATCHREG: [0-9]+]], 50048
+; 64BIT-NEXT: BL8_NOP <mcsymbol .mix_callee>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit killed $x7, implicit killed $x8, implicit $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
+; 64BIT-NEXT: ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm
+
+; CHEKASM-LABEL: .caller_mix
+; ASM32PWR4: mflr 0
+; ASM32PWR4-DAG: stw [[REG1:[0-9]+]], 56(1)
+; ASM32PWR4-DAG: stw [[REG2:[0-9]+]], 60(1)
+; ASM32PWR4-DAG: stw [[REG3:[0-9]+]], 64(1)
+; ASM32PWR4-DAG: stw [[REG4:[0-9]+]], 68(1)
+; ASM32PWR4-DAG: stw [[REG5:[0-9]+]], 72(1)
+; ASM32PWR4-DAG: stw [[REG6:[0-9]+]], 76(1)
+; ASM32PWR4-DAG: stw [[REG7:[0-9]+]], 80(1)
+; ASM32PWR4-DAG: stw 0, 8(1)
+; ASM32PWR4-DAG: stwu 1, -96(1)
+; ASM32PWR4-DAG: li 3, 60
+; ASM32PWR4-DAG: li 3, 50
+; ASM32PWR4-DAG: li 3, 40
+; ASM32PWR4-DAG: li 3, 0
+; ASM32PWR4-DAG: li 3, 2
+; ASM32PWR4-DAG: lwz 3, LC34(2)
+; ASM32PWR4-DAG: lfd 1, 0(3)
+; ASM32PWR4-DAG: lwz 3, LC35(2)
+; ASM32PWR4-DAG: lfd 2, 0(3)
+; ASM32PWR4-DAG: lwz 3, LC36(2)
+; ASM32PWR4-DAG: lfd 3, 0(3)
+; ASM32PWR4-DAG: lwz 3, LC37(2)
+; ASM32PWR4-DAG: lfd 4, 0(3)
+; ASM32PWR4-DAG: li 3, 1
+; ASM32PWR4-DAG: lis 3, 457
+; ASM32PWR4-DAG: ori 3, 3, 50048
+; ASM32PWR4-DAG: bl .mix_callee
+; ASM32PWR4-DAG: nop
+; ASM32PWR4-DAG: addi 1, 1, 96
+; ASM32PWR4-DAG: lwz 0, 8(1)
+; ASM32PWR4-DAG: mtlr 0
+; ASM32PWR4-DAG: blr
+
+; ASM64PWR4: mflr 0
+; ASM64PWR4-DAG: std 0, 16(1)
+; ASM64PWR4-DAG: stdu 1, -128(1)
+; ASM64PWR4-DAG: stw [[REG1:[0-9]+]], 112(1)
+; ASM64PWR4-DAG: stw [[REG2:[0-9]+]], 120(1)
+; ASM64PWR4-DAG: ld 3, LC32(2)
+; ASM64PWR4-DAG: ld 4, LC33(2)
+; ASM64PWR4-DAG: lis 5, 457
+; ASM64PWR4-DAG: li 7, 1
+; ASM64PWR4-DAG: ori 9, 5, 50048
+; ASM64PWR4-DAG: li 8, 2
+; ASM64PWR4-DAG: lfd 1, 0(3)
+; ASM64PWR4-DAG: ld 3, LC34(2)
+; ASM64PWR4-DAG: li 10, 40
+; ASM64PWR4-DAG: lfd 2, 0(4)
+; ASM64PWR4-DAG: ld 4, LC35(2)
+; ASM64PWR4-DAG: lfd 3, 0(3)
+; ASM64PWR4-DAG: li 3, 60
+; ASM64PWR4-DAG: lfd 4, 0(4)
+; ASM64PWR4-DAG: li 4, 50
+; ASM64PWR4-DAG: bl .mix_callee
+; ASM64PWR4-DAG: nop
+; ASM64PWR4-DAG: addi 1, 1, 128
+; ASM64PWR4-DAG: ld 0, 16(1)
+; ASM64PWR4-DAG: mtlr 0
+; ASM64PWR4-DAG: blr
+
+
+ define i32 @mix_floats(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10, double %d11, double %d12, double %d13, double %d14) {
+ entry:
+ %add = add nsw i32 %i1, %i2
+ %add1 = add nsw i32 %add, %i3
+ %add2 = add nsw i32 %add1, %i4
+ %add3 = add nsw i32 %add2, %i5
+ %add4 = add nsw i32 %add3, %i6
+ %add5 = add nsw i32 %add4, %i7
+ %add6 = add nsw i32 %add5, %i8
+ %conv = sitofp i32 %add6 to double
+ %add7 = fadd double %conv, %d1
+ %add8 = fadd double %add7, %d2
+ %add9 = fadd double %add8, %d3
+ %add10 = fadd double %add9, %d4
+ %add11 = fadd double %add10, %d5
+ %add12 = fadd double %add11, %d6
+ %add13 = fadd double %add12, %d7
+ %add14 = fadd double %add13, %d8
+ %add15 = fadd double %add14, %d9
+ %add16 = fadd double %add15, %d10
+ %add17 = fadd double %add16, %d11
+ %add18 = fadd double %add17, %d12
+ %add19 = fadd double %add18, %d13
+ %add20 = fadd double %add19, %d14
+ %conv21 = fptosi double %add20 to i32
+ ret i32 %conv21
+ }
+; CHECK-LABEL: mix_floats
+
+; 32BIT-DAG: liveins:
+; 32BIT-DAG: - { reg: '$r3', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r4', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r5', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r6', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r7', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r8', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r9', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$r10', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f1', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f2', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f3', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f4', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f5', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f6', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f7', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f8', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f9', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f10', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f11', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f12', virtual-reg: '' }
+; 32BIT-DAG: - { reg: '$f13', virtual-reg: '' }
+
+; 32BIT-DAG: fixedStack:
+; 32BIT-DAG: - { id: 0, type: default, offset: 160, size: 8
+
+; 32BIT-DAG: body: |
+; 32BIT-DAG: bb.0.entry:
+; 32BIT-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+
+; 64BIT-DAG: liveins:
+; 64BIT-DAG: - { reg: '$x3', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x5', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x6', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x7', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x8', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x9', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$x10', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f1', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f2', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f3', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f4', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f5', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f6', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f7', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f8', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f9', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f10', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f11', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f12', virtual-reg: '' }
+; 64BIT-DAG: - { reg: '$f13', virtual-reg: '' }
+
+; 64BIT-DAG: fixedStack:
+; 64BIT-DAG: - { id: 0, type: default, offset: 216, size: 8
+
+; 64BIT-DAG: body: |
+; 64BIT-DAG: bb.0.entry:
+; 64BIT-DAG: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+
+; CHECKASM-LABEL: .mix_floats:
+; ASM32PWR4: stwu 1, -48(1)
+; ASM32PWR4-DAG: lfd [[REG1:[0-9]+]], 208(1)
+; ASM32PWR4-DAG: add 3, 3, 4
+; ASM32PWR4-DAG: lwz 4, LC38(2)
+; ASM32PWR4-DAG: lis 11, 17200
+; ASM32PWR4-DAG: stfd 31, 40(1)
+; ASM32PWR4-DAG: add 3, 3, 5
+; ASM32PWR4-DAG: add 3, 3, 6
+; ASM32PWR4-DAG: add 3, 3, 7
+; ASM32PWR4-DAG: stw 11, 24(1)
+; ASM32PWR4-DAG: add 3, 3, 8
+; ASM32PWR4-DAG: add 3, 3, 9
+; ASM32PWR4-DAG: add 3, 3, 10
+; ASM32PWR4-DAG: lfs 0, 0(4)
+; ASM32PWR4-DAG: xoris 3, 3, 32768
+; ASM32PWR4-DAG: stw 3, 28(1)
+; ASM32PWR4-DAG: addi 3, 1, 36
+; ASM32PWR4-DAG: lfd 31, 24(1)
+; ASM32PWR4-DAG: fsub 0, 31, 0
+; ASM32PWR4-DAG: fadd 0, 0, 1
+; ASM32PWR4-DAG: fadd 0, 0, 2
+; ASM32PWR4-DAG: fadd 0, 0, 3
+; ASM32PWR4-DAG: fadd 0, 0, 4
+; ASM32PWR4-DAG: fadd 0, 0, 5
+; ASM32PWR4-DAG: fadd 0, 0, 6
+; ASM32PWR4-DAG: fadd 0, 0, 7
+; ASM32PWR4-DAG: fadd 0, 0, 8
+; ASM32PWR4-DAG: fadd 0, 0, 9
+; ASM32PWR4-DAG: fadd 0, 0, 10
+; ASM32PWR4-DAG: fadd 0, 0, 11
+; ASM32PWR4-DAG: fadd 0, 0, 12
+; ASM32PWR4-DAG: fadd 0, 0, 13
+; ASM32PWR4-DAG: fadd 0, 0, [[REG1]]
+; ASM32PWR4-DAG: fctiwz 0, 0
+; ASM32PWR4-DAG: stfiwx 0, 0, 3
+; ASM32PWR4-DAG: lwz 3, 36(1)
+; ASM32PWR4-DAG: lfd 31, 40(1)
+; ASM32PWR4-DAG: addi 1, 1, 48
+; ASM32PWR4-NEXT: blr
+
+; ASM64PWR4: add 3, 3, 4
+; ASM64PWR4-DAG: add 3, 3, 5
+; ASM64PWR4-DAG: add 3, 3, 6
+; ASM64PWR4-DAG: add 3, 3, 7
+; ASM64PWR4-DAG: add 3, 3, 8
+; ASM64PWR4-DAG: add 3, 3, 9
+; ASM64PWR4-DAG: add 3, 3, 10
+; ASM64PWR4-DAG: extsw 3, 3
+; ASM64PWR4-DAG: std 3, -16(1)
+; ASM64PWR4-DAG: addi 3, 1, -4
+; ASM64PWR4-DAG: lfd 0, -16(1)
+; ASM64PWR4-DAG: fcfid 0, 0
+; ASM64PWR4-DAG: fadd 0, 0, 1
+; ASM64PWR4-DAG: lfd [[REG1:[0-9]+]], 216(1)
+; ASM64PWR4-DAG: fadd 0, 0, 2
+; ASM64PWR4-DAG: fadd 0, 0, 3
+; ASM64PWR4-DAG: fadd 0, 0, 4
+; ASM64PWR4-DAG: fadd 0, 0, 5
+; ASM64PWR4-DAG: fadd 0, 0, 6
+; ASM64PWR4-DAG: fadd 0, 0, 7
+; ASM64PWR4-DAG: fadd 0, 0, 8
+; ASM64PWR4-DAG: fadd 0, 0, 9
+; ASM64PWR4-DAG: fadd 0, 0, 10
+; ASM64PWR4-DAG: fadd 0, 0, 11
+; ASM64PWR4-DAG: fadd 0, 0, 12
+; ASM64PWR4-DAG: fadd 0, 0, 13
+; ASM64PWR4-DAG: fadd 0, 0, [[REG1]]
+; ASM64PWR4-DAG: fctiwz 0, 0
+; ASM64PWR4-DAG: stfiwx 0, 0, 3
+; ASM64PWR4-DAG: lwz 3, -4(1)
+; ASM64PWR4-DAG: blr
+
+ define void @mix_floats_caller() {
+ entry:
+ %call = call i32 @mix_floats(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 0x3FE6666666666666, double 8.000000e-01, double 9.000000e-01, double 1.000000e+00, double 1.100000e+00, double 1.200000e+00, double 1.300000e+00, double 1.400000e+00)
+ ret void
+ }
+
+; CHECK-LABEL: mix_floats_caller
+
+; 32BIT-DAG: ADJCALLSTACKDOWN 168, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-DAG: STW killed renamable $r7, 56, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r6, 60, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r8, 64, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r6, 68, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r10, 72, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r9, 76, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r11, 80, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r6, 84, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r4, 88, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r3, 92, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r4, 96, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r9, 100, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r5, 104, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r3, 108, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r7, 112, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r6, 116, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r10, 120, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r5, 128, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW renamable $r8, 124, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r3, 132, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r11, 136, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r6, 140, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r4, 144, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r9, 148, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r5, 152, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r8, 156, $r1 :: (store 4)
+; 32BIT-DAG: STW killed renamable $r12, 160, $r1 :: (store 4, align 8)
+; 32BIT-DAG: STW killed renamable $r3, 164, $r1 :: (store 4)
+; 32BIT-DAG: renamable $r10 = LWZtoc %const.0, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r6 = LWZtoc %const.1, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r11 = LWZtoc %const.2, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r9 = LWZtoc %const.3, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r4 = LWZtoc %const.4, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r8 = LWZtoc %const.5, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r5 = LWZtoc %const.6, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r3 = LWZtoc %const.7, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r10 = LWZtoc %const.8, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r6 = LWZtoc %const.9, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r11 = LWZtoc %const.10, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r9 = LWZtoc %const.11, $r2 :: (load 4 from got)
+; 32BIT-DAG: renamable $r4 = LWZtoc %const.12, $r2 :: (load 4 from got)
+; 32BIT-DAG: $r3 = LI 1
+; 32BIT-DAG: $r4 = LI 2
+; 32BIT-DAG: $r5 = LI 3
+; 32BIT-DAG: $r6 = LI 4
+; 32BIT-DAG: $r7 = LI 5
+; 32BIT-DAG: $r8 = LI 6
+; 32BIT-DAG: $r9 = LI 7
+; 32BIT-DAG: $r10 = LI 8
+; 32BIT-NEXT: BL_NOP <mcsymbol .mix_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def dead $r3
+; 32BIT-NEXT: ADJCALLSTACKUP 168, 0, implicit-def dead $r1, implicit $r1
+
+; CHEKASM-LABEL: .mix_floats_caller:
+
+; ASM32PWR4: mflr 0
+; ASM32PWR4-DAG: stw 0, 8(1)
+; ASM32PWR4-DAG: stwu 1, -176(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 56(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 60(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 64(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 68(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 72(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 76(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 80(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 84(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 88(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 92(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 96(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 100(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 104(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 108(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 112(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 116(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 120(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 124(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 128(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 132(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 136(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 140(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 144(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 148(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 152(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 156(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 160(1)
+; ASM32PWR4-DAG: stw [[REG:[0-9]+]], 164(1)
+; ASM32PWR4-NEXT: bl .mix_floats
+
+; ASM64PWR4: mflr 0
+; ASM64PWR4-DAG: std 0, 16(1)
+; ASM64PWR4-DAG: stdu 1, -240(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 112(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 120(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 128(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 136(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 144(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 152(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 160(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 168(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 176(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 184(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 192(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 200(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 208(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 216(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 224(1)
+; ASM64PWR4-DAG: std [[REG:[0-9]+]], 232(1)
+; ASM64PWR4-NEXT: bl .mix_floats
+; ASM64PWR4-DAG: nop
+; ASM64PWR4-DAG: ld [[REGF1:[0-9]+]], 232(1)
+; ASM64PWR4-DAG: ld [[REGF2:[0-9]+]], 224(1)
+; ASM64PWR4-DAG: addi 1, 1, 240
+; ASM64PWR4-DAG: ld 0, 16(1)
+; ASM64PWR4-DAG: mtlr 0
+; ASM64PWR4-NEXT: blr