Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -571,27 +571,6 @@ return AltMappings; } - case TargetOpcode::G_ICMP: { - // TODO: Should report 32-bit for scalar output type. - unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI); - const InstructionMapping &SSMapping = getInstructionMapping(1, 1, - getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), - nullptr, // Predicate operand. - AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), - AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}), - 4); // Num Operands - AltMappings.push_back(&SSMapping); - - const InstructionMapping &VVMapping = getInstructionMapping(4, 1, - getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), - nullptr, // Predicate operand. - AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), - AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}), - 4); // Num Operands - AltMappings.push_back(&VVMapping); - - return AltMappings; - } case TargetOpcode::G_SELECT: { unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); const InstructionMapping &SSMapping = getInstructionMapping(1, 1, @@ -1607,7 +1586,13 @@ MachineBasicBlock *MBB = MI.getParent(); B.setInsertPt(*MBB, std::next(MI.getIterator())); - B.buildTrunc(DstReg, NewDstReg); + + // If we had a constrained VCC result register, a copy was inserted to VCC + // from SGPR. + SmallVector DefRegs(OpdMapper.getVRegs(0)); + if (DefRegs.empty()) + DefRegs.push_back(DstReg); + B.buildTrunc(DefRegs[0], NewDstReg); return; } case AMDGPU::G_SELECT: { @@ -3040,25 +3025,31 @@ case AMDGPU::G_ICMP: { auto Pred = static_cast(MI.getOperand(1).getPredicate()); unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); + + // See if the result register has already been constrained to vcc, which may + // happen due to control flow intrinsic lowering. + unsigned DstBank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI, + AMDGPU::SGPRRegBankID); unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI); unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI); - bool CanUseSCC = Op2Bank == AMDGPU::SGPRRegBankID && + bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID && + Op2Bank == AMDGPU::SGPRRegBankID && Op3Bank == AMDGPU::SGPRRegBankID && (Size == 32 || (Size == 64 && (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) && Subtarget.hasScalarCompareEq64())); - unsigned Op0Bank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; + DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; + unsigned SrcBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; // TODO: Use 32-bit for scalar output size. // SCC results will need to be copied to a 32-bit SGPR virtual register. const unsigned ResultSize = 1; - OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, ResultSize); - OpdsMapping[1] = nullptr; // Predicate Operand. - OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size); - OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size); + OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize); + OpdsMapping[2] = AMDGPU::getValueMapping(SrcBank, Size); + OpdsMapping[3] = AMDGPU::getValueMapping(SrcBank, Size); break; } case AMDGPU::G_EXTRACT_VECTOR_ELT: { Index: llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll +++ llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll @@ -56,3 +56,145 @@ %val = load volatile i32, i32 addrspace(1)* undef br label %endif } + +; Make sure and 1 is inserted on llvm.amdgcn.if +define i32 @divergent_if_nonboolean_condition0(i32 %value) { +; CHECK-LABEL: divergent_if_nonboolean_condition0: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; CHECK-NEXT: ; implicit-def: $vgpr0 +; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc +; CHECK-NEXT: s_cbranch_execz BB2_2 +; CHECK-NEXT: ; %bb.1: ; %if.true +; CHECK-NEXT: global_load_dword v0, v[0:1], off +; CHECK-NEXT: BB2_2: ; %endif +; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %c = trunc i32 %value to i1 + br i1 %c, label %if.true, label %endif + +if.true: + %val = load volatile i32, i32 addrspace(1)* undef + br label %endif + +endif: + %v = phi i32 [ %val, %if.true ], [ undef, %entry ] + ret i32 %v +} + +; Make sure and 1 is inserted on llvm.amdgcn.if +define i32 @divergent_if_nonboolean_condition1(i32 addrspace(1)* %ptr) { +; CHECK-LABEL: divergent_if_nonboolean_condition1: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: global_load_dword v0, v[0:1], off +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 +; CHECK-NEXT: ; implicit-def: $vgpr0 +; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc +; CHECK-NEXT: s_cbranch_execz BB3_2 +; CHECK-NEXT: ; %bb.1: ; %if.true +; CHECK-NEXT: global_load_dword v0, v[0:1], off +; CHECK-NEXT: BB3_2: ; %endif +; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %value = load i32, i32 addrspace(1)* %ptr + %c = trunc i32 %value to i1 + br i1 %c, label %if.true, label %endif + +if.true: + %val = load volatile i32, i32 addrspace(1)* undef + br label %endif + +endif: + %v = phi i32 [ %val, %if.true ], [ undef, %entry ] + ret i32 %v +} + +@external_constant = external addrspace(4) constant i32, align 4 +@const.ptr = external addrspace(4) constant float*, align 4 + +; Make sure this case compiles. G_ICMP was mis-mapped due to having +; the result register class constrained by llvm.amdgcn.if lowering. +define void @constrained_if_register_class() { +; CHECK-LABEL: constrained_if_register_class: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: s_getpc_b64 s[4:5] +; CHECK-NEXT: s_add_u32 s4, s4, external_constant@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s5, s5, external_constant@gotpcrel32@hi+4 +; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_load_dword s6, s[4:5], 0x0 +; CHECK-NEXT: s_getpc_b64 s[4:5] +; CHECK-NEXT: s_add_u32 s4, s4, const.ptr@gotpcrel32@lo+4 +; CHECK-NEXT: s_addc_u32 s5, s5, const.ptr@gotpcrel32@hi+4 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_cmp_lg_u32 s6, 0 +; CHECK-NEXT: s_cselect_b32 s6, 1, 0 +; CHECK-NEXT: s_and_b32 s6, s6, 1 +; CHECK-NEXT: s_cmp_lg_u32 s6, 0 +; CHECK-NEXT: s_cbranch_scc1 BB4_6 +; CHECK-NEXT: ; %bb.1: ; %bb2 +; CHECK-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0 +; CHECK-NEXT: s_mov_b32 s4, -1 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: v_mov_b32_e32 v0, s6 +; CHECK-NEXT: v_mov_b32_e32 v1, s7 +; CHECK-NEXT: flat_load_dword v0, v[0:1] +; CHECK-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, 1 +; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0 +; CHECK-NEXT: s_xor_b64 s[8:9], vcc, s[6:7] +; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9] +; CHECK-NEXT: ; %bb.2: ; %bb7 +; CHECK-NEXT: s_mov_b32 s4, 0 +; CHECK-NEXT: ; %bb.3: ; %bb8 +; CHECK-NEXT: s_or_b64 exec, exec, s[6:7] +; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], s4, 0 +; CHECK-NEXT: s_and_saveexec_b64 s[4:5], s[6:7] +; CHECK-NEXT: s_cbranch_execz BB4_5 +; CHECK-NEXT: ; %bb.4: ; %bb11 +; CHECK-NEXT: v_mov_b32_e32 v0, 4.0 +; CHECK-NEXT: buffer_store_dword v0, v0, s[0:3], s33 offen +; CHECK-NEXT: BB4_5: ; %Flow +; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] +; CHECK-NEXT: BB4_6: ; %bb12 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +bb: + %tmp = load i32, i32 addrspace(4)* @external_constant + %ptr = load float*, float* addrspace(4)* @const.ptr + %tmp1 = icmp ne i32 %tmp, 0 + br i1 %tmp1, label %bb12, label %bb2 + +bb2: + %tmp4 = load float, float* %ptr, align 4 + %tmp5 = fcmp olt float %tmp4, 1.0 + %tmp6 = or i1 %tmp5, false + br i1 %tmp6, label %bb8, label %bb7 + +bb7: + br label %bb8 + +bb8: + %tmp9 = phi i32 [ 0, %bb7 ], [ -1, %bb2 ] + %tmp10 = icmp eq i32 %tmp9, 0 + br i1 %tmp10, label %bb11, label %bb12 + +bb11: + store float 4.0, float addrspace(5)* undef, align 4 + br label %bb12 + +bb12: + ret void +} Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir @@ -44,11 +44,12 @@ ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] - ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) - ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[ICMP]](s1) + ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]] + ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[ICMP]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s32) = COPY $sgpr2 @@ -71,10 +72,11 @@ ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] - ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) - ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY4]](s32), [[COPY5]](s32), [[ICMP]](s1) + ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]] + ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) + ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY5]](s32), [[COPY6]](s32), [[ICMP]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $sgpr0 %2:_(s32) = COPY $sgpr1 @@ -97,7 +99,8 @@ ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]] + ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]] ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[ICMP]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir @@ -86,8 +86,10 @@ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 @@ -157,9 +159,10 @@ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY3]], [[ICMP1]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 %2:_(s32) = G_CONSTANT i32 0 @@ -179,8 +182,10 @@ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] ; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]] %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir @@ -36,11 +36,13 @@ ; GFX7-LABEL: name: icmp_eq_s32_sv ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY1]] ; GFX8-LABEL: name: icmp_eq_s32_sv ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY1]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 %2:_(s1) = G_ICMP intpred(eq), %0, %1 @@ -56,11 +58,13 @@ ; GFX7-LABEL: name: icmp_eq_s32_vs ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]] ; GFX8-LABEL: name: icmp_eq_s32_vs ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 %2:_(s1) = G_ICMP intpred(eq), %1, %0 @@ -96,7 +100,9 @@ ; GFX7-LABEL: name: icmp_eq_s64_ss ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY3]] ; GFX8-LABEL: name: icmp_eq_s64_ss ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 @@ -117,11 +123,13 @@ ; GFX7-LABEL: name: icmp_eq_s64_sv ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY1]] ; GFX8-LABEL: name: icmp_eq_s64_sv ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY1]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $vgpr0_vgpr1 %2:_(s1) = G_ICMP intpred(eq), %0, %1 @@ -137,11 +145,13 @@ ; GFX7-LABEL: name: icmp_eq_s64_vs ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY2]] ; GFX8-LABEL: name: icmp_eq_s64_vs ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY2]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $vgpr0_vgpr1 %2:_(s1) = G_ICMP intpred(eq), %1, %0 @@ -177,7 +187,9 @@ ; GFX7-LABEL: name: icmp_ne_s64_ss ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s64), [[COPY3]] ; GFX8-LABEL: name: icmp_ne_s64_ss ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 @@ -198,11 +210,13 @@ ; GFX7-LABEL: name: icmp_ne_s64_sv ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s64), [[COPY1]] ; GFX8-LABEL: name: icmp_ne_s64_sv ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s64), [[COPY1]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $vgpr0_vgpr1 %2:_(s1) = G_ICMP intpred(ne), %0, %1 @@ -218,11 +232,13 @@ ; GFX7-LABEL: name: icmp_ne_s64_vs ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]] ; GFX8-LABEL: name: icmp_ne_s64_vs ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $vgpr0_vgpr1 %2:_(s1) = G_ICMP intpred(ne), %1, %0 @@ -258,11 +274,15 @@ ; GFX7-LABEL: name: icmp_slt_s64_ss ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY3]] ; GFX8-LABEL: name: icmp_slt_s64_ss ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY3]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $sgpr2_sgpr3 %2:_(s1) = G_ICMP intpred(slt), %0, %1 @@ -278,11 +298,13 @@ ; GFX7-LABEL: name: icmp_slt_s64_sv ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY1]] ; GFX8-LABEL: name: icmp_slt_s64_sv ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY1]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $vgpr0_vgpr1 %2:_(s1) = G_ICMP intpred(slt), %0, %1 @@ -298,11 +320,13 @@ ; GFX7-LABEL: name: icmp_slt_s64_vs ; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY]] + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY2]] ; GFX8-LABEL: name: icmp_slt_s64_vs ; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1 ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1 - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY2]] %0:_(s64) = COPY $sgpr0_sgpr1 %1:_(s64) = COPY $vgpr0_vgpr1 %2:_(s1) = G_ICMP intpred(slt), %1, %0 @@ -327,3 +351,66 @@ %1:_(s64) = COPY $vgpr2_vgpr3 %2:_(s1) = G_ICMP intpred(slt), %0, %1 ... + +# Result is already constrained to be VCC bank, despite scalar inputs. +--- +name: map_icmp_already_vcc_bank_sgpr_inputs +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; GFX7-LABEL: name: map_icmp_already_vcc_bank_sgpr_inputs + ; GFX7: liveins: $sgpr0, $sgpr1 + ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX7: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] + ; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1) + ; GFX8-LABEL: name: map_icmp_already_vcc_bank_sgpr_inputs + ; GFX8: liveins: $sgpr0, $sgpr1 + ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX8: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] + ; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:vcc(s1) = G_ICMP intpred(eq), %0, %1 + S_ENDPGM 0, implicit %2 +... + +# Result is already con strained to be VCC bank, despite scalar inputs +# and also has a register class. +--- +name: map_icmp_already_vcc_regclass_sgpr_inputs +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0, $sgpr1 + + ; GFX7-LABEL: name: map_icmp_already_vcc_regclass_sgpr_inputs + ; GFX7: liveins: $sgpr0, $sgpr1 + ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX7: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GFX7: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] + ; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1) + ; GFX8-LABEL: name: map_icmp_already_vcc_regclass_sgpr_inputs + ; GFX8: liveins: $sgpr0, $sgpr1 + ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GFX8: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GFX8: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] + ; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1) + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:sreg_64_xexec(s1) = G_ICMP intpred(eq), %0, %1 + S_ENDPGM 0, implicit %2 +... Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir @@ -14,7 +14,9 @@ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32) - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16) + ; GFX8: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s16), [[COPY3]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $sgpr1 %2:_(s16) = G_TRUNC %0 @@ -34,7 +36,8 @@ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32) - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s16), [[TRUNC1]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 %2:_(s16) = G_TRUNC %0 @@ -54,7 +57,8 @@ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32) ; GFX8: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32) - ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]] + ; GFX8: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16) + ; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s16), [[TRUNC1]] %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 %2:_(s16) = G_TRUNC %0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir @@ -108,8 +108,10 @@ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY3]] ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[ICMP]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $vgpr0 @@ -134,9 +136,10 @@ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP1]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY3]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 @@ -207,9 +210,10 @@ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY1]] + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY3]], [[ICMP]] ; CHECK: S_NOP 0, implicit [[OR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir @@ -242,13 +242,14 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; FAST: G_BR %bb.2 ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch ; GREEDY: bb.0: @@ -268,13 +269,14 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -316,7 +318,8 @@ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -326,13 +329,13 @@ ; FAST: successors: %bb.2(0x80000000) ; FAST: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] ; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch ; GREEDY: bb.0: @@ -342,7 +345,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -352,13 +356,13 @@ ; GREEDY: successors: %bb.2(0x80000000) ; GREEDY: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] ; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -400,7 +404,8 @@ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -408,12 +413,13 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; FAST: G_BR %bb.2 ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]] + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch ; GREEDY: bb.0: @@ -423,7 +429,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -431,12 +438,13 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]] + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -828,7 +836,8 @@ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -837,12 +846,12 @@ ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) ; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]] + ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch ; GREEDY: bb.0: @@ -852,7 +861,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -861,12 +871,12 @@ ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) ; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]] + ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -917,13 +927,14 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; FAST: G_BR %bb.2 ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch ; GREEDY: bb.0: @@ -942,13 +953,14 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -990,7 +1002,8 @@ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -1007,9 +1020,9 @@ ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1 ; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch ; GREEDY: bb.0: @@ -1019,7 +1032,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -1036,9 +1050,9 @@ ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1 ; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) bb.0: successors: %bb.1, %bb.2 @@ -1089,7 +1103,8 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] ; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 ; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]] @@ -1097,9 +1112,9 @@ ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1 ; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) ; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch ; GREEDY: bb.0: @@ -1118,7 +1133,8 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] ; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 ; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]] @@ -1126,9 +1142,9 @@ ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1 ; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) bb.0: successors: %bb.1, %bb.2 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir @@ -307,15 +307,16 @@ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; FAST: G_BRCOND [[ICMP]](s1), %bb.1 ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) + ; FAST: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; FAST: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; FAST: $sgpr0 = COPY [[PHI]](s32) ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31 ; GREEDY-LABEL: name: phi_s32_ss_vcc_sbranch @@ -326,15 +327,16 @@ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1 ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; GREEDY: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; GREEDY: $sgpr0 = COPY [[PHI]](s32) ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31 bb.0: @@ -376,15 +378,16 @@ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; FAST: G_BRCOND [[ICMP]](s1), %bb.1 ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; FAST: $vgpr0 = COPY [[PHI]](s32) ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31 ; GREEDY-LABEL: name: phi_s32_sv_vcc_sbranch @@ -395,15 +398,16 @@ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1 ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; GREEDY: $vgpr0 = COPY [[PHI]](s32) ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31 bb.0: @@ -445,15 +449,16 @@ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; FAST: G_BRCOND [[ICMP]](s1), %bb.1 ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) + ; FAST: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; FAST: $vgpr0 = COPY [[PHI]](s32) ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31 ; GREEDY-LABEL: name: phi_s32_vs_vcc_sbranch @@ -464,15 +469,16 @@ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1 ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; GREEDY: $vgpr0 = COPY [[PHI]](s32) ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31 bb.0: @@ -514,15 +520,16 @@ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; FAST: G_BRCOND [[ICMP]](s1), %bb.1 ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; FAST: $vgpr0 = COPY [[PHI]](s32) ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31 ; GREEDY-LABEL: name: phi_s32_vv_vcc_sbranch @@ -533,15 +540,16 @@ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]] ; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1 ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1 + ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1 ; GREEDY: $vgpr0 = COPY [[PHI]](s32) ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31 bb.0: @@ -809,13 +817,14 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; FAST: G_BR %bb.2 ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch ; GREEDY: bb.0: @@ -835,13 +844,14 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -883,7 +893,8 @@ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -893,13 +904,13 @@ ; FAST: successors: %bb.2(0x80000000) ; FAST: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] ; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch ; GREEDY: bb.0: @@ -909,7 +920,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -919,13 +931,13 @@ ; GREEDY: successors: %bb.2(0x80000000) ; GREEDY: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] ; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -967,7 +979,8 @@ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -975,12 +988,13 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; FAST: G_BR %bb.2 ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]] + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch ; GREEDY: bb.0: @@ -990,7 +1004,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -998,12 +1013,13 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1 - ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]] + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -1395,7 +1411,8 @@ ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -1404,12 +1421,12 @@ ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) ; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; FAST: G_BR %bb.2 ; FAST: bb.2: - ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]] + ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch ; GREEDY: bb.0: @@ -1419,7 +1436,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -1428,12 +1446,12 @@ ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) ; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1) ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: - ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]] + ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1 + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -1484,13 +1502,14 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; FAST: G_BR %bb.2 ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1 - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) ; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch ; GREEDY: bb.0: @@ -1509,13 +1528,14 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]] ; GREEDY: G_BR %bb.2 ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1 - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) - ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]] + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32) bb.0: successors: %bb.1, %bb.2 @@ -1557,7 +1577,8 @@ ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -1574,9 +1595,9 @@ ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1 ; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) ; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch ; GREEDY: bb.0: @@ -1586,7 +1607,8 @@ ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]] ; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32) ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) @@ -1603,9 +1625,9 @@ ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1 ; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) bb.0: successors: %bb.1, %bb.2 @@ -1656,7 +1678,8 @@ ; FAST: G_BR %bb.2 ; FAST: bb.1: ; FAST: successors: %bb.2(0x80000000) - ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] ; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 ; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]] @@ -1664,9 +1687,9 @@ ; FAST: bb.2: ; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1 ; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) ; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch ; GREEDY: bb.0: @@ -1685,7 +1708,8 @@ ; GREEDY: G_BR %bb.2 ; GREEDY: bb.1: ; GREEDY: successors: %bb.2(0x80000000) - ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]] + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]] ; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 ; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]] @@ -1693,9 +1717,9 @@ ; GREEDY: bb.2: ; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1 ; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32) - ; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) - ; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) - ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]] + ; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1) + ; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]] ; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32) bb.0: successors: %bb.1, %bb.2 Index: llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir =================================================================== --- llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir +++ llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir @@ -108,8 +108,10 @@ ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY3]] ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $vgpr0 @@ -134,9 +136,10 @@ ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) - ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] - ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP1]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]] + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY3]], [[ICMP1]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 @@ -207,9 +210,10 @@ ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] - ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP]] + ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY1]] + ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY3]], [[ICMP]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s32) = COPY $vgpr0 @@ -757,10 +761,11 @@ ; CHECK-LABEL: name: xor_i1_vcc_constant ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 - ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] + ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] ; CHECK: [[C1:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true - ; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[C1]](s1) - ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[COPY1]] + ; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C1]](s1) + ; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[COPY2]] ; CHECK: S_NOP 0, implicit [[XOR]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s32) = G_CONSTANT i32 0