Index: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td @@ -502,6 +502,16 @@ def : MipsPat<(i32 (trunc (xor GPR64:$lhs, GPR64:$rhs))), (EXTRACT_SUBREG (XOR64 GPR64:$lhs, GPR64:$rhs), sub_32)>; +// variable shift instructions patterns +def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), + (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; +def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), + (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; +def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), + (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; +def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), + (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; + // 32-to-64-bit extension def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -131,9 +131,7 @@ ; 32R6: jr $ra ; 32R6: or $3, $[[T0]], $[[T11]] - ; FIXME: The sll instruction below is redundant. - ; GP64: sll $[[T0:[0-9]+]], $5, 0 - ; GP64: dsrav $2, $4, $[[T0]] + ; GP64: dsrav $2, $4, $5 %r = ashr i64 %a, %b ret i64 %r @@ -146,11 +144,11 @@ ; GP32: lw $25, %call16(__ashrti3)($gp) ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: move $3, $[[T1]] - ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] @@ -163,35 +161,34 @@ ; M3: jr $ra ; M3: nop - ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 - ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] - ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] - ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] - ; GP64-NOT-R6: dsrav $2, $4, $[[T0]] - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 - + ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 + ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 + ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] + ; GP64-NOT-R6: dsrav $2, $4, $7 + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32 ; GP64-NOT-R6: movn $3, $2, $[[T5]] ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31 ; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] - ; 64R6: sll $[[T0:[0-9]+]], $7, 0 - ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]] - ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32 + ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7 + ; 64R6: sll $[[T1:[0-9]+]], $7, 0 + ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 32 ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 - ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]] ; 64R6: dsra $[[T5:[0-9]+]], $4, 31 ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] ; 64R6: or $2, $[[T6]], $[[T4]] - ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]] + ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7 ; 64R6: dsll $[[T8:[0-9]+]], $4, 1 - ; 64R6: not $[[T9:[0-9]+]], $[[T0]] + ; 64R6: not $[[T9:[0-9]+]], $[[T1]] ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] - ; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]] ; 64R6: jr $ra ; 64R6: or $3, $[[T13]], $[[T12]] Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -125,8 +125,7 @@ ; 32R6: jr $ra ; 32R6: seleqz $2, $[[T7]], $[[T5]] - ; GP64: sll $[[T0:[0-9]+]], $5, 0 - ; GP64: dsrlv $2, $4, $[[T0]] + ; GP64: dsrlv $2, $4, $5 %r = lshr i64 %a, %b ret i64 %r @@ -139,11 +138,11 @@ ; GP32: lw $25, %call16(__lshrti3)($gp) ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: dsrlv $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: move $3, $[[T1]] - ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] @@ -156,32 +155,32 @@ ; M3: jr $ra ; M3: nop - ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 - ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] - ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] - ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] - ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]] - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 + ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7 + ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1 + ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]] + ; GP64-NOT-R6: dsrlv $2, $4, $7 + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32 ; GP64-NOT-R6: movn $3, $2, $[[T5]] ; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: movn $2, $zero, $1 - ; 64R6: sll $[[T0:[0-9]+]], $7, 0 - ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] - ; 64R6: dsll $[[T2:[0-9]+]], $4, 1 - ; 64R6: not $[[T3:[0-9]+]], $[[T0]] - ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]] - ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 + ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7 + ; 64R6: dsll $[[T1:[0-9]+]], $4, 1 + ; 64R6: sll $[[T2:[0-9]+]], $7, 0 + ; 64R6: not $[[T3:[0-9]+]], $[[T2]] + ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] - ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]] + ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7 ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ; 64R6: or $3, $[[T10]], $[[T8]] ; 64R6: jr $ra - ; 64R6: seleqz $2, $[[T0]], $[[T7]] + ; 64R6: seleqz $2, $[[T9]], $[[T7]] %r = lshr i128 %a, %b ret i128 %r Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/shl.ll @@ -137,8 +137,7 @@ ; 32R6: jr $ra ; 32R6: seleqz $3, $[[T7]], $[[T5]] - ; GP64: sll $[[T0:[0-9]+]], $5, 0 - ; GP64: dsllv $2, $4, $1 + ; GP64: dsllv $2, $4, $5 %r = shl i64 %a, %b ret i64 %r @@ -151,11 +150,11 @@ ; GP32: lw $25, %call16(__ashlti3)($gp) ; M3: sll $[[T0:[0-9]+]], $7, 0 - ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]] + ; M3: dsllv $[[T1:[0-9]+]], $5, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: move $2, $[[T1]] - ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]] + ; M3: dsllv $[[T4:[0-9]+]], $4, $7 ; M3: dsrl $[[T5:[0-9]+]], $5, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] @@ -168,32 +167,32 @@ ; M3: jr $ra ; M3: nop - ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 - ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] - ; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1 - ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] - ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]] - ; GP64-NOT-R6: dsllv $3, $5, $[[T0]] - ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 + ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7 + ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1 + ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]] + ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]] + ; GP64-NOT-R6: dsllv $3, $5, $7 + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 32 ; GP64-NOT-R6: movn $2, $3, $[[T5]] ; GP64-NOT-R6: jr $ra ; GP64-NOT-R6: movn $3, $zero, $1 - ; 64R6: sll $[[T0:[0-9]+]], $7, 0 - ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] - ; 64R6: dsrl $[[T2:[0-9]+]], $5, 1 - ; 64R6: not $[[T3:[0-9]+]], $[[T0]] - ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]] - ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 + ; 64R6: dsllv $[[T0:[0-9]+]], $4, $7 + ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1 + ; 64R6: sll $[[T2:[0-9]+]], $7, 0 + ; 64R6: not $[[T3:[0-9]+]], $[[T2]] + ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 32 ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] - ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]] + ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7 ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] ; 64R6: or $2, $[[T10]], $[[T8]] ; 64R6: jr $ra - ; 64R6: seleqz $3, $[[T0]], $[[T7]] + ; 64R6: seleqz $3, $[[T9]], $[[T7]] %r = shl i128 %a, %b ret i128 %r Index: llvm/trunk/test/CodeGen/Mips/mips64shift.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/mips64shift.ll +++ llvm/trunk/test/CodeGen/Mips/mips64shift.ll @@ -65,7 +65,8 @@ define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: drotrv +; CHECK-NOT: sll +; CHECK: drotrv %shr = lshr i64 %a0, %a1 %sub = sub i64 64, %a1 %shl = shl i64 %a0, %sub @@ -75,7 +76,8 @@ define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: drotrv +; CHECK-NOT: sll +; CHECK: drotrv %shl = shl i64 %a0, %a1 %sub = sub i64 64, %a1 %shr = lshr i64 %a0, %sub