Index: llvm/include/llvm/CodeGen/TargetInstrInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -970,6 +970,13 @@
     return None;
   }
 
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  virtual bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                           bool IgnoreBundle = false) const {
+    return false;
+  }
+
   /// Store the specified register of the given register class to the specified
   /// stack frame index. The store instruction is to be added to the given
   /// machine basic block before the specified machine instruction. If isKill
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -863,7 +863,8 @@
       MI = &*std::next(Before);
     }
 
-    if (MI->isCall() && DAG->getTarget().Options.EnableDebugEntryValues)
+    if (TII->isCandidateForCallSiteEntry(*MI) &&
+        DAG->getTarget().Options.EnableDebugEntryValues)
       MF.addCallArgsForwardingRegs(MI, DAG->getSDCallSiteInfo(Node));
 
     return MI;
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -277,6 +277,11 @@
   Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                                  Register Reg) const override;
 
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                   bool IgnoreBundle = false) const override;
+
 #define GET_INSTRINFO_HELPER_DECLS
 #include "AArch64GenInstrInfo.inc"
 
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -6667,5 +6667,24 @@
   return TargetInstrInfo::describeLoadedValue(MI, Reg);
 }
 
+bool AArch64InstrInfo::isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                                   bool IgnoreBundle) const {
+  bool IsCall = IgnoreBundle ? MI.isCall(MachineInstr::IgnoreBundle) :
+                               MI.isCall();
+  if (!IsCall)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case AArch64::BL:
+  case AArch64::BLR:
+  case AArch64::TCRETURNdi:
+  case AArch64::TCRETURNri:
+  case AArch64::TLSDESC_CALLSEQ:
+    return true;
+  }
+}
+
 #define GET_INSTRINFO_HELPERS
 #include "AArch64GenInstrInfo.inc"
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.h
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -457,6 +457,11 @@
 
   Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                       Register Reg) const override;
+
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                   bool IgnoreBundle = false) const override;
 };
 
 /// Get the operands corresponding to the given \p Pred value. By default, the
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -5373,6 +5373,27 @@
   return RegImmPair{MI.getOperand(1).getReg(), Offset};
 }
 
+bool ARMBaseInstrInfo::isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                                   bool IgnoreBundle) const {
+  bool IsCall = IgnoreBundle ? MI.isCall(MachineInstr::IgnoreBundle) :
+                               MI.isCall();
+  if (!IsCall)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case ARM::BL:
+  case ARM::BLX:
+  case ARM::BL_pred:
+  case ARM::TCRETURNdi:
+  case ARM::TCRETURNri:
+  case ARM::tTAILJMPd:
+  case ARM::tTAILJMPdND:
+    return true;
+  }
+}
+
 bool llvm::registerDefinedBetween(unsigned Reg,
                                   MachineBasicBlock::iterator From,
                                   MachineBasicBlock::iterator To,
Index: llvm/lib/Target/X86/X86InstrInfo.h
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.h
+++ llvm/lib/Target/X86/X86InstrInfo.h
@@ -527,6 +527,11 @@
   Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                                  Register Reg) const override;
 
+  /// Return true if the \c MI is a candidate for the call site info
+  /// (the 'callSites:') production.
+  bool isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                   bool IgnoreBundle = false) const override;
+
 protected:
   /// Commutes the operands in the given instruction by changing the operands
   /// order and/or changing the instruction's opcode and/or the immediate value
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3054,6 +3054,36 @@
   return None;
 }
 
+bool X86InstrInfo::isCandidateForCallSiteEntry(const MachineInstr &MI,
+                                               bool IgnoreBundle) const {
+  bool IsCall = IgnoreBundle ? MI.isCall(MachineInstr::IgnoreBundle) :
+                               MI.isCall();
+  if (!IsCall)
+    return false;
+
+  switch (MI.getOpcode()) {
+  default:
+    return false;
+  case X86::CALL64pcrel32:
+  case X86::CALLpcrel32:
+  case X86::CALL64m:
+  case X86::CALL32m:
+  case X86::CALL64r:
+  case X86::CALL32r:
+  case X86::TAILJMPd64:
+  case X86::TAILJMPd:
+  case X86::TAILJMPd64_CC:
+  case X86::TAILJMPd_CC:
+  case X86::TCRETURNdi64:
+  case X86::TCRETURNri64:
+  case X86::TCRETURNmi64:
+  case X86::TCRETURNdi:
+  case X86::TCRETURNri:
+  case X86::TCRETURNmi:
+    return true;
+  }
+}
+
 static unsigned getLoadStoreRegOpcode(unsigned Reg,
                                       const TargetRegisterClass *RC,
                                       bool isStackAligned,