diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -4434,6 +4434,11 @@
                                                    AssumptionCache *AC,
                                                    const Instruction *CxtI,
                                                    const DominatorTree *DT) {
+  if (auto C = isImpliedByDomCondition(CmpInst::ICMP_UGE, LHS, RHS, CxtI, DL)) {
+    if (*C)
+      return OverflowResult::NeverOverflows;
+    return OverflowResult::AlwaysOverflowsLow;
+  }
   ConstantRange LHSRange = computeConstantRangeIncludingKnownBits(
       LHS, /*ForSigned=*/false, DL, /*Depth=*/0, AC, CxtI, DT);
   ConstantRange RHSRange = computeConstantRangeIncludingKnownBits(
diff --git a/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll b/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll
--- a/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll
+++ b/llvm/test/Transforms/InstCombine/usub-overflow-known-by-implied-cond.ll
@@ -9,12 +9,9 @@
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[BB3:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB2:%.*]], label [[BB3]]
+; CHECK-NEXT:    br i1 false, label [[BB2:%.*]], label [[BB3]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    ret i32 undef
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -39,12 +36,10 @@
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[BB3:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
+; CHECK-NEXT:    br i1 false, label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nuw i32 [[A]], [[B]]
+; CHECK-NEXT:    ret i32 [[SUB1]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -70,12 +65,9 @@
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB2:%.*]], label [[BB3]]
+; CHECK-NEXT:    br i1 false, label [[BB2:%.*]], label [[BB3]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    ret i32 undef
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -100,12 +92,10 @@
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ugt i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
+; CHECK-NEXT:    br i1 false, label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nuw i32 [[A]], [[B]]
+; CHECK-NEXT:    ret i32 [[SUB1]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -131,12 +121,10 @@
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
+; CHECK-NEXT:    br i1 false, label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nuw i32 [[A]], [[B]]
+; CHECK-NEXT:    ret i32 [[SUB1]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -161,12 +149,9 @@
 ; CHECK-NEXT:    [[COND:%.*]] = icmp ult i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    br i1 [[COND]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
+; CHECK-NEXT:    br i1 true, label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    ret i32 undef
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;
@@ -252,12 +237,10 @@
 ; CHECK-NEXT:    [[AND:%.*]] = and i1 [[COND]], [[COND2:%.*]]
 ; CHECK-NEXT:    br i1 [[AND]], label [[BB1:%.*]], label [[BB3:%.*]]
 ; CHECK:       bb1:
-; CHECK-NEXT:    [[SUB1:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[A]], i32 [[B]])
-; CHECK-NEXT:    [[C1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 1
-; CHECK-NEXT:    br i1 [[C1]], label [[BB3]], label [[BB2:%.*]]
+; CHECK-NEXT:    br i1 false, label [[BB3]], label [[BB2:%.*]]
 ; CHECK:       bb2:
-; CHECK-NEXT:    [[R1:%.*]] = extractvalue { i32, i1 } [[SUB1]], 0
-; CHECK-NEXT:    ret i32 [[R1]]
+; CHECK-NEXT:    [[SUB1:%.*]] = sub nuw i32 [[A]], [[B]]
+; CHECK-NEXT:    ret i32 [[SUB1]]
 ; CHECK:       bb3:
 ; CHECK-NEXT:    ret i32 0
 ;