Index: llvm/lib/CodeGen/ReachingDefAnalysis.cpp
===================================================================
--- llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -371,6 +371,12 @@
   return Def < 0 ? nullptr : getInstFromId(MBB, Def);
 }
 
+static bool mayHaveSideEffects(MachineInstr &MI) {
+  return MI.mayLoadOrStore() || MI.mayRaiseFPException() ||
+         MI.hasUnmodeledSideEffects() || MI.isTerminator() ||
+         MI.isCall() || MI.isBarrier() || MI.isBranch() || MI.isReturn();
+}
+
 // Can we safely move 'From' to just before 'To'? To satisfy this, 'From' must
 // not define a register that is used by any instructions, after and including,
 // 'To'. These instructions also must not redefine any of Froms operands.
@@ -392,10 +398,13 @@
   }
 
   // Now walk checking that the rest of the instructions will compute the same
-  // value.
+  // value and that we're not overwriting anything. Don't move the instruction
+  // past any memory, control-flow or other ambigious instructions.
   for (auto I = ++Iterator(From), E = Iterator(To); I != E; ++I) {
+    if (mayHaveSideEffects(*I))
+      return false;
     for (auto &MO : I->operands())
-      if (MO.isReg() && MO.getReg() && MO.isUse() && Defs.count(MO.getReg()))
+      if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg()))
         return false;
   }
   return true;
@@ -430,8 +439,7 @@
                                     InstSet &ToRemove, InstSet &Ignore) const {
   if (Visited.count(MI) || Ignore.count(MI))
     return true;
-  else if (MI->mayLoadOrStore() || MI->hasUnmodeledSideEffects() ||
-           MI->isBranch() || MI->isTerminator() || MI->isReturn()) {
+  else if (mayHaveSideEffects(*MI)) {
     // Unless told to ignore the instruction, don't remove anything which has
     // side effects.
     return false;
Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -390,6 +390,8 @@
   // The element count register maybe defined after InsertPt, in which case we
   // need to try to move either InsertPt or the def so that the [w|d]lstp can
   // use the value.
+  // TODO: On failing to move an instruction, check if the count is provided by
+  // a mov and whether we can use the mov operand directly.
   MachineBasicBlock *InsertBB = StartInsertPt->getParent();
   if (!RDA->isReachingDefLiveOut(StartInsertPt, NumElements)) {
     if (auto *ElemDef = RDA->getLocalLiveOutMIDef(InsertBB, NumElements)) {
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/cant-move-def-past-mem.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/cant-move-def-past-mem.mir
@@ -0,0 +1,152 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+--- |
+  define dso_local arm_aapcs_vfpcc void @start_before_elems(i32* noalias nocapture %a, i8* nocapture readonly %b, i8* nocapture readonly %c, i32 %N) {
+  entry:
+    %div = lshr i32 %N, 1
+    %cmp9 = icmp eq i32 %div, 0
+    %0 = add nuw i32 %div, 3
+    %1 = lshr i32 %0, 2
+    %2 = shl nuw i32 %1, 2
+    %3 = add i32 %2, -4
+    %4 = lshr i32 %3, 2
+    %5 = add nuw nsw i32 %4, 1
+    br i1 %cmp9, label %for.cond.cleanup, label %vector.ph
+
+  vector.ph:                                        ; preds = %entry
+    call void @llvm.set.loop.iterations.i32(i32 %5)
+    store i32 0, i32* %a
+    br label %vector.body
+
+  vector.body:                                      ; preds = %vector.body, %vector.ph
+    %lsr.iv8 = phi i32 [ %lsr.iv.next, %vector.body ], [ %5, %vector.ph ]
+    %lsr.iv5 = phi i8* [ %scevgep6, %vector.body ], [ %b, %vector.ph ]
+    %lsr.iv2 = phi i8* [ %scevgep3, %vector.body ], [ %c, %vector.ph ]
+    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
+    %6 = phi i32 [ %div, %vector.ph ], [ %8, %vector.body ]
+    %lsr.iv57 = bitcast i8* %lsr.iv5 to <4 x i8>*
+    %lsr.iv24 = bitcast i8* %lsr.iv2 to <4 x i8>*
+    %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
+    %7 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %6)
+    %8 = sub i32 %6, 4
+    %wide.masked.load = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv57, i32 1, <4 x i1> %7, <4 x i8> undef)
+    %9 = zext <4 x i8> %wide.masked.load to <4 x i32>
+    %wide.masked.load13 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* %lsr.iv24, i32 1, <4 x i1> %7, <4 x i8> undef)
+    %10 = zext <4 x i8> %wide.masked.load13 to <4 x i32>
+    %11 = mul nuw nsw <4 x i32> %10, %9
+    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %11, <4 x i32>* %lsr.iv1, i32 4, <4 x i1> %7)
+    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
+    %12 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv8, i32 1)
+    %13 = icmp ne i32 %12, 0
+    %scevgep3 = getelementptr i8, i8* %lsr.iv2, i32 4
+    %scevgep6 = getelementptr i8, i8* %lsr.iv5, i32 4
+    %lsr.iv.next = add nsw i32 %lsr.iv8, -1
+    br i1 %13, label %vector.body, label %for.cond.cleanup
+
+  for.cond.cleanup:                                 ; preds = %vector.body, %entry
+    ret void
+  }
+
+  declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32 immarg, <4 x i1>, <4 x i8>) #1
+  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>) #2
+  declare void @llvm.set.loop.iterations.i32(i32) #3
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
+  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
+
+...
+---
+name:            start_before_elems
+tracksRegLiveness: true
+alignment:       2
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+  - { reg: '$r3', virtual-reg: '' }
+frameInfo:
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: start_before_elems
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
+  ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
+  ; CHECK:   renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
+  ; CHECK:   t2CMPrs renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   t2IT 0, 8, implicit-def $itstate
+  ; CHECK:   tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
+  ; CHECK:   renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 1, 14, $noreg
+  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
+  ; CHECK:   t2STRi12 killed renamable $r12, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.a)
+  ; CHECK: bb.1.vector.body:
+  ; CHECK:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+  ; CHECK:   liveins: $lr, $r0, $r1, $r2
+  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRBU32_post killed renamable $r1, 4, 0, $noreg :: (load 4 from %ir.lsr.iv57, align 1)
+  ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRBU32_post killed renamable $r2, 4, 0, $noreg :: (load 4 from %ir.lsr.iv24, align 1)
+  ; CHECK:   renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
+  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv1, align 4)
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
+  ; CHECK: bb.2.for.cond.cleanup:
+  ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $pc
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $r0, $r1, $r2, $r3, $r4, $lr
+
+    frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r4, -8
+    renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
+    t2CMPrs renamable $r12, renamable $r3, 11, 14, $noreg, implicit-def $cpsr
+    t2IT 0, 8, implicit-def $itstate
+    tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
+    renamable $lr = t2MOVi 3, 14, $noreg, $noreg
+    renamable $r4, dead $cpsr = tMOVi8 1, 14, $noreg
+    renamable $lr = nuw t2ADDrs killed renamable $lr, renamable $r3, 11, 14, $noreg, $noreg
+    renamable $r3, dead $cpsr = tLSRri killed renamable $r3, 1, 14, $noreg
+    renamable $lr = t2BICri killed renamable $lr, 3, 14, $noreg, $noreg
+    renamable $lr = t2SUBri killed renamable $lr, 4, 14, $noreg, $noreg
+    renamable $lr = nuw nsw t2ADDrs killed renamable $r4, killed renamable $lr, 19, 14, $noreg, $noreg
+    t2DoLoopStart renamable $lr
+    t2STRi12 killed renamable $r12, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.a)
+    $r4 = tMOVr killed $lr, 14, $noreg
+
+  bb.1.vector.body:
+    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+    liveins: $r0, $r1, $r2, $r3, $r4
+
+    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+    $lr = tMOVr $r4, 14, $noreg
+    renamable $r4, dead $cpsr = nsw tSUBi8 killed $r4, 1, 14, $noreg
+    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
+    MVE_VPST 4, implicit $vpr
+    renamable $r1, renamable $q0 = MVE_VLDRBU32_post killed renamable $r1, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv57, align 1)
+    renamable $r2, renamable $q1 = MVE_VLDRBU32_post killed renamable $r2, 4, 1, renamable $vpr :: (load 4 from %ir.lsr.iv24, align 1)
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    renamable $q0 = nuw nsw MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
+    MVE_VPST 8, implicit $vpr
+    renamable $r0 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv1, align 4)
+    t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr
+    tB %bb.2, 14, $noreg
+
+  bb.2.for.cond.cleanup:
+    tPOP_RET 14, $noreg, def $r4, def $pc
+
+...
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-move-start-thru-it.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-move-start-thru-it.mir
@@ -0,0 +1,334 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+
+# TODO: We should be able to use tail predication. The transform fails to sink
+# DLSTP to the $r3 = tMOVr $r1 because of the IT block, but we could just
+# understand that the tMOVr is just a copy and so we could use $r1 directly
+# instead.
+
+--- |
+  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
+  declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>)
+  declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>)
+
+  define hidden arm_aapcs_vfpcc void @cond_count_after_dls(float* %pSrc, i32 %blockSize, float* nocapture %pResult) {
+  entry:
+    %cmp = icmp ult i32 %blockSize, 2
+    %0 = add i32 %blockSize, 3
+    %1 = icmp slt i32 %blockSize, 4
+    %smin1 = select i1 %1, i32 %blockSize, i32 4
+    %2 = sub i32 %0, %smin1
+    %3 = lshr i32 %2, 2
+    %4 = add nuw nsw i32 %3, 1
+    br i1 %cmp, label %cleanup, label %do.body.i.preheader
+
+  do.body.i.preheader:                              ; preds = %entry
+    %5 = add i32 %blockSize, 3
+    %6 = icmp slt i32 %blockSize, 4
+    %smin = select i1 %6, i32 %blockSize, i32 4
+    %7 = sub i32 %5, %smin
+    %8 = lshr i32 %7, 2
+    %9 = add nuw nsw i32 %8, 1
+    call void @llvm.set.loop.iterations.i32(i32 %4)
+    br label %do.body.i
+
+  do.body.i:                                        ; preds = %do.body.i.preheader, %do.body.i
+    %blkCnt.0.i = phi i32 [ %sub.i, %do.body.i ], [ %blockSize, %do.body.i.preheader ]
+    %sumVec.0.i = phi <4 x float> [ %13, %do.body.i ], [ zeroinitializer, %do.body.i.preheader ]
+    %pSrc.addr.0.i = phi float* [ %add.ptr.i, %do.body.i ], [ %pSrc, %do.body.i.preheader ]
+    %10 = phi i32 [ %4, %do.body.i.preheader ], [ %14, %do.body.i ]
+    %cast.pSrc.i = bitcast float* %pSrc.addr.0.i to <4 x float>*
+    %11 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0.i)
+    %12 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %cast.pSrc.i, i32 4, <4 x i1> %11, <4 x float> undef)
+    %13 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0.i, <4 x float> %12, <4 x i1> %11, <4 x float> undef)
+    %sub.i = add nsw i32 %blkCnt.0.i, -4
+    %add.ptr.i = getelementptr inbounds float, float* %pSrc.addr.0.i, i32 4
+    %14 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %10, i32 1)
+    %15 = icmp ne i32 %14, 0
+    br i1 %15, label %do.body.i, label %arm_mean_f32_mve.exit
+
+  arm_mean_f32_mve.exit:                            ; preds = %do.body.i
+    %16 = extractelement <4 x float> %13, i32 0
+    %17 = extractelement <4 x float> %13, i32 1
+    %add.i.i = fadd nnan ninf nsz float %16, %17
+    %18 = extractelement <4 x float> %13, i32 2
+    %add3.i.i = fadd nnan ninf nsz float %18, %add.i.i
+    %19 = extractelement <4 x float> %13, i32 3
+    %add5.i.i = fadd nnan ninf nsz float %19, %add3.i.i
+    %conv.i32 = uitofp i32 %blockSize to float
+    %div.i = fdiv nnan ninf nsz float %add5.i.i, %conv.i32
+    call void @llvm.set.loop.iterations.i32(i32 %9)
+    br label %do.body
+
+  do.body:                                          ; preds = %do.body, %arm_mean_f32_mve.exit
+    %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %sub, %do.body ]
+    %sumVec.0 = phi <4 x float> [ zeroinitializer, %arm_mean_f32_mve.exit ], [ %24, %do.body ]
+    %pSrc.addr.0 = phi float* [ %pSrc, %arm_mean_f32_mve.exit ], [ %add.ptr, %do.body ]
+    %20 = phi i32 [ %9, %arm_mean_f32_mve.exit ], [ %25, %do.body ]
+    %cast.pSrc = bitcast float* %pSrc.addr.0 to <4 x float>*
+    %21 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0)
+    %22 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %cast.pSrc, i32 4, <4 x i1> %21, <4 x float> undef)
+    %div.insert = insertelement <4 x float> undef, float %div.i, i32 0
+    %div.splat = shufflevector <4 x float> %div.insert, <4 x float> undef, <4 x i32> zeroinitializer
+    %23 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %22, <4 x float> %div.splat, <4 x i1> %21, <4 x float> undef)
+    %24 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %23, <4 x float> %sumVec.0, <4 x i1> %21, <4 x float> undef)
+    %sub = add nsw i32 %blkCnt.0, -4
+    %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4
+    %25 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %20, i32 1)
+    %26 = icmp ne i32 %25, 0
+    br i1 %26, label %do.body, label %do.end
+
+  do.end:                                           ; preds = %do.body
+    %27 = extractelement <4 x float> %24, i32 0
+    %28 = extractelement <4 x float> %24, i32 1
+    %add.i = fadd nnan ninf nsz float %27, %28
+    %29 = extractelement <4 x float> %24, i32 2
+    %add3.i = fadd nnan ninf nsz float %29, %add.i
+    %30 = extractelement <4 x float> %24, i32 3
+    %add5.i = fadd nnan ninf nsz float %30, %add3.i
+    %sub8 = add i32 %blockSize, -1
+    %conv = uitofp i32 %sub8 to float
+    %div = fdiv nnan ninf nsz float %add5.i, %conv
+    br label %cleanup
+
+  cleanup:                                          ; preds = %do.end, %entry
+    %storemerge = phi float [ %div, %do.end ], [ 0.000000e+00, %entry ]
+    store float %storemerge, float* %pResult, align 4
+    ret void
+  }
+
+  declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>)
+  declare void @llvm.set.loop.iterations.i32(i32)
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
+
+...
+---
+name:            cond_count_after_dls
+alignment:       4
+tracksRegLiveness: true
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+  stackSize:       16
+  offsetAdjustment: 0
+  maxAlignment:    4
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:
+  - id:              0
+    value:           'float 0.000000e+00'
+    alignment:       4
+    isTargetSpecific: false
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: cond_count_after_dls
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r4, $r5, $r7
+  ; CHECK:   frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 16
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r5, -12
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -16
+  ; CHECK:   tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   renamable $r4 = t2MOVi 4, 14, $noreg, $noreg
+  ; CHECK:   t2IT 11, 8, implicit-def $itstate
+  ; CHECK:   $r4 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r4, implicit killed $itstate
+  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 4, 14, $noreg
+  ; CHECK:   tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   tBcc %bb.2, 2, killed $cpsr
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.7(0x80000000)
+  ; CHECK:   liveins: $r2
+  ; CHECK:   renamable $s0 = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
+  ; CHECK:   tB %bb.7, 14, $noreg
+  ; CHECK: bb.2.do.body.i.preheader:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r4
+  ; CHECK:   renamable $r4, dead $cpsr = tSUBrr renamable $r1, killed renamable $r4, 14, $noreg
+  ; CHECK:   renamable $r5, dead $cpsr = tMOVi8 1, 14, $noreg
+  ; CHECK:   renamable $r4, dead $cpsr = tADDi8 killed renamable $r4, 3, 14, $noreg
+  ; CHECK:   tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr
+  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+  ; CHECK:   renamable $lr = nuw nsw t2ADDrs renamable $r5, killed renamable $r4, 19, 14, $noreg, $noreg
+  ; CHECK:   $r4 = tMOVr $r0, 14, $noreg
+  ; CHECK:   $lr = t2DLS killed renamable $lr
+  ; CHECK:   t2IT 11, 8, implicit-def $itstate
+  ; CHECK:   $r3 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
+  ; CHECK:   renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14, $noreg
+  ; CHECK:   renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg
+  ; CHECK:   dead renamable $r5 = nuw nsw t2ADDrs killed renamable $r5, killed renamable $r3, 19, 14, $noreg, $noreg
+  ; CHECK:   $r3 = tMOVr $r1, 14, $noreg
+  ; CHECK: bb.3.do.body.i:
+  ; CHECK:   successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4
+  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+  ; CHECK:   renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
+  ; CHECK:   MVE_VPST 4, implicit $vpr
+  ; CHECK:   renamable $r4, renamable $q1 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr :: (load 16 from %ir.cast.pSrc.i, align 4)
+  ; CHECK:   renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q0
+  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.3
+  ; CHECK: bb.4.arm_mean_f32_mve.exit:
+  ; CHECK:   successors: %bb.5(0x80000000)
+  ; CHECK:   liveins: $q0, $r0, $r1, $r2
+  ; CHECK:   renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg
+  ; CHECK:   $r3 = tMOVr $r1, 14, $noreg
+  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r3
+  ; CHECK:   renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg
+  ; CHECK:   renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit killed $q0
+  ; CHECK:   $s2 = VMOVSR $r1, 14, $noreg
+  ; CHECK:   renamable $s2 = VUITOS killed renamable $s2, 14, $noreg
+  ; CHECK:   renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg
+  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+  ; CHECK: bb.5.do.body:
+  ; CHECK:   successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $s4
+  ; CHECK:   $r4 = VMOVRS $s4, 14, $noreg
+  ; CHECK:   renamable $q2 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q2
+  ; CHECK:   renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg :: (load 16 from %ir.cast.pSrc, align 4)
+  ; CHECK:   renamable $q2 = nnan ninf nsz MVE_VADDf32 killed renamable $q3, killed renamable $q2, 0, $noreg, undef renamable $q2
+  ; CHECK:   renamable $q0 = nnan ninf nsz MVE_VSUBf32 killed renamable $q2, killed renamable $q0, 0, killed $noreg, undef renamable $q0
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.5
+  ; CHECK: bb.6.do.end:
+  ; CHECK:   successors: %bb.7(0x80000000)
+  ; CHECK:   liveins: $q0, $r1, $r2
+  ; CHECK:   renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg
+  ; CHECK:   renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14, $noreg
+  ; CHECK:   renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg
+  ; CHECK:   renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit killed $q0
+  ; CHECK:   $s2 = VMOVSR killed $r0, 14, $noreg
+  ; CHECK:   renamable $s2 = VUITOS killed renamable $s2, 14, $noreg
+  ; CHECK:   renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg
+  ; CHECK: bb.7.cleanup:
+  ; CHECK:   liveins: $r2, $s0
+  ; CHECK:   VSTRS killed renamable $s0, killed renamable $r2, 0, 14, $noreg :: (store 4 into %ir.pResult)
+  ; CHECK:   tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
+  ; CHECK: bb.8 (align 4):
+  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 4
+  bb.0.entry:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $r0, $r1, $r2, $r4, $r5, $r7, $lr
+
+    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    frame-setup CFI_INSTRUCTION offset $r5, -12
+    frame-setup CFI_INSTRUCTION offset $r4, -16
+    tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr
+    renamable $r4 = t2MOVi 4, 14, $noreg, $noreg
+    t2IT 11, 8, implicit-def $itstate
+    $r4 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r4, implicit killed $itstate
+    renamable $r3, dead $cpsr = tMOVi8 4, 14, $noreg
+    tCMPi8 renamable $r1, 2, 14, $noreg, implicit-def $cpsr
+    tBcc %bb.2, 2, killed $cpsr
+
+  bb.1:
+    successors: %bb.7(0x80000000)
+    liveins: $r2
+
+    renamable $s0 = VLDRS %const.0, 0, 14, $noreg :: (load 4 from constant-pool)
+    tB %bb.7, 14, $noreg
+
+  bb.2.do.body.i.preheader:
+    successors: %bb.3(0x80000000)
+    liveins: $r0, $r1, $r2, $r3, $r4
+
+    renamable $r4, dead $cpsr = tSUBrr renamable $r1, killed renamable $r4, 14, $noreg
+    renamable $r5, dead $cpsr = tMOVi8 1, 14, $noreg
+    renamable $r4, dead $cpsr = tADDi8 killed renamable $r4, 3, 14, $noreg
+    tCMPi8 renamable $r1, 4, 14, $noreg, implicit-def $cpsr
+    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+    renamable $lr = nuw nsw t2ADDrs renamable $r5, killed renamable $r4, 19, 14, $noreg, $noreg
+    $r4 = tMOVr $r0, 14, $noreg
+    t2DoLoopStart renamable $lr
+    t2IT 11, 8, implicit-def $itstate
+    $r3 = tMOVr renamable $r1, 11, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate
+    renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14, $noreg
+    renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14, $noreg
+    renamable $r5 = nuw nsw t2ADDrs killed renamable $r5, killed renamable $r3, 19, 14, $noreg, $noreg
+    $r3 = tMOVr $r1, 14, $noreg
+
+  bb.3.do.body.i:
+    successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+    liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5
+
+    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    MVE_VPST 4, implicit $vpr
+    renamable $r4, renamable $q1 = MVE_VLDRWU32_post killed renamable $r4, 16, 1, renamable $vpr :: (load 16 from %ir.cast.pSrc.i, align 4)
+    renamable $q0 = nnan ninf nsz MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q0
+    t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
+    tB %bb.4, 14, $noreg
+
+  bb.4.arm_mean_f32_mve.exit:
+    successors: %bb.5(0x80000000)
+    liveins: $q0, $r0, $r1, $r2, $r5
+
+    renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg
+    t2DoLoopStart $r5
+    $lr = tMOVr killed $r5, 14, $noreg
+    $r3 = tMOVr $r1, 14, $noreg
+    renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg
+    renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0
+    $s2 = VMOVSR $r1, 14, $noreg
+    renamable $s2 = VUITOS killed renamable $s2, 14, $noreg
+    renamable $s4 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg
+    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0
+
+  bb.5.do.body:
+    successors: %bb.5(0x7c000000), %bb.6(0x04000000)
+    liveins: $lr, $q0, $r0, $r1, $r2, $r3, $s4
+
+    $r4 = VMOVRS $s4, 14, $noreg
+    renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg
+    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 4, 14, $noreg
+    renamable $q2 = MVE_VDUP32 killed renamable $r4, 0, $noreg, undef renamable $q2
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    MVE_VPST 2, implicit $vpr
+    renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.cast.pSrc, align 4)
+    renamable $q2 = nnan ninf nsz MVE_VADDf32 killed renamable $q3, killed renamable $q2, 1, renamable $vpr, undef renamable $q2
+    renamable $q0 = nnan ninf nsz MVE_VSUBf32 killed renamable $q2, killed renamable $q0, 1, killed renamable $vpr, undef renamable $q0
+    t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
+    tB %bb.6, 14, $noreg
+
+  bb.6.do.end:
+    successors: %bb.7(0x80000000)
+    liveins: $q0, $r1, $r2
+
+    renamable $s4 = nnan ninf nsz VADDS renamable $s0, renamable $s1, 14, $noreg
+    renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14, $noreg
+    renamable $s4 = nnan ninf nsz VADDS renamable $s2, killed renamable $s4, 14, $noreg
+    renamable $s0 = nnan ninf nsz VADDS killed renamable $s3, killed renamable $s4, 14, $noreg, implicit $q0
+    $s2 = VMOVSR killed $r0, 14, $noreg
+    renamable $s2 = VUITOS killed renamable $s2, 14, $noreg
+    renamable $s0 = nnan ninf nsz VDIVS killed renamable $s0, killed renamable $s2, 14, $noreg
+
+  bb.7.cleanup:
+    liveins: $r2, $s0
+
+    VSTRS killed renamable $s0, killed renamable $r2, 0, 14, $noreg :: (store 4 into %ir.pResult)
+    tPOP_RET 14, $noreg, def $r4, def $r5, def $r7, def $pc
+
+  bb.8 (align 4):
+    CONSTPOOL_ENTRY 0, %const.0, 4
+
+...
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
===================================================================
--- llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
@@ -3,8 +3,6 @@
 
 # Test that, though the vctp operand is defined at the end of the block,
 # that the correct value is used for the dlstp.
-# TODO: The pass currently just bails instead of finding the correct
-# value.
 
 --- |
   define dso_local arm_aapcs_vfpcc void @start_before_elems(i32* noalias nocapture %a, i8* nocapture readonly %b, i8* nocapture readonly %c, i32 %N) local_unnamed_addr #0 {