diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -90,7 +90,7 @@
 }
 
 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
-// relocation types. We those pseudo-instructions while encoding them, meaning
+// relocation types. We expand pseudo-instructions while encoding them, meaning
 // AUIPC and JALR won't go through RISCV MC to MC compressed instruction
 // transformation. This is acceptable because AUIPC has no 16-bit form and
 // C_JALR have no immediate operand field.  We let linker relaxation deal with