Index: llvm/lib/Target/AArch64/AArch64SystemOperands.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -1006,7 +1006,7 @@ def : RWSysReg<"TRCSEQEVR2", 0b10, 0b001, 0b0000, 0b0010, 0b100>; def : RWSysReg<"TRCSEQRSTEVR", 0b10, 0b001, 0b0000, 0b0110, 0b100>; def : RWSysReg<"TRCSEQSTR", 0b10, 0b001, 0b0000, 0b0111, 0b100>; -def : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; +def TRCEXTINSELR_PRIO_0 : RWSysReg<"TRCEXTINSELR", 0b10, 0b001, 0b0000, 0b1000, 0b100>; def : RWSysReg<"TRCCNTRLDVR0", 0b10, 0b001, 0b0000, 0b0000, 0b101>; def : RWSysReg<"TRCCNTRLDVR1", 0b10, 0b001, 0b0000, 0b0001, 0b101>; def : RWSysReg<"TRCCNTRLDVR2", 0b10, 0b001, 0b0000, 0b0010, 0b101>; @@ -1472,7 +1472,7 @@ // Name Op0 Op1 CRn CRm Op2 def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; // TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR -def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; +def TRCEXTINSELR_PRIO_1 : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>; def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>; def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>; Index: llvm/test/MC/AArch64/ete-sysregs.s =================================================================== --- llvm/test/MC/AArch64/ete-sysregs.s +++ llvm/test/MC/AArch64/ete-sysregs.s @@ -11,8 +11,8 @@ mrs x0, TRCEXTINSELR3 // CHECK: mrs x0, TRCRSR // encoding: [0x00,0x0a,0x31,0xd5] -// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5] -// CHECK: mrs x0, TRCEXTINSELR0 // encoding: [0x80,0x08,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5] // CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5] // CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5] // CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5] @@ -26,8 +26,8 @@ msr TRCEXTINSELR3, x0 // CHECK: msr TRCRSR, x0 // encoding: [0x00,0x0a,0x11,0xd5] -// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5] -// CHECK: msr TRCEXTINSELR0, x0 // encoding: [0x80,0x08,0x11,0xd5] +// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5] +// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5] // CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5] // CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5] // CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5] Index: llvm/test/MC/AArch64/trace-regs.s =================================================================== --- llvm/test/MC/AArch64/trace-regs.s +++ llvm/test/MC/AArch64/trace-regs.s @@ -269,7 +269,7 @@ // CHECK: mrs x26, {{trcseqevr2|TRCSEQEVR2}} // encoding: [0x9a,0x02,0x31,0xd5] // CHECK: mrs x14, {{trcseqrstevr|TRCSEQRSTEVR}} // encoding: [0x8e,0x06,0x31,0xd5] // CHECK: mrs x4, {{trcseqstr|TRCSEQSTR}} // encoding: [0x84,0x07,0x31,0xd5] -// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR0}} // encoding: [0x91,0x08,0x31,0xd5] +// CHECK: mrs x17, {{trcextinselr|TRCEXTINSELR}} // encoding: [0x91,0x08,0x31,0xd5] // CHECK: mrs x21, {{trccntrldvr0|TRCCNTRLDVR0}} // encoding: [0xb5,0x00,0x31,0xd5] // CHECK: mrs x10, {{trccntrldvr1|TRCCNTRLDVR1}} // encoding: [0xaa,0x01,0x31,0xd5] // CHECK: mrs x20, {{trccntrldvr2|TRCCNTRLDVR2}} // encoding: [0xb4,0x02,0x31,0xd5] @@ -618,7 +618,7 @@ // CHECK: msr {{trcseqevr2|TRCSEQEVR2}}, x16 // encoding: [0x90,0x02,0x11,0xd5] // CHECK: msr {{trcseqrstevr|TRCSEQRSTEVR}}, x16 // encoding: [0x90,0x06,0x11,0xd5] // CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 // encoding: [0x99,0x07,0x11,0xd5] -// CHECK: msr {{trcextinselr|TRCEXTINSELR0}}, x29 // encoding: [0x9d,0x08,0x11,0xd5] +// CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 // encoding: [0x9d,0x08,0x11,0xd5] // CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 // encoding: [0xb4,0x00,0x11,0xd5] // CHECK: msr {{trccntrldvr1|TRCCNTRLDVR1}}, x20 // encoding: [0xb4,0x01,0x11,0xd5] // CHECK: msr {{trccntrldvr2|TRCCNTRLDVR2}}, x22 // encoding: [0xb6,0x02,0x11,0xd5] Index: llvm/test/MC/Disassembler/AArch64/ete.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/ete.txt +++ llvm/test/MC/Disassembler/AArch64/ete.txt @@ -24,7 +24,7 @@ # CHECK: msr TRCRSR, x0 [0x80,0x08,0x11,0xd5] -# CHECK: msr TRCEXTINSELR0, x0 +# CHECK: msr TRCEXTINSELR, x0 [0x80,0x09,0x11,0xd5] # CHECK: msr TRCEXTINSELR1, x0 Index: llvm/test/MC/Disassembler/AArch64/trace-regs.txt =================================================================== --- llvm/test/MC/Disassembler/AArch64/trace-regs.txt +++ llvm/test/MC/Disassembler/AArch64/trace-regs.txt @@ -456,7 +456,7 @@ 0x99 0x7 0x11 0xd5 # CHECK: msr {{trcseqstr|TRCSEQSTR}}, x25 0x9d 0x8 0x11 0xd5 -# CHECK: msr {{trcextinselr|TRCEXTINSELR0}}, x29 +# CHECK: msr {{trcextinselr|TRCEXTINSELR}}, x29 0xb4 0x0 0x11 0xd5 # CHECK: msr {{trccntrldvr0|TRCCNTRLDVR0}}, x20 0xb4 0x1 0x11 0xd5