diff --git a/clang/include/clang/Basic/BuiltinsWebAssembly.def b/clang/include/clang/Basic/BuiltinsWebAssembly.def
--- a/clang/include/clang/Basic/BuiltinsWebAssembly.def
+++ b/clang/include/clang/Basic/BuiltinsWebAssembly.def
@@ -73,20 +73,20 @@
 TARGET_BUILTIN(__builtin_wasm_swizzle_v8x16, "V16cV16cV16c", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i8x16, "iV16cIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i8x16, "iV16cIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i8x16, "iV16cIi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extract_lane_s_i16x8, "iV8sIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i16x8, "iV8sIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_u_i16x8, "iV8sIi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extract_lane_i32x4, "iV4iIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_i64x2, "LLiV2LLiIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_i64x2, "LLiV2LLiIi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extract_lane_f32x4, "fV4fIi", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_extract_lane_f64x2, "dV2dIi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_extract_lane_f64x2, "dV2dIi", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i8x16, "V16cV16cIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i16x8, "V8sV8sIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i32x4, "V4iV4iIii", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2LLiV2LLiIiLLi", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2LLiV2LLiIiLLi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_f32x4, "V4fV4fIif", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_replace_lane_f64x2, "V2dV2dIid", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_replace_lane_f64x2, "V2dV2dIid", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i8x16, "V16cV16cV16c", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i8x16, "V16cV16cV16c", "nc", "simd128")
@@ -98,8 +98,8 @@
 TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i16x8, "V8sV8sV8s", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, "V16cV16cV16c", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, "V8sV8sV8s", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, "V16cV16cV16c", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, "V8sV8sV8s", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_bitselect, "V4iV4iV4iV4i", "nc", "simd128")
 
@@ -113,20 +113,20 @@
 TARGET_BUILTIN(__builtin_wasm_all_true_i64x2, "iV2LLi", "nc", "unimplemented-simd128")
 
 TARGET_BUILTIN(__builtin_wasm_abs_f32x4, "V4fV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_abs_f64x2, "V2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_abs_f64x2, "V2dV2d", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_min_f32x4, "V4fV4fV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_f32x4, "V4fV4fV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_min_f64x2, "V2dV2dV2d", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_max_f64x2, "V2dV2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_min_f64x2, "V2dV2dV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_max_f64x2, "V2dV2dV2d", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_dot_s_i32x4_i16x8, "V4iV8sV8s", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_sqrt_f32x4, "V4fV4f", "nc", "unimplemented-simd128")
-TARGET_BUILTIN(__builtin_wasm_sqrt_f64x2, "V2dV2d", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_sqrt_f32x4, "V4fV4f", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_sqrt_f64x2, "V2dV2d", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_qfma_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
+TARGET_BUILTIN(__builtin_wasm_qfms_f32x4, "V4fV4fV4fV4f", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfma_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
 TARGET_BUILTIN(__builtin_wasm_qfms_f64x2, "V2dV2dV2dV2d", "nc", "unimplemented-simd128")
 
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -61,8 +61,6 @@
     addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
-  }
-  if (Subtarget->hasUnimplementedSIMD128()) {
     addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
     addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
   }
@@ -116,10 +114,8 @@
     for (auto T : {MVT::i32, MVT::i64})
       setOperationAction(Op, T, Expand);
     if (Subtarget->hasSIMD128())
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
         setOperationAction(Op, T, Expand);
-    if (Subtarget->hasUnimplementedSIMD128())
-      setOperationAction(Op, MVT::v2i64, Expand);
   }
 
   // SIMD-specific configuration
@@ -130,83 +126,64 @@
         setOperationAction(Op, T, Legal);
 
     // Custom lower BUILD_VECTORs to minimize number of replace_lanes
-    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                   MVT::v2f64})
       setOperationAction(ISD::BUILD_VECTOR, T, Custom);
-    if (Subtarget->hasUnimplementedSIMD128())
-      for (auto T : {MVT::v2i64, MVT::v2f64})
-        setOperationAction(ISD::BUILD_VECTOR, T, Custom);
 
     // We have custom shuffle lowering to expose the shuffle mask
-    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
+    for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                   MVT::v2f64})
       setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
-    if (Subtarget->hasUnimplementedSIMD128())
-      for (auto T: {MVT::v2i64, MVT::v2f64})
-        setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom);
 
     // Custom lowering since wasm shifts must have a scalar shift amount
-    for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+    for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
         setOperationAction(Op, T, Custom);
-      if (Subtarget->hasUnimplementedSIMD128())
-        setOperationAction(Op, MVT::v2i64, Custom);
-    }
 
     // Custom lower lane accesses to expand out variable indices
-    for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
+    for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                     MVT::v2f64})
         setOperationAction(Op, T, Custom);
-      if (Subtarget->hasUnimplementedSIMD128())
-        for (auto T : {MVT::v2i64, MVT::v2f64})
-          setOperationAction(Op, T, Custom);
-    }
 
     // There is no i64x2.mul instruction
+    // TODO: Actually, there is now. Implement it.
     setOperationAction(ISD::MUL, MVT::v2i64, Expand);
 
     // There are no vector select instructions
-    for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32})
+    for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                     MVT::v2f64})
         setOperationAction(Op, T, Expand);
-      if (Subtarget->hasUnimplementedSIMD128())
-        for (auto T : {MVT::v2i64, MVT::v2f64})
-          setOperationAction(Op, T, Expand);
-    }
 
     // Expand integer operations supported for scalars but not SIMD
     for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV,
-                    ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
-      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+                    ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
         setOperationAction(Op, T, Expand);
-      if (Subtarget->hasUnimplementedSIMD128())
-        setOperationAction(Op, MVT::v2i64, Expand);
-    }
 
     // But we do have integer min and max operations
-    if (Subtarget->hasUnimplementedSIMD128()) {
-      for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
-        for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
-          setOperationAction(Op, T, Legal);
-    }
+    for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
+      for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
+        setOperationAction(Op, T, Legal);
 
     // Expand float operations supported for scalars but not SIMD
     for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
                     ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
-                    ISD::FEXP, ISD::FEXP2, ISD::FRINT}) {
-      setOperationAction(Op, MVT::v4f32, Expand);
-      if (Subtarget->hasUnimplementedSIMD128())
-        setOperationAction(Op, MVT::v2f64, Expand);
-    }
+                    ISD::FEXP, ISD::FEXP2, ISD::FRINT})
+      for (auto T : {MVT::v4f32, MVT::v2f64})
+        setOperationAction(Op, T, Expand);
 
     // Expand operations not supported for i64x2 vectors
-    if (Subtarget->hasUnimplementedSIMD128())
-      for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)
-        setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);
-
-    // Expand additional SIMD ops that V8 hasn't implemented yet
-    if (!Subtarget->hasUnimplementedSIMD128()) {
-      setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
-      setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
-    }
+    for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC)
+      setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom);
+
+    // 64x2 conversions are not in the spec
+    if (!Subtarget->hasUnimplementedSIMD128())
+      for (auto Op :
+           {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT})
+        for (auto T : {MVT::v2i64, MVT::v2f64})
+          setOperationAction(Op, T, Expand);
   }
 
   // As a special case, these operators use the type to mean the type to
@@ -1533,7 +1510,6 @@
   // expanding all i64x2 SETCC nodes, but that seems to expand f64x2 SETCC nodes
   // (which return i64x2 results) as well. So instead we manually unroll i64x2
   // comparisons here.
-  assert(Subtarget->hasUnimplementedSIMD128());
   assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);
   SmallVector<SDValue, 2> LHS, RHS;
   DAG.ExtractVectorElements(Op->getOperand(0), LHS);
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -371,7 +371,6 @@
 }
 
 defm "" : ExtractLaneExtended<"_s", 5>;
-let Predicates = [HasUnimplementedSIMD128] in
 defm "" : ExtractLaneExtended<"_u", 6>;
 defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
 defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
@@ -739,7 +738,7 @@
 } // isCommutable = 1
 
 // Integer unsigned rounding average: avgr_u
-let isCommutable = 1, Predicates = [HasUnimplementedSIMD128] in {
+let isCommutable = 1 in {
 defm AVGR_U : SIMDBinary<v16i8, "i8x16", int_wasm_avgr_unsigned, "avgr_u", 217>;
 defm AVGR_U : SIMDBinary<v8i16, "i16x8", int_wasm_avgr_unsigned, "avgr_u", 218>;
 }
@@ -781,7 +780,6 @@
 defm NEG : SIMDUnaryFP<fneg, "neg", 150>;
 
 // Square root: sqrt
-let Predicates = [HasUnimplementedSIMD128] in
 defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
 
 //===----------------------------------------------------------------------===//
@@ -805,7 +803,6 @@
 defm MUL : SIMDBinaryFP<fmul, "mul", 156>;
 
 // Division: div
-let Predicates = [HasUnimplementedSIMD128] in
 defm DIV : SIMDBinaryFP<fdiv, "div", 157>;
 
 // NaN-propagating minimum: min
@@ -829,14 +826,20 @@
 // Integer to floating point: convert
 defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
 defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
+
+let Predicates = [HasUnimplementedSIMD128] in {
 defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
 defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
+}
 
 // Floating point to integer with saturation: trunc_sat
 defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
 defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
+
+let Predicates = [HasUnimplementedSIMD128] in {
 defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
 defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
+}
 
 // Widening operations
 multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
diff --git a/llvm/test/CodeGen/WebAssembly/simd-arith.ll b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-arith.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-arith.ll
@@ -905,7 +905,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: add_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype add_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -916,7 +915,6 @@
 
 ; CHECK-LABEL: sub_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -928,7 +926,6 @@
 ; v2i64.mul is not in spec
 ; CHECK-LABEL: mul_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NOT: i64x2.mul
 ; SIMD128: i64x2.extract_lane
 ; SIMD128: i64.mul
@@ -1150,7 +1147,6 @@
 
 ; CHECK-LABEL: and_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype and_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1161,7 +1157,6 @@
 
 ; CHECK-LABEL: or_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype or_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1172,7 +1167,6 @@
 
 ; CHECK-LABEL: xor_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype xor_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.xor $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1183,7 +1177,6 @@
 
 ; CHECK-LABEL: not_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype not_v2i64 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1209,7 +1202,6 @@
 
 ; CHECK-LABEL: bitselect_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype bitselect_v2i64 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-SLOW-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $1, $2, $0{{$}}
 ; SIMD128-SLOW-NEXT: return $pop[[R]]{{$}}
@@ -1401,7 +1393,6 @@
 
 ; CHECK-LABEL: div_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-VM-NOT: f32x4.div
 ; SIMD128-NEXT: .functype div_v4f32 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.div $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1422,7 +1413,6 @@
 
 ; CHECK-LABEL: sqrt_v4f32:
 ; NO-SIMD128-NOT: f32x4
-; SIMD128-VM-NOT: f32x4.sqrt
 ; SIMD128-NEXT: .functype sqrt_v4f32 (v128) -> (v128){{$}}
 ; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1565,7 +1555,6 @@
 
 ; CHECK-LABEL: add_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype add_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.add $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1576,7 +1565,6 @@
 
 ; CHECK-LABEL: sub_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype sub_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1587,7 +1575,6 @@
 
 ; CHECK-LABEL: div_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype div_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.div $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1598,7 +1585,6 @@
 
 ; CHECK-LABEL: mul_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f62x2
 ; SIMD128-NEXT: .functype mul_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll b/llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-bitcasts.ll
@@ -1,5 +1,4 @@
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+unimplemented-simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
 ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals | FileCheck %s --check-prefixes CHECK,NO-SIMD128
 
 ; Test that bitcasts between vector types are lowered to zero instructions
@@ -33,8 +32,6 @@
 
 ; CHECK-LABEL: v16i8_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
   %res = bitcast <16 x i8> %v to <2 x i64>
@@ -51,8 +48,6 @@
 
 ; CHECK-LABEL: v16i8_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
   %res = bitcast <16 x i8> %v to <2 x double>
@@ -85,8 +80,6 @@
 
 ; CHECK-LABEL: v8i16_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
   %res = bitcast <8 x i16> %v to <2 x i64>
@@ -103,8 +96,6 @@
 
 ; CHECK-LABEL: v8i16_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
   %res = bitcast <8 x i16> %v to <2 x double>
@@ -137,8 +128,6 @@
 
 ; CHECK-LABEL: v4i32_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
   %res = bitcast <4 x i32> %v to <2 x i64>
@@ -155,8 +144,6 @@
 
 ; CHECK-LABEL: v4i32_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
   %res = bitcast <4 x i32> %v to <2 x double>
@@ -165,7 +152,6 @@
 
 ; CHECK-LABEL: v2i64_to_v16i8:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <16 x i8>
@@ -174,7 +160,6 @@
 
 ; CHECK-LABEL: v2i64_to_v8i16:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <8 x i16>
@@ -183,7 +168,6 @@
 
 ; CHECK-LABEL: v2i64_to_v4i32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <4 x i32>
@@ -192,7 +176,6 @@
 
 ; CHECK-LABEL: v2i64_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <2 x i64>
@@ -201,7 +184,6 @@
 
 ; CHECK-LABEL: v2i64_to_v4f32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <4 x float>
@@ -210,7 +192,6 @@
 
 ; CHECK-LABEL: v2i64_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
   %res = bitcast <2 x i64> %v to <2 x double>
@@ -243,8 +224,6 @@
 
 ; CHECK-LABEL: v4f32_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
   %res = bitcast <4 x float> %v to <2 x i64>
@@ -261,8 +240,6 @@
 
 ; CHECK-LABEL: v4f32_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM: v128.store
-; SIMD128-VM-NEXT: return{{$}}
 ; SIMD128: return $0
 define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
   %res = bitcast <4 x float> %v to <2 x double>
@@ -271,7 +248,6 @@
 
 ; CHECK-LABEL: v2f64_to_v16i8:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <16 x i8>
@@ -280,7 +256,6 @@
 
 ; CHECK-LABEL: v2f64_to_v8i16:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <8 x i16>
@@ -289,7 +264,6 @@
 
 ; CHECK-LABEL: v2f64_to_v4i32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <4 x i32>
@@ -298,7 +272,6 @@
 
 ; CHECK-LABEL: v2f64_to_v2i64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <2 x i64>
@@ -307,7 +280,6 @@
 
 ; CHECK-LABEL: v2f64_to_v4f32:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <4 x float>
@@ -316,7 +288,6 @@
 
 ; CHECK-LABEL: v2f64_to_v2f64:
 ; NO-SIMD128-NOT: return $0
-; SIMD128-VM-NOT: return $0
 ; SIMD128: return $0
 define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
   %res = bitcast <2 x double> %v to <2 x double>
diff --git a/llvm/test/CodeGen/WebAssembly/simd-build-pair.ll b/llvm/test/CodeGen/WebAssembly/simd-build-pair.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-build-pair.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-build-pair.ll
@@ -14,13 +14,7 @@
 ;    t8: ch = store<(store 8 into `i64* undef`, align 1)> t3:1, t24, undef:i32, undef:i32
 ;  t9: ch = WebAssemblyISD::RETURN t8
 
-; CHECK:      i32x4.extract_lane
-; CHECK-NEXT: i64.extend_i32_u
-; CHECK-NEXT: i32x4.extract_lane
-; CHECK-NEXT: i64.extend_i32_u
-; CHECK-NEXT: i64.const {{.*}} 32
-; CHECK-NEXT: i64.shl
-; CHECK-NEXT: i64.or
+; CHECK:      i64x2.extract_lane
 ; CHECK-NEXT: i64.store
 define void @build_pair_i32s() {
 entry:
diff --git a/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll b/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-comparisons.ll
@@ -1417,7 +1417,6 @@
 
 ; CHECK-LABEL: compare_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oeq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1428,7 +1427,6 @@
 
 ; CHECK-LABEL: compare_oeq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oeq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1439,7 +1437,6 @@
 
 ; CHECK-LABEL: compare_sext_oeq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oeq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1451,7 +1448,6 @@
 
 ; CHECK-LABEL: compare_sext_oeq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oeq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1463,7 +1459,6 @@
 
 ; CHECK-LABEL: compare_ogt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ogt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1474,7 +1469,6 @@
 
 ; CHECK-LABEL: compare_ogt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ogt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1485,7 +1479,6 @@
 
 ; CHECK-LABEL: compare_sext_ogt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ogt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1497,7 +1490,6 @@
 
 ; CHECK-LABEL: compare_sext_ogt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ogt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1509,7 +1501,6 @@
 
 ; CHECK-LABEL: compare_oge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1520,7 +1511,6 @@
 
 ; CHECK-LABEL: compare_oge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_oge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1531,7 +1521,6 @@
 
 ; CHECK-LABEL: compare_sext_oge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1543,7 +1532,6 @@
 
 ; CHECK-LABEL: compare_sext_oge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_oge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1555,7 +1543,6 @@
 
 ; CHECK-LABEL: compare_olt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_olt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1566,7 +1553,6 @@
 
 ; CHECK-LABEL: compare_olt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_olt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1577,7 +1563,6 @@
 
 ; CHECK-LABEL: compare_sext_olt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_olt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1589,7 +1574,6 @@
 
 ; CHECK-LABEL: compare_sext_olt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_olt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1601,7 +1585,6 @@
 
 ; CHECK-LABEL: compare_ole_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ole_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1612,7 +1595,6 @@
 
 ; CHECK-LABEL: compare_ole_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ole_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1623,7 +1605,6 @@
 
 ; CHECK-LABEL: compare_sext_ole_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ole_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1635,7 +1616,6 @@
 
 ; CHECK-LABEL: compare_sext_ole_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ole_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1647,7 +1627,6 @@
 
 ; CHECK-LABEL: compare_one_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_one_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
@@ -1662,7 +1641,6 @@
 
 ; CHECK-LABEL: compare_one_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_one_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1673,7 +1651,6 @@
 
 ; CHECK-LABEL: compare_sext_one_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_one_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}}
@@ -1689,7 +1666,6 @@
 
 ; CHECK-LABEL: compare_sext_one_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_one_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1701,7 +1677,6 @@
 
 ; CHECK-LABEL: compare_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -1714,7 +1689,6 @@
 
 ; CHECK-LABEL: compare_ord_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ord_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -1727,7 +1701,6 @@
 
 ; CHECK-LABEL: compare_sext_ord_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ord_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -1741,7 +1714,6 @@
 
 ; CHECK-LABEL: compare_sext_ord_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ord_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -1755,7 +1727,6 @@
 
 ; CHECK-LABEL: compare_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ueq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
@@ -1770,7 +1741,6 @@
 
 ; CHECK-LABEL: compare_ueq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ueq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1781,7 +1751,6 @@
 
 ; CHECK-LABEL: compare_sext_ueq_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ueq_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}}
@@ -1797,7 +1766,6 @@
 
 ; CHECK-LABEL: compare_sext_ueq_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ueq_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1809,7 +1777,6 @@
 
 ; CHECK-LABEL: compare_ugt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ugt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1821,7 +1788,6 @@
 
 ; CHECK-LABEL: compare_ugt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ugt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1832,7 +1798,6 @@
 
 ; CHECK-LABEL: compare_sext_ugt_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ugt_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1845,7 +1810,6 @@
 
 ; CHECK-LABEL: compare_sext_ugt_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ugt_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1857,7 +1821,6 @@
 
 ; CHECK-LABEL: compare_uge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1869,7 +1832,6 @@
 
 ; CHECK-LABEL: compare_uge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1880,7 +1842,6 @@
 
 ; CHECK-LABEL: compare_sext_uge_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uge_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1893,7 +1854,6 @@
 
 ; CHECK-LABEL: compare_sext_uge_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uge_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1905,7 +1865,6 @@
 
 ; CHECK-LABEL: compare_ult_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ult_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1917,7 +1876,6 @@
 
 ; CHECK-LABEL: compare_ult_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ult_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1928,7 +1886,6 @@
 
 ; CHECK-LABEL: compare_sext_ult_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ult_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ge $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1941,7 +1898,6 @@
 
 ; CHECK-LABEL: compare_sext_ult_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ult_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.lt $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1953,7 +1909,6 @@
 
 ; CHECK-LABEL: compare_ule_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ule_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1965,7 +1920,6 @@
 
 ; CHECK-LABEL: compare_ule_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_ule_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1976,7 +1930,6 @@
 
 ; CHECK-LABEL: compare_sext_ule_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ule_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T0]]{{$}}
@@ -1989,7 +1942,6 @@
 
 ; CHECK-LABEL: compare_sext_ule_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_ule_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.le $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2001,7 +1953,6 @@
 
 ; CHECK-LABEL: compare_une_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_une_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2012,7 +1963,6 @@
 
 ; CHECK-LABEL: compare_une_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_une_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2023,7 +1973,6 @@
 
 ; CHECK-LABEL: compare_sext_une_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_une_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2035,7 +1984,6 @@
 
 ; CHECK-LABEL: compare_sext_une_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_une_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2047,7 +1995,6 @@
 
 ; CHECK-LABEL: compare_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -2060,7 +2007,6 @@
 
 ; CHECK-LABEL: compare_uno_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_uno_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -2073,7 +2019,6 @@
 
 ; CHECK-LABEL: compare_sext_uno_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uno_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
@@ -2087,7 +2032,6 @@
 
 ; CHECK-LABEL: compare_sext_uno_nnan_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype compare_sext_uno_nnan_v2f64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $0{{$}}
 ; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $1, $1{{$}}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-extended-extract.ll b/llvm/test/CodeGen/WebAssembly/simd-extended-extract.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-extended-extract.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-extended-extract.ll
@@ -16,58 +16,11 @@
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-define void @foo(<4 x i8>* %p) {
 ; CHECK-LABEL: foo:
 ; CHECK:         .functype foo (i32) -> ()
-; CHECK-NEXT:    i32.load8_u 0
-; CHECK-NEXT:    i32x4.splat
-; CHECK-NEXT:    local.tee
-; CHECK-NEXT:    i8x16.extract_lane_s 0
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.splat
-; CHECK-NEXT:    i32.load8_u 1
-; CHECK-NEXT:    i32x4.replace_lane 1
-; CHECK-NEXT:    local.tee
-; CHECK-NEXT:    i8x16.extract_lane_s 4
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.replace_lane 1
-; CHECK-NEXT:    i32.const 2
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i32.load8_u 0
-; CHECK-NEXT:    i32x4.replace_lane 2
-; CHECK-NEXT:    local.tee
-; CHECK-NEXT:    i8x16.extract_lane_s 8
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.replace_lane 2
-; CHECK-NEXT:    i32.const 3
-; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    i32.load8_u 0
-; CHECK-NEXT:    i32x4.replace_lane 3
-; CHECK-NEXT:    i8x16.extract_lane_s 12
-; CHECK-NEXT:    f64.convert_i32_s
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.mul
-; CHECK-NEXT:    f64.const 0x0p0
-; CHECK-NEXT:    f64.add
-; CHECK-NEXT:    f32.demote_f64
-; CHECK-NEXT:    f32x4.replace_lane 3
-; CHECK-NEXT:    v128.store 0
-; CHECK-NEXT:    return
+; Implementation omitted...
+; CHECK:         return
+define void @foo(<4 x i8>* %p) {
   %1 = load <4 x i8>, <4 x i8>* %p
   %2 = sitofp <4 x i8> %1 to <4 x double>
   %3 = fmul <4 x double> zeroinitializer, %2
diff --git a/llvm/test/CodeGen/WebAssembly/simd-offset.ll b/llvm/test/CodeGen/WebAssembly/simd-offset.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-offset.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-offset.ll
@@ -1550,7 +1550,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: load_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1561,7 +1560,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1574,7 +1572,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1586,7 +1583,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1609,7 +1605,6 @@
 
 ; CHECK-LABEL: load_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1623,7 +1618,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1639,7 +1633,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1654,7 +1647,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1683,7 +1675,6 @@
 
 ; CHECK-LABEL: load_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1695,7 +1686,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1709,7 +1699,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1722,7 +1711,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1747,7 +1735,6 @@
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1761,7 +1748,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1777,7 +1763,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1792,7 +1777,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1821,7 +1805,6 @@
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1837,7 +1820,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1855,7 +1837,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1872,7 +1853,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1905,7 +1885,6 @@
 
 ; CHECK-LABEL: load_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1919,7 +1898,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1935,7 +1913,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1950,7 +1927,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -1979,7 +1955,6 @@
 
 ; CHECK-LABEL: load_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
@@ -1992,7 +1967,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
@@ -2007,7 +1981,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
@@ -2021,7 +1994,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
@@ -2048,7 +2020,6 @@
 
 ; CHECK-LABEL: load_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2i64($pop[[L0]]){{$}}
@@ -2061,7 +2032,6 @@
 
 ; CHECK-LABEL: load_splat_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, gv_i64($pop[[L0]]){{$}}
@@ -2076,7 +2046,6 @@
 
 ; CHECK-LABEL: load_sext_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_sext_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_s $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
@@ -2090,7 +2059,6 @@
 
 ; CHECK-LABEL: load_zext_v2i64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_zext_v2i64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: i64x2.load32x2_u $push[[R:[0-9]+]]=, gv_v2i32($pop[[L0]]){{$}}
@@ -2115,7 +2083,6 @@
 
 ; CHECK-LABEL: store_v2i64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2i64(<2 x i64> %v, <2 x i64>* %p) {
@@ -2125,7 +2092,6 @@
 
 ; CHECK-LABEL: store_v2i64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2i64_with_folded_offset(<2 x i64> %v, <2 x i64>* %p) {
@@ -2138,7 +2104,6 @@
 
 ; CHECK-LABEL: store_v2i64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2i64_with_folded_gep_offset(<2 x i64> %v, <2 x i64>* %p) {
@@ -2149,7 +2114,6 @@
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
@@ -2162,7 +2126,6 @@
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
@@ -2175,7 +2138,6 @@
 
 ; CHECK-LABEL: store_v2i64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
@@ -2188,7 +2150,6 @@
 
 ; CHECK-LABEL: store_v2i64_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
@@ -2200,7 +2161,6 @@
 
 ; CHECK-LABEL: store_v2i64_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2i64_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v2i64($pop[[R]]), $0{{$}}
@@ -2519,7 +2479,6 @@
 ; ==============================================================================
 ; CHECK-LABEL: load_v2f64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2530,7 +2489,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64 (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2543,7 +2501,6 @@
 
 ; CHECK-LABEL: load_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2557,7 +2514,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_folded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2573,7 +2529,6 @@
 
 ; CHECK-LABEL: load_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 16($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2585,7 +2540,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_folded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 8($0){{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -2599,7 +2553,6 @@
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -2613,7 +2566,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_gep_negative_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -2629,7 +2581,6 @@
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -2645,7 +2596,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -2663,7 +2613,6 @@
 
 ; CHECK-LABEL: load_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -2677,7 +2626,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_with_unfolded_gep_offset (i32) -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 8{{$}}
 ; SIMD128-NEXT: i32.add $push[[L1:[0-9]+]]=, $0, $pop[[L0]]{{$}}
@@ -2693,7 +2641,6 @@
 
 ; CHECK-LABEL: load_v2f64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
@@ -2706,7 +2653,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_from_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_from_numeric_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 32($pop[[L0]]){{$}}
@@ -2721,7 +2667,6 @@
 
 ; CHECK-LABEL: load_v2f64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_v2f64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.load $push[[R:[0-9]+]]=, gv_v2f64($pop[[L0]]){{$}}
@@ -2734,7 +2679,6 @@
 
 ; CHECK-LABEL: load_splat_v2f64_from_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype load_splat_v2f64_from_global_address () -> (v128){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, gv_f64($pop[[L0]]){{$}}
@@ -2749,7 +2693,6 @@
 
 ; CHECK-LABEL: store_v2f64:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64 (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 0($1), $0{{$}}
 define void @store_v2f64(<2 x double> %v, <2 x double>* %p) {
@@ -2759,7 +2702,6 @@
 
 ; CHECK-LABEL: store_v2f64_with_folded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_folded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2f64_with_folded_offset(<2 x double> %v, <2 x double>* %p) {
@@ -2772,7 +2714,6 @@
 
 ; CHECK-LABEL: store_v2f64_with_folded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_folded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: v128.store 16($1), $0{{$}}
 define void @store_v2f64_with_folded_gep_offset(<2 x double> %v, <2 x double>* %p) {
@@ -2783,7 +2724,6 @@
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_gep_negative_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_unfolded_gep_negative_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
@@ -2796,7 +2736,6 @@
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_unfolded_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, -16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
@@ -2809,7 +2748,6 @@
 
 ; CHECK-LABEL: store_v2f64_with_unfolded_gep_offset:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_with_unfolded_gep_offset (v128, i32) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 16{{$}}
 ; SIMD128-NEXT: i32.add $push[[R:[0-9]+]]=, $1, $pop[[L0]]{{$}}
@@ -2822,7 +2760,6 @@
 
 ; CHECK-LABEL: store_v2f64_to_numeric_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_to_numeric_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[L0:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store 32($pop[[L0]]), $0{{$}}
@@ -2834,7 +2771,6 @@
 
 ; CHECK-LABEL: store_v2f64_to_global_address:
 ; NO-SIMD128-NOT: v128
-; SIMD128-VM-NOT: v128
 ; SIMD128-NEXT: .functype store_v2f64_to_global_address (v128) -> (){{$}}
 ; SIMD128-NEXT: i32.const $push[[R:[0-9]+]]=, 0{{$}}
 ; SIMD128-NEXT: v128.store gv_v2f64($pop[[R]]), $0{{$}}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll b/llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll
--- a/llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-scalar-to-vector.ll
@@ -24,7 +24,7 @@
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: foo:
-; CHECK: i32x4.splat
+; CHECK: i64x2.splat
 define void @foo() {
 entry:
   %a = load <2 x i16>, <2 x i16>* undef, align 1
diff --git a/llvm/test/CodeGen/WebAssembly/simd.ll b/llvm/test/CodeGen/WebAssembly/simd.ll
--- a/llvm/test/CodeGen/WebAssembly/simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd.ll
@@ -85,7 +85,6 @@
 
 ; CHECK-LABEL: extract_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-VM-NOT: i8x16.extract_lane_u
 ; SIMD128-NEXT: .functype extract_v16i8_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 13{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -116,7 +115,6 @@
 
 ; CHECK-LABEL: extract_undef_v16i8_u:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-VM-NOT: i8x16.extract_lane_u
 ; SIMD128-NEXT: .functype extract_undef_v16i8_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i8x16.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -279,6 +277,7 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v8i16:
 ; NO-SIMD128-NOT: i16x8
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v8i16 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 256, 770, 1284, 1798, 2312, 2826, 3340, 3854{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -350,7 +349,6 @@
 
 ; CHECK-LABEL: extract_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-VM-NOT: i16x8.extract_lane_u
 ; SIMD128-NEXT: .functype extract_v8i16_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 5{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -383,7 +381,6 @@
 
 ; CHECK-LABEL: extract_undef_v8i16_u:
 ; NO-SIMD128-NOT: i16x8
-; SIMD128-VM-NOT: i16x8.extract_lane_u
 ; SIMD128-NEXT: .functype extract_undef_v8i16_u (v128) -> (i32){{$}}
 ; SIMD128-NEXT: i16x8.extract_lane_u $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -529,6 +526,7 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v4i32:
 ; NO-SIMD128-NOT: i32x4
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4i32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 50462976, 117835012, 185207048, 252579084{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -680,7 +678,7 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2i64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 506097522914230528, 1084818905618843912{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -690,7 +688,6 @@
 
 ; CHECK-LABEL: splat_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype splat_v2i64 (i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -708,7 +705,6 @@
 
 ; CHECK-LABEL: extract_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype extract_v2i64 (v128) -> (i64){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -739,7 +735,6 @@
 
 ; CHECK-LABEL: extract_zero_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype extract_zero_v2i64 (v128) -> (i64){{$}}
 ; SIMD128-NEXT: i64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -750,7 +745,6 @@
 
 ; CHECK-LABEL: replace_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype replace_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -761,7 +755,6 @@
 
 ; CHECK-LABEL: replace_var_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype replace_var_v2i64 (v128, i32, i64) -> (v128){{$}}
 ; SIMD128-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
@@ -783,7 +776,6 @@
 
 ; CHECK-LABEL: replace_zero_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype replace_zero_v2i64 (v128, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -817,7 +809,6 @@
 
 ; CHECK-LABEL: build_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-VM-NOT: i64x2
 ; SIMD128-NEXT: .functype build_v2i64 (i64, i64) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}
@@ -833,6 +824,7 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v4f32:
 ; NO-SIMD128-NOT: f32x4
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v4f32 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=,
 ; SIMD128-SAME: 0x1.0402p-121, 0x1.0c0a08p-113, 0x1.14121p-105, 0x1.1c1a18p-97{{$}}
@@ -986,6 +978,7 @@
 ; ==============================================================================
 ; CHECK-LABEL: const_v2f64:
 ; NO-SIMD128-NOT: f64x2
+; SIMD128-VM-NOT: v128.const
 ; SIMD128-NEXT: .functype const_v2f64 () -> (v128){{$}}
 ; SIMD128-NEXT: v128.const $push[[R:[0-9]+]]=, 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -995,7 +988,6 @@
 
 ; CHECK-LABEL: splat_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype splat_v2f64 (f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[R:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1013,7 +1005,6 @@
 
 ; CHECK-LABEL: extract_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype extract_v2f64 (v128) -> (f64){{$}}
 ; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1044,7 +1035,6 @@
 
 ; CHECK-LABEL: extract_zero_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype extract_zero_v2f64 (v128) -> (f64){{$}}
 ; SIMD128-NEXT: f64x2.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1055,7 +1045,6 @@
 
 ; CHECK-LABEL: replace_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype replace_v2f64 (v128, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1066,7 +1055,6 @@
 
 ; CHECK-LABEL: replace_var_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype replace_var_v2f64 (v128, i32, f64) -> (v128){{$}}
 ; SIMD128-NEXT: global.get $push[[L0:[0-9]+]]=, __stack_pointer{{$}}
 ; SIMD128-NEXT: i32.const $push[[L1:[0-9]+]]=, 16{{$}}
@@ -1088,7 +1076,6 @@
 
 ; CHECK-LABEL: replace_zero_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype replace_zero_v2f64 (v128, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $0, 0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
@@ -1123,7 +1110,6 @@
 
 ; CHECK-LABEL: build_v2f64:
 ; NO-SIMD128-NOT: f64x2
-; SIMD128-VM-NOT: f64x2
 ; SIMD128-NEXT: .functype build_v2f64 (f64, f64) -> (v128){{$}}
 ; SIMD128-NEXT: f64x2.splat $push[[L0:[0-9]+]]=, $0{{$}}
 ; SIMD128-NEXT: f64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L0]], 1, $1{{$}}