Index: llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
+++ llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
@@ -297,7 +297,7 @@
     // Don't do this if it would create a PHI node with an illegal type from a
     // legal type.
     if (!Src->getType()->isIntegerTy() || !CI.getType()->isIntegerTy() ||
-        shouldChangeType(CI.getType(), Src->getType()))
+        shouldChangeType(CI.getSrcTy(), CI.getType()))
       if (Instruction *NV = foldOpIntoPhi(CI, PN))
         return NV;
   }
Index: llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
+++ llvm/test/CodeGen/AMDGPU/diverge-switch-default.ll
@@ -1,5 +1,7 @@
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -print-after=si-annotate-control-flow %s -o /dev/null 2>&1 | FileCheck %s
 
+target datalayout = "n32"
+
 ; CHECK-LABEL: @switch_unreachable_default
 
 define amdgpu_kernel void @switch_unreachable_default(i32 addrspace(1)* %out, i8 addrspace(1)* %in0, i8 addrspace(1)* %in1) #0 {
Index: llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
+++ llvm/test/CodeGen/AMDGPU/reqd-work-group-size.ll
@@ -1,5 +1,7 @@
 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -amdgpu-lower-kernel-attributes -instcombine %s | FileCheck -enable-var-scope %s
 
+target datalayout = "n32"
+
 ; CHECK-LABEL: @invalid_reqd_work_group_size(
 ; CHECK: load i16,
 define amdgpu_kernel void @invalid_reqd_work_group_size(i16 addrspace(1)* %out) #0 !reqd_work_group_size !1 {
Index: llvm/test/Transforms/InstCombine/cast_phi.ll
===================================================================
--- llvm/test/Transforms/InstCombine/cast_phi.ll
+++ llvm/test/Transforms/InstCombine/cast_phi.ll
@@ -185,14 +185,14 @@
 ; CHECK-NEXT:    br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
 ; CHECK:       t:
 ; CHECK-NEXT:    [[Y:%.*]] = call i32 @get_i32()
-; CHECK-NEXT:    [[PHITMP:%.*]] = zext i32 [[Y]] to i37
 ; CHECK-NEXT:    br label [[EXIT:%.*]]
 ; CHECK:       f:
 ; CHECK-NEXT:    call void @bar()
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[P:%.*]] = phi i37 [ [[PHITMP]], [[T]] ], [ 3, [[F]] ]
-; CHECK-NEXT:    ret i37 [[P]]
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ [[Y]], [[T]] ], [ 3, [[F]] ]
+; CHECK-NEXT:    [[R:%.*]] = zext i32 [[P]] to i37
+; CHECK-NEXT:    ret i37 [[R]]
 ;
 entry:
   %cmp = icmp eq i32 %x, 42
@@ -219,14 +219,14 @@
 ; CHECK-NEXT:    br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
 ; CHECK:       t:
 ; CHECK-NEXT:    [[Y:%.*]] = call i3 @get_i3()
-; CHECK-NEXT:    [[PHITMP:%.*]] = zext i3 [[Y]] to i37
 ; CHECK-NEXT:    br label [[EXIT:%.*]]
 ; CHECK:       f:
 ; CHECK-NEXT:    call void @bar()
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[P:%.*]] = phi i37 [ [[PHITMP]], [[T]] ], [ 3, [[F]] ]
-; CHECK-NEXT:    ret i37 [[P]]
+; CHECK-NEXT:    [[P:%.*]] = phi i3 [ [[Y]], [[T]] ], [ 3, [[F]] ]
+; CHECK-NEXT:    [[R:%.*]] = zext i3 [[P]] to i37
+; CHECK-NEXT:    ret i37 [[R]]
 ;
 entry:
   %cmp = icmp eq i32 %x, 42
@@ -287,14 +287,14 @@
 ; CHECK-NEXT:    br i1 [[CMP]], label [[T:%.*]], label [[F:%.*]]
 ; CHECK:       t:
 ; CHECK-NEXT:    [[Y:%.*]] = call i3 @get_i3()
+; CHECK-NEXT:    [[PHITMP:%.*]] = zext i3 [[Y]] to i64
 ; CHECK-NEXT:    br label [[EXIT:%.*]]
 ; CHECK:       f:
 ; CHECK-NEXT:    call void @bar()
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
-; CHECK-NEXT:    [[P:%.*]] = phi i3 [ [[Y]], [[T]] ], [ 3, [[F]] ]
-; CHECK-NEXT:    [[R:%.*]] = zext i3 [[P]] to i64
-; CHECK-NEXT:    ret i64 [[R]]
+; CHECK-NEXT:    [[P:%.*]] = phi i64 [ [[PHITMP]], [[T]] ], [ 3, [[F]] ]
+; CHECK-NEXT:    ret i64 [[P]]
 ;
 entry:
   %cmp = icmp eq i32 %x, 42
Index: llvm/test/Transforms/InstCombine/icmp-div-constant.ll
===================================================================
--- llvm/test/Transforms/InstCombine/icmp-div-constant.ll
+++ llvm/test/Transforms/InstCombine/icmp-div-constant.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+target datalayout = "n32"
+
 define i1 @is_rem2_neg_i8(i8 %x) {
 ; CHECK-LABEL: @is_rem2_neg_i8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i8 [[X:%.*]], -127
Index: llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
===================================================================
--- llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
+++ llvm/test/Transforms/InstCombine/icmp-mul-zext.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
+target datalayout = "n32"
+
 define i32 @sterix(i32, i8, i64) {
 ; CHECK-LABEL: @sterix(
 ; CHECK-NEXT:  entry: