diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -969,18 +969,50 @@ /// stack arguments from being clobbered. SDValue getStackArgumentTokenFactor(SDValue Chain); + LLVM_ATTRIBUTE_DEPRECATED(SDValue getMemcpy(SDValue Chain, const SDLoc &dl, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, + bool isVol, bool AlwaysInline, + bool isTailCall, + MachinePointerInfo DstPtrInfo, + MachinePointerInfo SrcPtrInfo), + "Use the version that takes Align instead") { + return getMemcpy(Chain, dl, Dst, Src, Size, llvm::Align(Align), isVol, + AlwaysInline, isTailCall, DstPtrInfo, SrcPtrInfo); + } + SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVol, bool AlwaysInline, - bool isTailCall, MachinePointerInfo DstPtrInfo, + SDValue Size, Align Alignment, bool isVol, + bool AlwaysInline, bool isTailCall, + MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo); + LLVM_ATTRIBUTE_DEPRECATED(SDValue getMemmove(SDValue Chain, const SDLoc &dl, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, + bool isVol, bool isTailCall, + MachinePointerInfo DstPtrInfo, + MachinePointerInfo SrcPtrInfo), + "Use the version that takes Align instead") { + return getMemmove(Chain, dl, Dst, Src, Size, llvm::Align(Align), isVol, + isTailCall, DstPtrInfo, SrcPtrInfo); + } SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVol, bool isTailCall, + SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo); + LLVM_ATTRIBUTE_DEPRECATED(SDValue getMemset(SDValue Chain, const SDLoc &dl, + SDValue Dst, SDValue Src, + SDValue Size, unsigned Align, + bool isVol, bool isTailCall, + MachinePointerInfo DstPtrInfo), + "Use the version that takes Align instead") { + return getMemset(Chain, dl, Dst, Src, Size, llvm::Align(Align), isVol, + isTailCall, DstPtrInfo); + } SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, - SDValue Size, unsigned Align, bool isVol, bool isTailCall, + SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo); SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, diff --git a/llvm/include/llvm/CodeGen/TargetCallingConv.h b/llvm/include/llvm/CodeGen/TargetCallingConv.h --- a/llvm/include/llvm/CodeGen/TargetCallingConv.h +++ b/llvm/include/llvm/CodeGen/TargetCallingConv.h @@ -125,13 +125,19 @@ bool isPointer() const { return IsPointer; } void setPointer() { IsPointer = 1; } - unsigned getByValAlign() const { + LLVM_ATTRIBUTE_DEPRECATED(unsigned getByValAlign() const, + "Use getNonZeroByValAlign() instead") { MaybeAlign A = decodeMaybeAlign(ByValAlign); return A ? A->value() : 0; } + Align getNonZeroByValAlign() const { + MaybeAlign A = decodeMaybeAlign(ByValAlign); + assert(A && "ByValAlign must be defined"); + return *A; + } void setByValAlign(Align A) { ByValAlign = encode(A); - assert(getByValAlign() == A.value() && "bitfield overflow"); + assert(getNonZeroByValAlign() == A && "bitfield overflow"); } unsigned getOrigAlign() const { diff --git a/llvm/lib/CodeGen/CallingConvLower.cpp b/llvm/lib/CodeGen/CallingConvLower.cpp --- a/llvm/lib/CodeGen/CallingConvLower.cpp +++ b/llvm/lib/CodeGen/CallingConvLower.cpp @@ -44,7 +44,7 @@ CCValAssign::LocInfo LocInfo, int MinSize, int MinAlignment, ISD::ArgFlagsTy ArgFlags) { Align MinAlign(MinAlignment); - Align Alignment(ArgFlags.getByValAlign()); + Align Alignment = ArgFlags.getNonZeroByValAlign(); unsigned Size = ArgFlags.getByValSize(); if (MinSize > (int)Size) Size = MinSize; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -6264,13 +6264,10 @@ } SDValue SelectionDAG::getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, - SDValue Src, SDValue Size, unsigned Alignment, + SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) { - assert(Alignment && - "The SDAG layer expects explicit alignment and reserves 0"); - // Check to see if we should lower the memcpy to loads and stores first. // For cases within the target-specified limits, this is the best choice. ConstantSDNode *ConstantSize = dyn_cast(Size); @@ -6280,8 +6277,8 @@ return Chain; SDValue Result = getMemcpyLoadsAndStores( - *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), - Align(Alignment), isVol, false, DstPtrInfo, SrcPtrInfo); + *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment, + isVol, false, DstPtrInfo, SrcPtrInfo); if (Result.getNode()) return Result; } @@ -6290,8 +6287,8 @@ // code. If the target chooses to do this, this is the next best. if (TSI) { SDValue Result = TSI->EmitTargetCodeForMemcpy( - *this, dl, Chain, Dst, Src, Size, Alignment, isVol, AlwaysInline, - DstPtrInfo, SrcPtrInfo); + *this, dl, Chain, Dst, Src, Size, Alignment.value(), isVol, + AlwaysInline, DstPtrInfo, SrcPtrInfo); if (Result.getNode()) return Result; } @@ -6300,9 +6297,9 @@ // use a (potentially long) sequence of loads and stores. if (AlwaysInline) { assert(ConstantSize && "AlwaysInline requires a constant size!"); - return getMemcpyLoadsAndStores( - *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), - Align(Alignment), isVol, true, DstPtrInfo, SrcPtrInfo); + return getMemcpyLoadsAndStores(*this, dl, Chain, Dst, Src, + ConstantSize->getZExtValue(), Alignment, + isVol, true, DstPtrInfo, SrcPtrInfo); } checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace()); @@ -6381,13 +6378,10 @@ } SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, - SDValue Src, SDValue Size, unsigned Alignment, + SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) { - assert(Alignment && - "The SDAG layer expects explicit alignment and reserves 0"); - // Check to see if we should lower the memmove to loads and stores first. // For cases within the target-specified limits, this is the best choice. ConstantSDNode *ConstantSize = dyn_cast(Size); @@ -6397,8 +6391,8 @@ return Chain; SDValue Result = getMemmoveLoadsAndStores( - *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), - Align(Alignment), isVol, false, DstPtrInfo, SrcPtrInfo); + *this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment, + isVol, false, DstPtrInfo, SrcPtrInfo); if (Result.getNode()) return Result; } @@ -6406,9 +6400,9 @@ // Then check to see if we should lower the memmove with target-specific // code. If the target chooses to do this, this is the next best. if (TSI) { - SDValue Result = - TSI->EmitTargetCodeForMemmove(*this, dl, Chain, Dst, Src, Size, - Alignment, isVol, DstPtrInfo, SrcPtrInfo); + SDValue Result = TSI->EmitTargetCodeForMemmove( + *this, dl, Chain, Dst, Src, Size, Alignment.value(), isVol, DstPtrInfo, + SrcPtrInfo); if (Result.getNode()) return Result; } @@ -6486,12 +6480,9 @@ } SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, - SDValue Src, SDValue Size, unsigned Alignment, + SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo) { - assert(Alignment && - "The SDAG layer expects explicit alignment and reserves 0"); - // Check to see if we should lower the memset to stores first. // For cases within the target-specified limits, this is the best choice. ConstantSDNode *ConstantSize = dyn_cast(Size); @@ -6501,8 +6492,8 @@ return Chain; SDValue Result = getMemsetStores(*this, dl, Chain, Dst, Src, - ConstantSize->getZExtValue(), - Align(Alignment), isVol, DstPtrInfo); + ConstantSize->getZExtValue(), Alignment, + isVol, DstPtrInfo); if (Result.getNode()) return Result; @@ -6512,7 +6503,7 @@ // code. If the target chooses to do this, this is the next best. if (TSI) { SDValue Result = TSI->EmitTargetCodeForMemset( - *this, dl, Chain, Dst, Src, Size, Alignment, isVol, DstPtrInfo); + *this, dl, Chain, Dst, Src, Size, Alignment.value(), isVol, DstPtrInfo); if (Result.getNode()) return Result; } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -5836,15 +5836,15 @@ SDValue Op2 = getValue(I.getArgOperand(1)); SDValue Op3 = getValue(I.getArgOperand(2)); // @llvm.memcpy defines 0 and 1 to both mean no alignment. - unsigned DstAlign = std::max(MCI.getDestAlignment(), 1); - unsigned SrcAlign = std::max(MCI.getSourceAlignment(), 1); - unsigned Align = MinAlign(DstAlign, SrcAlign); + Align DstAlign = MCI.getDestAlign().valueOrOne(); + Align SrcAlign = MCI.getSourceAlign().valueOrOne(); + Align Alignment = commonAlignment(DstAlign, SrcAlign); bool isVol = MCI.isVolatile(); bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); // FIXME: Support passing different dest/src alignments to the memcpy DAG // node. SDValue Root = isVol ? getRoot() : getMemoryRoot(); - SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Align, isVol, + SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Alignment, isVol, /* AlwaysInline */ false, isTC, MachinePointerInfo(I.getArgOperand(0)), MachinePointerInfo(I.getArgOperand(1))); @@ -5865,10 +5865,10 @@ bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); // FIXME: Support passing different dest/src alignments to the memcpy DAG // node. - SDValue MC = DAG.getMemcpy( - getRoot(), sdl, Dst, Src, Size, Alignment.value(), isVol, - /* AlwaysInline */ true, isTC, MachinePointerInfo(I.getArgOperand(0)), - MachinePointerInfo(I.getArgOperand(1))); + SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Alignment, isVol, + /* AlwaysInline */ true, isTC, + MachinePointerInfo(I.getArgOperand(0)), + MachinePointerInfo(I.getArgOperand(1))); updateDAGForMaybeTailCall(MC); return; } @@ -5878,12 +5878,12 @@ SDValue Op2 = getValue(I.getArgOperand(1)); SDValue Op3 = getValue(I.getArgOperand(2)); // @llvm.memset defines 0 and 1 to both mean no alignment. - unsigned Align = std::max(MSI.getDestAlignment(), 1); + Align Alignment = MSI.getDestAlign().valueOrOne(); bool isVol = MSI.isVolatile(); bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); SDValue Root = isVol ? getRoot() : getMemoryRoot(); - SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Align, isVol, - isTC, MachinePointerInfo(I.getArgOperand(0))); + SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Alignment, isVol, isTC, + MachinePointerInfo(I.getArgOperand(0))); updateDAGForMaybeTailCall(MS); return; } @@ -5893,15 +5893,15 @@ SDValue Op2 = getValue(I.getArgOperand(1)); SDValue Op3 = getValue(I.getArgOperand(2)); // @llvm.memmove defines 0 and 1 to both mean no alignment. - unsigned DstAlign = std::max(MMI.getDestAlignment(), 1); - unsigned SrcAlign = std::max(MMI.getSourceAlignment(), 1); - unsigned Align = MinAlign(DstAlign, SrcAlign); + Align DstAlign = MMI.getDestAlign().valueOrOne(); + Align SrcAlign = MMI.getSourceAlign().valueOrOne(); + Align Alignment = commonAlignment(DstAlign, SrcAlign); bool isVol = MMI.isVolatile(); bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); // FIXME: Support passing different dest/src alignments to the memmove DAG // node. SDValue Root = isVol ? getRoot() : getMemoryRoot(); - SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Align, isVol, + SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Alignment, isVol, isTC, MachinePointerInfo(I.getArgOperand(0)), MachinePointerInfo(I.getArgOperand(1))); updateDAGForMaybeTailCall(MM); @@ -7473,9 +7473,8 @@ unsigned DstAlign = DAG.InferPtrAlignment(Dst); unsigned SrcAlign = DAG.InferPtrAlignment(Src); - unsigned Align = std::min(DstAlign, SrcAlign); - if (Align == 0) // Alignment of one or both could not be inferred. - Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved. + // DAG::getMemcpy needs Alignment to be defined. + Align Alignment = assumeAligned(std::min(DstAlign, SrcAlign)); bool isVol = false; SDLoc sdl = getCurSDLoc(); @@ -7484,8 +7483,8 @@ // because the return pointer needs to be adjusted by the size of // the copied memory. SDValue Root = isVol ? getRoot() : getMemoryRoot(); - SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Align, isVol, - false, /*isTailCall=*/false, + SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Alignment, isVol, false, + /*isTailCall=*/false, MachinePointerInfo(I.getArgOperand(0)), MachinePointerInfo(I.getArgOperand(1))); assert(MC.getNode() != nullptr && diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4226,10 +4226,10 @@ SDValue SizeNode = DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64); SDValue Cpy = DAG.getMemcpy( - Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(), + Chain, DL, DstAddr, Arg, SizeNode, + Outs[i].Flags.getNonZeroByValAlign(), /*isVol = */ false, /*AlwaysInline = */ false, - /*isTailCall = */ false, - DstInfo, MachinePointerInfo()); + /*isTailCall = */ false, DstInfo, MachinePointerInfo()); MemOpChains.push_back(Cpy); } else { @@ -5762,9 +5762,9 @@ const Value *SrcSV = cast(Op.getOperand(4))->getValue(); return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1), Op.getOperand(2), - DAG.getConstant(VaListSize, DL, MVT::i32), PtrSize, - false, false, false, MachinePointerInfo(DestSV), - MachinePointerInfo(SrcSV)); + DAG.getConstant(VaListSize, DL, MVT::i32), + Align(PtrSize), false, false, false, + MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV)); } SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2835,7 +2835,7 @@ // FIXME: We can have better than the minimum byval required alignment. Alignment = Flags.isByVal() - ? MaybeAlign(Flags.getByValAlign()) + ? Flags.getNonZeroByValAlign() : commonAlignment(Subtarget->getStackAlignment(), Offset); Offset = Offset + FPDiff; @@ -2862,11 +2862,12 @@ if (Outs[i].Flags.isByVal()) { SDValue SizeNode = DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32); - SDValue Cpy = DAG.getMemcpy( - Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(), - /*isVol = */ false, /*AlwaysInline = */ true, - /*isTailCall = */ false, DstInfo, - MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS)); + SDValue Cpy = + DAG.getMemcpy(Chain, DL, DstAddr, Arg, SizeNode, + Outs[i].Flags.getNonZeroByValAlign(), + /*isVol = */ false, /*AlwaysInline = */ true, + /*isTailCall = */ false, DstInfo, + MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS)); MemOpChains.push_back(Cpy); } else { diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp --- a/llvm/lib/Target/ARC/ARCISelLowering.cpp +++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp @@ -563,14 +563,16 @@ for (const auto &ArgDI : ArgData) { if (ArgDI.Flags.isByVal() && ArgDI.Flags.getByValSize()) { unsigned Size = ArgDI.Flags.getByValSize(); - unsigned Align = std::max(StackSlotSize, ArgDI.Flags.getByValAlign()); + Align Alignment = + std::max(Align(StackSlotSize), ArgDI.Flags.getNonZeroByValAlign()); // Create a new object on the stack and copy the pointee into it. - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); InVals.push_back(FIN); MemOps.push_back(DAG.getMemcpy( - Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32), Align, - false, false, false, MachinePointerInfo(), MachinePointerInfo())); + Chain, dl, FIN, ArgDI.SDV, DAG.getConstant(Size, dl, MVT::i32), + Alignment, false, false, false, MachinePointerInfo(), + MachinePointerInfo())); } else { InVals.push_back(ArgDI.SDV); } diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2274,8 +2274,8 @@ SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset); SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl, MVT::i32); - SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl, - MVT::i32); + SDValue AlignNode = + DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32); SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode}; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -167,10 +167,10 @@ SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); - return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - /*isVolatile=*/false, /*AlwaysInline=*/false, - /*isTailCall=*/false, - MachinePointerInfo(), MachinePointerInfo()); + return DAG.getMemcpy( + Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); } bool @@ -993,10 +993,9 @@ // Size of the va_list is 12 bytes as it has 3 pointers. Therefore, // we need to memcopy 12 bytes from va_list to another similar list. return DAG.getMemcpy(Chain, DL, DestPtr, SrcPtr, - DAG.getIntPtrConstant(12, DL), 4, /*isVolatile*/false, - false, false, + DAG.getIntPtrConstant(12, DL), Align(4), + /*isVolatile*/ false, false, false, MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV)); - } SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -633,13 +633,13 @@ SDValue Arg = OutVals[I]; unsigned Size = Flags.getByValSize(); - unsigned Align = Flags.getByValAlign(); + Align Alignment = Flags.getNonZeroByValAlign(); - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue SizeNode = DAG.getConstant(Size, DL, MVT::i32); - Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align, + Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, /*IsVolatile=*/false, /*AlwaysInline=*/false, /*isTailCall=*/false, MachinePointerInfo(), diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp --- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -863,13 +863,11 @@ if (Flags.isByVal()) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); - MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, - Flags.getByValAlign(), - /*isVolatile*/false, - /*AlwaysInline=*/true, - /*isTailCall=*/false, - MachinePointerInfo(), - MachinePointerInfo()); + MemOp = DAG.getMemcpy( + Chain, dl, PtrOff, Arg, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile*/ false, + /*AlwaysInline=*/true, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); } else { MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()); } diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -4361,7 +4361,8 @@ unsigned ByValSizeInBytes = Flags.getByValSize(); unsigned OffsetInBytes = 0; // From beginning of struct unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); - unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); + Align Alignment = + std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes)); EVT PtrTy = getPointerTy(DAG.getDataLayout()), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); unsigned NumRegs = LastReg - FirstReg; @@ -4376,7 +4377,7 @@ SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, DAG.getConstant(OffsetInBytes, DL, PtrTy)); SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, - MachinePointerInfo(), Alignment); + MachinePointerInfo(), Alignment.value()); MemOpChains.push_back(LoadVal.getValue(1)); unsigned ArgReg = ArgRegs[FirstReg + I]; RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); @@ -4403,7 +4404,7 @@ PtrTy)); SDValue LoadVal = DAG.getExtLoad( ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), - MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); + MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment.value()); MemOpChains.push_back(LoadVal.getValue(1)); // Shift the loaded value. @@ -4424,7 +4425,7 @@ OffsetInBytes += LoadSizeInBytes; TotalBytesLoaded += LoadSizeInBytes; - Alignment = std::min(Alignment, LoadSizeInBytes); + Alignment = std::min(Alignment, Align(LoadSizeInBytes)); } unsigned ArgReg = ArgRegs[FirstReg + I]; @@ -4439,11 +4440,10 @@ DAG.getConstant(OffsetInBytes, DL, PtrTy)); SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); - Chain = DAG.getMemcpy(Chain, DL, Dst, Src, - DAG.getConstant(MemCpySize, DL, PtrTy), - Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, - /*isTailCall=*/false, - MachinePointerInfo(), MachinePointerInfo()); + Chain = DAG.getMemcpy( + Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), + Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); MemOpChains.push_back(Chain); } diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -1354,9 +1354,9 @@ assert(PTy && "Param with byval attribute should be a pointer type"); Type *ETy = PTy->getElementType(); - unsigned align = Outs[OIdx].Flags.getByValAlign(); + Align align = Outs[OIdx].Flags.getNonZeroByValAlign(); unsigned sz = DL.getTypeAllocSize(ETy); - O << ".param .align " << align << " .b8 "; + O << ".param .align " << align.value() << " .b8 "; O << "_"; O << "[" << sz << "]"; } @@ -1581,7 +1581,7 @@ // declare .param .align .b8 .param[]; unsigned sz = Outs[OIdx].Flags.getByValSize(); SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); - unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign(); + Align ArgAlign = Outs[OIdx].Flags.getNonZeroByValAlign(); // The ByValAlign in the Outs[OIdx].Flags is alway set at this point, // so we don't need to worry about natural alignment or not. // See TargetLowering::LowerCallTo(). @@ -1589,18 +1589,19 @@ // Enforce minumum alignment of 4 to work around ptxas miscompile // for sm_50+. See corresponding alignment adjustment in // emitFunctionParamList() for details. - if (ArgAlign < 4) - ArgAlign = 4; - SDValue DeclareParamOps[] = {Chain, DAG.getConstant(ArgAlign, dl, MVT::i32), - DAG.getConstant(paramCount, dl, MVT::i32), - DAG.getConstant(sz, dl, MVT::i32), InFlag}; + if (ArgAlign < Align(4)) + ArgAlign = Align(4); + SDValue DeclareParamOps[] = { + Chain, DAG.getConstant(ArgAlign.value(), dl, MVT::i32), + DAG.getConstant(paramCount, dl, MVT::i32), + DAG.getConstant(sz, dl, MVT::i32), InFlag}; Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs, DeclareParamOps); InFlag = Chain.getValue(1); for (unsigned j = 0, je = VTs.size(); j != je; ++j) { EVT elemtype = VTs[j]; int curOffset = Offsets[j]; - unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset); + unsigned PartAlign = GreatestCommonDivisor64(ArgAlign.value(), curOffset); auto PtrVT = getPointerTy(DL); SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx], DAG.getConstant(curOffset, dl, PtrVT)); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3142,10 +3142,10 @@ // We have to copy the entire va_list struct: // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte - return DAG.getMemcpy(Op.getOperand(0), Op, - Op.getOperand(1), Op.getOperand(2), - DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true, - false, MachinePointerInfo(), MachinePointerInfo()); + return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2), + DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8), + false, true, false, MachinePointerInfo(), + MachinePointerInfo()); } SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, @@ -3308,31 +3308,31 @@ /// CalculateStackSlotAlignment - Calculates the alignment of this argument /// on the stack. -static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, - ISD::ArgFlagsTy Flags, - unsigned PtrByteSize) { - unsigned Align = PtrByteSize; +static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, + ISD::ArgFlagsTy Flags, + unsigned PtrByteSize) { + Align Alignment(PtrByteSize); // Altivec parameters are padded to a 16 byte boundary. if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || ArgVT == MVT::v1i128 || ArgVT == MVT::f128) - Align = 16; + Alignment = Align(16); // QPX vector types stored in double-precision are padded to a 32 byte // boundary. else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1) - Align = 32; + Alignment = Align(32); // ByVal parameters are aligned as requested. if (Flags.isByVal()) { - unsigned BVAlign = Flags.getByValAlign(); + auto BVAlign = Flags.getNonZeroByValAlign(); if (BVAlign > PtrByteSize) { - if (BVAlign % PtrByteSize != 0) - llvm_unreachable( + if (BVAlign.value() % PtrByteSize != 0) + llvm_unreachable( "ByVal alignment is not a multiple of the pointer size"); - Align = BVAlign; + Alignment = BVAlign; } } @@ -3342,12 +3342,12 @@ // needs to be aligned to the size of the full type. (Except for // ppcf128, which is only aligned as its f64 components.) if (Flags.isSplit() && OrigVT != MVT::ppcf128) - Align = OrigVT.getStoreSize(); + Alignment = Align(OrigVT.getStoreSize()); else - Align = ArgVT.getStoreSize(); + Alignment = Align(ArgVT.getStoreSize()); } - return Align; + return Alignment; } /// CalculateStackSlotUsed - Return whether this argument will use its @@ -3365,9 +3365,9 @@ bool UseMemory = false; // Respect alignment of argument on the stack. - unsigned Align = - CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); - ArgOffset = ((ArgOffset + Align - 1) / Align) * Align; + Align Alignment = + CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); + ArgOffset = alignTo(ArgOffset, Alignment); // If there's no space left in the argument save area, we must // use memory (this check also catches zero-sized arguments). if (ArgOffset >= LinkageSize + ParamAreaSize) @@ -3789,11 +3789,13 @@ // We re-align the argument offset for each argument, except when using the // fast calling convention, when we need to make sure we do that only when // we'll actually use a stack slot. - unsigned CurArgOffset, Align; + unsigned CurArgOffset; + Align Alignment; auto ComputeArgOffset = [&]() { /* Respect alignment of argument on the stack. */ - Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); - ArgOffset = ((ArgOffset + Align - 1) / Align) * Align; + Alignment = + CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize); + ArgOffset = alignTo(ArgOffset, Alignment); CurArgOffset = ArgOffset; }; @@ -3841,7 +3843,7 @@ ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize) FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true); else - FI = MFI.CreateStackObject(ArgSize, Align, false); + FI = MFI.CreateStackObject(ArgSize, Alignment, false); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); // Handle aggregates smaller than 8 bytes. @@ -4874,9 +4876,9 @@ SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); - return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - false, false, false, MachinePointerInfo(), - MachinePointerInfo()); + return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, + Flags.getNonZeroByValAlign(), false, false, false, + MachinePointerInfo(), MachinePointerInfo()); } /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of @@ -5907,9 +5909,9 @@ } /* Respect alignment of argument on the stack. */ - unsigned Align = - CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); - NumBytes = ((NumBytes + Align - 1) / Align) * Align; + auto Alignement = + CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); + NumBytes = alignTo(NumBytes, Alignement); NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); if (Flags.isInConsecutiveRegsLast()) @@ -5988,9 +5990,9 @@ // we'll actually use a stack slot. auto ComputePtrOff = [&]() { /* Respect alignment of argument on the stack. */ - unsigned Align = - CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); - ArgOffset = ((ArgOffset + Align - 1) / Align) * Align; + auto Alignment = + CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize); + ArgOffset = alignTo(ArgOffset, Alignment); PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType()); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2140,17 +2140,17 @@ SDValue Arg = OutVals[i]; unsigned Size = Flags.getByValSize(); - unsigned Align = Flags.getByValAlign(); + Align Alignment = Flags.getNonZeroByValAlign(); - int FI = MF.getFrameInfo().CreateStackObject(Size, Align, /*isSS=*/false); + int FI = + MF.getFrameInfo().CreateStackObject(Size, Alignment, /*isSS=*/false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue SizeNode = DAG.getConstant(Size, DL, XLenVT); - Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align, + Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Alignment, /*IsVolatile=*/false, - /*AlwaysInline=*/false, - IsTailCall, MachinePointerInfo(), - MachinePointerInfo()); + /*AlwaysInline=*/false, IsTailCall, + MachinePointerInfo(), MachinePointerInfo()); ByValArgs.push_back(FIPtr); } diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -753,14 +753,14 @@ SDValue Arg = OutVals[i]; unsigned Size = Flags.getByValSize(); - unsigned Align = Flags.getByValAlign(); + Align Alignment = Flags.getNonZeroByValAlign(); if (Size > 0U) { - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32); - Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, + Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment, false, // isVolatile, (Size <= 32), // AlwaysInline if size <= 32, false, // isTailCall diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -3355,9 +3355,9 @@ SDLoc DL(Op); return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL), - /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false, - /*isTailCall*/false, - MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); + Align(8), /*isVolatile*/ false, /*AlwaysInline*/ false, + /*isTailCall*/ false, MachinePointerInfo(DstSV), + MachinePointerInfo(SrcSV)); } SDValue SystemZTargetLowering:: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -754,13 +754,13 @@ if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) { auto &MFI = MF.getFrameInfo(); int FI = MFI.CreateStackObject(Out.Flags.getByValSize(), - Out.Flags.getByValAlign(), + Out.Flags.getNonZeroByValAlign(), /*isSS=*/false); SDValue SizeNode = DAG.getConstant(Out.Flags.getByValSize(), DL, MVT::i32); SDValue FINode = DAG.getFrameIndex(FI, getPointerTy(Layout)); Chain = DAG.getMemcpy( - Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getByValAlign(), + Chain, DL, FINode, OutVal, SizeNode, Out.Flags.getNonZeroByValAlign(), /*isVolatile*/ false, /*AlwaysInline=*/false, /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo()); OutVal = FINode; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3131,10 +3131,10 @@ SelectionDAG &DAG, const SDLoc &dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); - return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - /*isVolatile*/false, /*AlwaysInline=*/true, - /*isTailCall*/false, - MachinePointerInfo(), MachinePointerInfo()); + return DAG.getMemcpy( + Chain, dl, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile*/ false, /*AlwaysInline=*/true, + /*isTailCall*/ false, MachinePointerInfo(), MachinePointerInfo()); } /// Return true if the calling convention is one that we can guarantee TCO for. @@ -3966,8 +3966,8 @@ // the caller from seeing any modifications the callee may make // as guaranteed by the `byval` attribute. int FrameIdx = MF.getFrameInfo().CreateStackObject( - Flags.getByValSize(), std::max(16, (int)Flags.getByValAlign()), - false); + Flags.getByValSize(), + std::max(Align(16), Flags.getNonZeroByValAlign()), false); SDValue StackSlot = DAG.getFrameIndex(FrameIdx, getPointerTy(DAG.getDataLayout())); Chain = @@ -23310,9 +23310,8 @@ const Value *SrcSV = cast(Op.getOperand(4))->getValue(); SDLoc DL(Op); - return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, - DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false, - false, false, + return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(24, DL), + Align(8), /*isVolatile*/ false, false, false, MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); } diff --git a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp --- a/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp +++ b/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp @@ -172,9 +172,8 @@ Chain = DAG.getMemset(Chain, dl, DAG.getNode(ISD::ADD, dl, AddrVT, Dst, DAG.getConstant(Offset, dl, AddrVT)), - Val, - DAG.getConstant(BytesLeft, dl, SizeVT), - Align, isVolatile, false, + Val, DAG.getConstant(BytesLeft, dl, SizeVT), + llvm::Align(Align), isVolatile, false, DstPtrInfo.getWithOffset(Offset)); } @@ -283,7 +282,7 @@ Chain, dl, DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)), - DAG.getConstant(BytesLeft, dl, SizeVT), Align, isVolatile, + DAG.getConstant(BytesLeft, dl, SizeVT), llvm::Align(Align), isVolatile, /*AlwaysInline*/ true, /*isTailCall*/ false, DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset))); return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results); diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -1391,16 +1391,16 @@ ArgDI != ArgDE; ++ArgDI) { if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) { unsigned Size = ArgDI->Flags.getByValSize(); - unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign()); + Align Alignment = + std::max(Align(StackSlotSize), ArgDI->Flags.getNonZeroByValAlign()); // Create a new object on the stack and copy the pointee into it. - int FI = MFI.CreateStackObject(Size, Align, false); + int FI = MFI.CreateStackObject(Size, Alignment, false); SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); InVals.push_back(FIN); - MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, - DAG.getConstant(Size, dl, MVT::i32), - Align, false, false, false, - MachinePointerInfo(), - MachinePointerInfo())); + MemOps.push_back(DAG.getMemcpy( + Chain, dl, FIN, ArgDI->SDV, DAG.getConstant(Size, dl, MVT::i32), + Alignment, false, false, false, MachinePointerInfo(), + MachinePointerInfo())); } else { InVals.push_back(ArgDI->SDV); } @@ -1800,11 +1800,10 @@ !LD->isVolatile() && !LD->isIndexed() && Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { bool isTail = isInTailCallPosition(DAG, ST, Chain); - return DAG.getMemmove(Chain, dl, ST->getBasePtr(), - LD->getBasePtr(), - DAG.getConstant(StoreBits/8, dl, MVT::i32), - Alignment, false, isTail, ST->getPointerInfo(), - LD->getPointerInfo()); + return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), + DAG.getConstant(StoreBits / 8, dl, MVT::i32), + Align(Alignment), false, isTail, + ST->getPointerInfo(), LD->getPointerInfo()); } } break;