Index: llvm/lib/CodeGen/MachineLICM.cpp
===================================================================
--- llvm/lib/CodeGen/MachineLICM.cpp
+++ llvm/lib/CodeGen/MachineLICM.cpp
@@ -1367,6 +1367,11 @@
   UpdateRegPressure(NewMIs[1]);
 
   // Otherwise we successfully unfolded a load that we can hoist.
+
+  // Update the call site info.
+  if (TII->isCandidateForCallSiteEntry(*MI))
+    MF.eraseCallSiteInfo(MI);
+
   MI->eraseFromParent();
   return NewMIs[0];
 }
Index: llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
+++ llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
@@ -105,6 +105,10 @@
                                  TII->get(TargetOpcode::COPY), AArch64::X0)
                              .addReg(TLSBaseAddrReg);
 
+    // Update the call site info.
+    if (TII->isCandidateForCallSiteEntry(I))
+      I.getMF()->eraseCallSiteInfo(&I);
+
     // Erase the TLS_base_addr instruction.
     I.eraseFromParent();
 
Index: llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
===================================================================
--- llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
+++ llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
@@ -920,6 +920,11 @@
         // Now stitch the new instructions into place and erase the old one.
         for (auto *NewMI : NewMIs)
           MBB.insert(MI.getIterator(), NewMI);
+
+        // Update the call site info.
+        if (TII->isCandidateForCallSiteEntry(MI))
+          MF.eraseCallSiteInfo(&MI);
+
         MI.eraseFromParent();
         LLVM_DEBUG({
           dbgs() << "Unfolded load successfully into:\n";
Index: llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
+++ llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
@@ -1,3 +1,7 @@
+; Verify the call site info. If the call site info is not
+; in the valid state, an assert should be triggered.
+; RUN: llc < %s -debug-entry-values -mtriple=arm64-none-linux-gnu -stop-after=machineverifier -relocation-model=pic -aarch64-elf-ldtls-generation=1 < %s
+
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s
 ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOLD %s
Index: llvm/test/CodeGen/X86/hoist-invariant-load.ll
===================================================================
--- llvm/test/CodeGen/X86/hoist-invariant-load.ll
+++ llvm/test/CodeGen/X86/hoist-invariant-load.ll
@@ -1,4 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; Verify the call site info. If the call site info is not
+; in the valid state, an assert should be triggered.
+; RUN: llc < %s -debug-entry-values -stop-after=machineverifier
+
 ; REQUIRES: asserts
 ; RUN: llc -mcpu=haswell < %s -O2 2>&1 | FileCheck %s
 ; For test:
Index: llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
===================================================================
--- llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
+++ llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
@@ -1,4 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; Verify the call site info. If the call site info is not
+; in the valid state, an assert should be triggered.
+; RUN: llc < %s -debug-entry-values -mtriple=x86_64-unknown-linux-gnu -x86-speculative-load-hardening -stop-after=machineverifier
+
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -x86-speculative-load-hardening -data-sections | FileCheck %s --check-prefix=X64
 ; FIXME: Fix machine verifier issues and remove -verify-machineinstrs=0. PR39451.
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -x86-speculative-load-hardening -relocation-model pic -data-sections -verify-machineinstrs=0 | FileCheck %s --check-prefix=X64-PIC