Index: llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
===================================================================
--- llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -286,7 +286,12 @@
     default:
       OpId = 0;
       break;
+    case ARM::MVE_WLSTP_8:
+    case ARM::MVE_WLSTP_16:
+    case ARM::MVE_WLSTP_32:
+    case ARM::MVE_WLSTP_64:
     case ARM::t2WLS:
+    case ARM::MVE_LETP:
     case ARM::t2LEUpdate:
       OpId = 2;
       break;
Index: llvm/test/MC/Disassembler/ARM/mve-lol.txt
===================================================================
--- /dev/null
+++ llvm/test/MC/Disassembler/ARM/mve-lol.txt
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -assemble -triple=thumbv8.1m.main -mattr=+mve -filetype=obj %s -o - 2>&1 | \
+# RUN:   llvm-objdump -d -r -triple=thumbv8.1m.main -mattr=+mve - | FileCheck %s
+
+# Test to check that we can evaluate branches and their targets, i.e.
+# checking that we see branch targets annotations like <$t.0+0xc> in the
+# disassembly.
+
+# CHECK:  wls lr, r3, #8 <$t.0+0xc>
+# CHECK:  vmov  q0, q1
+# CHECK:  le  lr, #-8 <$t.0+0x4>
+
+          wls lr, r3, #8
+          vmov  q0, q1
+          le  lr, #-8
+
+
+# CHECK:  wlstp.8 lr, r3, #8 <$t.0+0x18>
+# CHECK:  vmov  q0, q1
+# CHECK:  letp  lr, #-8 <$t.0+0x10>
+
+          wlstp.8  lr, r3, #8
+          vmov  q0, q1
+          letp  lr, #-8
+
+
+# CHECK:  wlstp.16  lr, r3, #8 <$t.0+0x24>
+# CHECK:  vmov  q0, q1
+# CHECK:  letp  lr, #-8 <$t.0+0x1c>
+
+          wlstp.16  lr, r3, #8
+          vmov  q0, q1
+          letp  lr, #-8
+
+
+# CHECK:  wlstp.32  lr, r3, #8 <$t.0+0x30>
+# CHECK:  vmov  q0, q1
+# CHECK:  letp  lr, #-8 <$t.0+0x28>
+
+          wlstp.32  lr, r3, #8
+          vmov  q0, q1
+          letp  lr, #-8
+
+
+# CHECK:  wlstp.64  lr, r3, #8 <$t.0+0x3c>
+# CHECK:  vmov  q0, q1
+# CHECK:  letp  lr, #-8 <$t.0+0x34>
+
+          wlstp.64  lr, r3, #8
+          vmov  q0, q1
+          letp  lr, #-8