Index: llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
===================================================================
--- llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
+++ llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
@@ -1155,8 +1155,8 @@
 
   /// Return true if MI is either legal or has been legalized and false
   /// if not legal.
-  virtual bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
-                                 MachineIRBuilder &MIRBuilder) const;
+  virtual bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+                                 GISelChangeObserver &Observer) const;
 
   /// Return the opcode (SEXT/ZEXT/ANYEXT) that should be performed while
   /// widening a constant of type SmallTy which targets can override.
Index: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -114,8 +114,8 @@
 
   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
-    return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
-                                                     : UnableToLegalize;
+    return LI.legalizeIntrinsic(MI, MIRBuilder, Observer) ? Legalized
+                                                          : UnableToLegalize;
   auto Step = LI.getAction(MI, MRI);
   switch (Step.Action) {
   case Legal:
Index: llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
===================================================================
--- llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
+++ llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
@@ -682,8 +682,8 @@
 }
 
 bool LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
-                                      MachineRegisterInfo &MRI,
-                                      MachineIRBuilder &MIRBuilder) const {
+                                      MachineIRBuilder &MIRBuilder,
+                                      GISelChangeObserver &Observer) const {
   return true;
 }
 
Index: llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
===================================================================
--- llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
+++ llvm/lib/Target/AArch64/AArch64LegalizerInfo.h
@@ -31,8 +31,8 @@
                       MachineIRBuilder &MIRBuilder,
                       GISelChangeObserver &Observer) const override;
 
-  bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         MachineIRBuilder &MIRBuilder) const override;
+  bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+                         GISelChangeObserver &Observer) const override;
 
 private:
   bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
Index: llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
@@ -640,13 +640,13 @@
 }
 
 bool AArch64LegalizerInfo::legalizeIntrinsic(
-    MachineInstr &MI, MachineRegisterInfo &MRI,
-    MachineIRBuilder &MIRBuilder) const {
+    MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+    GISelChangeObserver &Observer) const {
   switch (MI.getIntrinsicID()) {
   case Intrinsic::memcpy:
   case Intrinsic::memset:
   case Intrinsic::memmove:
-    if (createMemLibcall(MIRBuilder, MRI, MI) ==
+    if (createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI) ==
         LegalizerHelper::UnableToLegalize)
       return false;
     MI.eraseFromParent();
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -133,9 +133,8 @@
   bool legalizeAtomicIncDec(MachineInstr &MI,  MachineIRBuilder &B,
                             bool IsInc) const;
 
-  bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         MachineIRBuilder &B) const override;
-
+  bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &B,
+                         GISelChangeObserver &Observer) const override;
 };
 } // End llvm namespace.
 #endif
Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -3089,10 +3089,10 @@
   return true;
 }
 
-// FIXME: Needs observer like custom
-bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
-                                            MachineRegisterInfo &MRI,
-                                            MachineIRBuilder &B) const {
+bool AMDGPULegalizerInfo::legalizeIntrinsic(
+    MachineInstr &MI, MachineIRBuilder &B,
+    GISelChangeObserver &Observer) const {
+  MachineRegisterInfo &MRI = *B.getMRI();
   // Replace the use G_BRCOND with the exec manipulate and branch pseudos.
   auto IntrID = MI.getIntrinsicID();
   switch (IntrID) {
Index: llvm/lib/Target/Mips/MipsLegalizerInfo.h
===================================================================
--- llvm/lib/Target/Mips/MipsLegalizerInfo.h
+++ llvm/lib/Target/Mips/MipsLegalizerInfo.h
@@ -29,8 +29,8 @@
                       MachineIRBuilder &MIRBuilder,
                       GISelChangeObserver &Observer) const override;
 
-  bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         MachineIRBuilder &MIRBuilder) const override;
+  bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+                         GISelChangeObserver &Observer) const override;
 };
 } // end namespace llvm
 #endif
Index: llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -369,8 +369,9 @@
 }
 
 bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
-                                          MachineRegisterInfo &MRI,
-                                          MachineIRBuilder &MIRBuilder) const {
+                                          MachineIRBuilder &MIRBuilder,
+                                          GISelChangeObserver &Observer) const {
+  MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
   const MipsSubtarget &ST =
       static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget());
   const MipsInstrInfo &TII = *ST.getInstrInfo();
Index: llvm/lib/Target/X86/X86LegalizerInfo.h
===================================================================
--- llvm/lib/Target/X86/X86LegalizerInfo.h
+++ llvm/lib/Target/X86/X86LegalizerInfo.h
@@ -32,8 +32,8 @@
 public:
   X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM);
 
-  bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
-                         MachineIRBuilder &MIRBuilder) const override;
+  bool legalizeIntrinsic(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
+                         GISelChangeObserver &Observer) const override;
 
 private:
   void setLegalizerInfo32bit();
Index: llvm/lib/Target/X86/X86LegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -86,13 +86,13 @@
 }
 
 bool X86LegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
-                                         MachineRegisterInfo &MRI,
-                                         MachineIRBuilder &MIRBuilder) const {
+                                         MachineIRBuilder &MIRBuilder,
+                                         GISelChangeObserver &Observer) const {
   switch (MI.getIntrinsicID()) {
   case Intrinsic::memcpy:
   case Intrinsic::memset:
   case Intrinsic::memmove:
-    if (createMemLibcall(MIRBuilder, MRI, MI) ==
+    if (createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI) ==
         LegalizerHelper::UnableToLegalize)
       return false;
     MI.eraseFromParent();