Index: llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h =================================================================== --- llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h +++ llvm/lib/CodeGen/AsmPrinter/DwarfExpression.h @@ -107,21 +107,29 @@ /// Holds information about all subregisters comprising a register location. struct Register { int DwarfRegNo; - unsigned SubRegSize; - const char *Comment; + uint16_t SubRegisterSizeInBits; + uint16_t SubRegisterOffsetInBits; + enum : char { Full, SuperReg, SubReg } Kind; /// Create a full register, no extra DW_OP_piece operators necessary. - static Register createRegister(int RegNo, const char *Comment) { - return {RegNo, 0, Comment}; + static Register create(int RegNo) { + return {RegNo, 0, 0, Full}; + } + + /// Stencil a subregister out of a superregister. + static Register createSuperReg(int RegNo, uint16_t SizeInBits, + uint16_t OffsetInBits) { + return {RegNo, SizeInBits, OffsetInBits, SuperReg}; } /// Create a subregister that needs a DW_OP_piece operator with SizeInBits. - static Register createSubRegister(int RegNo, unsigned SizeInBits, - const char *Comment) { - return {RegNo, SizeInBits, Comment}; + static Register createSubReg(int RegNo, uint16_t SizeInBits, + uint16_t OffsetInBits) { + return {RegNo, SizeInBits, OffsetInBits, SubReg}; } - bool isSubRegister() const { return SubRegSize; } + /// Return the assembler comment for this register. + const char *getComment() const; }; /// Whether we are currently emitting an entry value operation. @@ -136,8 +144,8 @@ uint64_t OffsetInBits = 0; /// Sometimes we need to add a DW_OP_bit_piece to describe a subregister. - unsigned SubRegisterSizeInBits : 16; - unsigned SubRegisterOffsetInBits : 16; + uint16_t SubRegisterSizeInBits = 0; + uint16_t SubRegisterOffsetInBits = 0; /// The kind of location description being produced. enum { Unknown = 0, Register, Memory, Implicit }; @@ -178,16 +186,12 @@ protected: /// Push a DW_OP_piece / DW_OP_bit_piece for emitting later, if one is needed - /// to represent a subregister. - void setSubRegisterPiece(unsigned SizeInBits, unsigned OffsetInBits) { - assert(SizeInBits < 65536 && OffsetInBits < 65536); + /// to represent a register as a piece of a superregister. + void setSuperRegisterPiece(uint16_t SizeInBits, uint16_t OffsetInBits) { SubRegisterSizeInBits = SizeInBits; SubRegisterOffsetInBits = OffsetInBits; } - /// Add masking operations to stencil out a subregister. - void maskSubRegister(); - /// Output a dwarf operand and an optional assembler comment. virtual void emitOp(uint8_t Op, const char *Comment = nullptr) = 0; @@ -229,7 +233,7 @@ void addReg(int DwarfReg, const char *Comment = nullptr); /// Emit a DW_OP_breg operation. - void addBReg(int DwarfReg, int Offset); + void addBReg(int DwarfReg, int Offset, const char *Comment = nullptr); /// Emit DW_OP_fbreg . void addFBReg(int Offset); @@ -237,10 +241,6 @@ /// Emit a partial DWARF register operation. /// /// \param MachineReg The register number. - /// \param MaxSize If the register must be composed from - /// sub-registers this is an upper bound - /// for how many bits the emitted DW_OP_piece - /// may cover. /// /// If size and offset is zero an operation for the entire register is /// emitted: Some targets do not provide a DWARF register number for every @@ -249,8 +249,7 @@ /// multiple subregisters that alias the register. /// /// \return false if no DWARF register exists for MachineReg. - bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg, - unsigned MaxSize = ~1U); + bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg); /// Emit a DW_OP_piece or DW_OP_bit_piece operation for a variable fragment. /// \param OffsetInBits This is an optional offset into the location that @@ -280,12 +279,15 @@ /// DWARF block which has been emitted to the temporary buffer. void finalizeEntryValue(); + /// Return the index of a base type with the given properties and + /// create one if necessary. + unsigned getOrCreateBaseType(unsigned BitSize, dwarf::TypeKind Encoding); + ~DwarfExpression() = default; public: DwarfExpression(unsigned DwarfVersion, DwarfCompileUnit &CU) - : CU(CU), SubRegisterSizeInBits(0), SubRegisterOffsetInBits(0), - LocationKind(Unknown), LocationFlags(Unknown), + : CU(CU), LocationKind(Unknown), LocationFlags(Unknown), DwarfVersion(DwarfVersion) {} /// This needs to be called last to commit any pending changes. Index: llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp =================================================================== --- llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp +++ llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp @@ -13,6 +13,7 @@ #include "DwarfExpression.h" #include "DwarfCompileUnit.h" #include "llvm/ADT/APInt.h" +#include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/SmallBitVector.h" #include "llvm/BinaryFormat/Dwarf.h" #include "llvm/CodeGen/Register.h" @@ -52,13 +53,13 @@ } } -void DwarfExpression::addBReg(int DwarfReg, int Offset) { +void DwarfExpression::addBReg(int DwarfReg, int Offset, const char *Comment) { assert(DwarfReg >= 0 && "invalid negative dwarf register number"); assert(!isRegisterLocation() && "location description already locked down"); if (DwarfReg < 32) { emitOp(dwarf::DW_OP_breg0 + DwarfReg); } else { - emitOp(dwarf::DW_OP_bregx); + emitOp(dwarf::DW_OP_bregx, Comment); emitUnsigned(DwarfReg); } emitSigned(Offset); @@ -97,10 +98,10 @@ } bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI, - unsigned MachineReg, unsigned MaxSize) { + unsigned MachineReg) { if (!llvm::Register::isPhysicalRegister(MachineReg)) { if (isFrameRegister(TRI, MachineReg)) { - DwarfRegs.push_back(Register::createRegister(-1, nullptr)); + DwarfRegs.push_back(Register::create(-1)); return true; } return false; @@ -110,7 +111,7 @@ // If this is a valid register number, emit it. if (Reg >= 0) { - DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); + DwarfRegs.push_back(Register::create(Reg)); return true; } @@ -122,9 +123,9 @@ unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg); unsigned Size = TRI.getSubRegIdxSize(Idx); unsigned RegOffset = TRI.getSubRegIdxOffset(Idx); - DwarfRegs.push_back(Register::createRegister(Reg, "super-register")); // Use a DW_OP_bit_piece to describe the sub-register. - setSubRegisterPiece(Size, RegOffset); + DwarfRegs.push_back(Register::createSuperReg(Reg, Size, RegOffset)); + setSuperRegisterPiece(Size, RegOffset); return true; } } @@ -136,10 +137,7 @@ const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); unsigned RegSize = TRI.getRegSizeInBits(*RC); // Keep track of the bits in the register we already emitted, so we - // can avoid emitting redundant aliasing subregs. Because this is - // just doing a greedy scan of all subregisters, it is possible that - // this doesn't find a combination of subregisters that fully cover - // the register (even though one may exist). + // can avoid emitting redundant aliasing subregs. SmallBitVector Coverage(RegSize, false); for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) { unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR); @@ -156,16 +154,11 @@ // If this sub-register has a DWARF number and we haven't covered // its range, and its range covers the value, emit a DWARF piece for it. - if (Offset < MaxSize && CurSubReg.test(Coverage)) { + if (CurSubReg.test(Coverage)) { // Emit a piece for any gap in the coverage. if (Offset > CurPos) - DwarfRegs.push_back(Register::createSubRegister( - -1, Offset - CurPos, "no DWARF register encoding")); - if (Offset == 0 && Size >= MaxSize) - DwarfRegs.push_back(Register::createRegister(Reg, "sub-register")); - else - DwarfRegs.push_back(Register::createSubRegister( - Reg, std::min(Size, MaxSize - Offset), "sub-register")); + return false; + DwarfRegs.push_back(Register::createSubReg(Reg, Size, Offset)); } // Mark it as emitted. Coverage.set(Offset, Offset + Size); @@ -176,11 +169,18 @@ return false; // Found a partial or complete DWARF encoding. if (CurPos < RegSize) - DwarfRegs.push_back(Register::createSubRegister( - -1, RegSize - CurPos, "no DWARF register encoding")); + return false; return true; } +const char *DwarfExpression::Register::getComment() const { + switch(Kind) { + case Register::Full: return nullptr; + case Register::SuperReg: return "super-register"; + case Register::SubReg: return "sub-register"; + } +} + void DwarfExpression::addStackValue() { if (DwarfVersion >= 4) emitOp(dwarf::DW_OP_stack_value); @@ -223,8 +223,9 @@ DIExpressionCursor &ExprCursor, unsigned MachineReg, unsigned FragmentOffsetInBits) { - auto Fragment = ExprCursor.getFragmentInfo(); - if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) { + auto ClearDwarfRegs = make_scope_exit([this] { DwarfRegs.clear(); }); + + if (!addMachineReg(TRI, MachineReg)) { LocationKind = Unknown; return false; } @@ -234,35 +235,86 @@ if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment) HasComplexExpression = true; - // If the register can only be described by a complex expression (i.e., - // multiple subregisters) it doesn't safely compose with another complex - // expression. For example, it is not possible to apply a DW_OP_deref - // operation to multiple DW_OP_pieces. + // If the register itself can only be described by combining + // multiple subregisters, we cannot use DW_OP_piece, since it + // doesn't safely compose with another complex expression, Since it + // is not possible to apply any DWARF operation to the combined + // DW_OP_pieces. By manualy shifting the subregisters into place, + // this can be worked around at the expense of a slightly larger + // encoding. if (HasComplexExpression && DwarfRegs.size() > 1) { - DwarfRegs.clear(); - LocationKind = Unknown; - return false; + if (isMemoryLocation()) + return false; + // Shift each piece into place and or the results together. No + // masking is necessary even if the subregisters are overlapping, + // since any overlapping bits in are expected be identical. + const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg); + unsigned RegSize = TRI.getRegSizeInBits(*RC); + bool Large = RegSize > CU.getAddressSize(); + bool First = true; + for (auto &Reg : DwarfRegs) { + if (Large) { + emitOp(dwarf::DW_OP_regval_type); + emitUnsigned(Reg.DwarfRegNo); + emitBaseTypeRef(getOrCreateBaseType(RegSize, dwarf::DW_ATE_unsigned)); + } else { + addBReg(Reg.DwarfRegNo, 0, Reg.getComment()); + } + if (Reg.SubRegisterOffsetInBits > 0) { + emitConstu(Reg.SubRegisterOffsetInBits); + emitOp(dwarf::DW_OP_shl); + } + if (!First) + emitOp(dwarf::DW_OP_or); + else + First = false; + } + return true; } - // Handle simple register locations. If we are supposed to emit - // a call site parameter expression and if that expression is just a register - // location, emit it with addBReg and offset 0, because we should emit a DWARF - // expression representing a value, rather than a location. + // Handle simple register locations. If we are supposed to emit a + // call site parameter expression and if that expression is just a + // register location, emit it with addBReg and offset 0, because we + // should emit a DWARF expression representing a value, rather than + // a location. if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() || isEntryValue())) { + unsigned BitsEmitted = 0; + auto Fragment = ExprCursor.getFragmentInfo(); + unsigned FragmentBits = + Fragment ? Fragment->SizeInBits : std::numeric_limits::max(); for (auto &Reg : DwarfRegs) { - if (Reg.DwarfRegNo >= 0) - addReg(Reg.DwarfRegNo, Reg.Comment); - addOpPiece(Reg.SubRegSize); + switch (Reg.Kind) { + case Register::Full: + case Register::SuperReg: + if (Reg.DwarfRegNo >= 0) + addReg(Reg.DwarfRegNo, Reg.getComment()); + break; + case Register::SubReg: { + // If the last subregister(s) extend beyond the size of the + // fragment, truncate the DW_OP_piece accordingly. This is safe + // because we have a simple expression. + unsigned SubRegBits = Reg.SubRegisterSizeInBits; + if (BitsEmitted + SubRegBits > FragmentBits) + SubRegBits -= (BitsEmitted + SubRegBits) - FragmentBits; + BitsEmitted += SubRegBits; + if (SubRegBits == 0) + break; + if (Reg.DwarfRegNo >= 0) + addReg(Reg.DwarfRegNo, Reg.getComment()); + if (SubRegBits < FragmentBits) + addOpPiece(SubRegBits); + break; + } + } } - + if (isEntryValue()) finalizeEntryValue(); if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4) emitOp(dwarf::DW_OP_stack_value); - DwarfRegs.clear(); return true; } @@ -271,16 +323,21 @@ if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool { return Op.getOp() == dwarf::DW_OP_stack_value; })) { - DwarfRegs.clear(); LocationKind = Unknown; return false; } - assert(DwarfRegs.size() == 1); - auto Reg = DwarfRegs[0]; + if (DwarfRegs.size() != 1) { + // While this could happen legitimately, it is more likely to + // indicate a bug. + assert(isMemoryLocation() && "pointer spawns multiple registers"); + return false; + } + + auto Reg = DwarfRegs.front(); bool FBReg = isFrameRegister(TRI, MachineReg); int SignedOffset = 0; - assert(!Reg.isSubRegister() && "full register expected"); + assert(Reg.Kind != Register::SubReg && "full register expected"); // Pattern-match combinations for which more efficient representations exist. // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset]. @@ -304,7 +361,7 @@ SignedOffset = Offset; ExprCursor.consume(2); } else if (N && N->getOp() == dwarf::DW_OP_minus && - !SubRegisterSizeInBits && Offset <= IntMax + 1) { + !Reg.SubRegisterSizeInBits && Offset <= IntMax + 1) { SignedOffset = -static_cast(Offset); ExprCursor.consume(2); } @@ -314,7 +371,6 @@ addFBReg(SignedOffset); else addBReg(Reg.DwarfRegNo, SignedOffset); - DwarfRegs.clear(); return true; } @@ -348,6 +404,21 @@ IsEmittingEntryValue = false; } +unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize, + dwarf::TypeKind Encoding) { + // Reuse the base_type if we already have one in this CU otherwise we + // create a new one. + unsigned I = 0, E = CU.ExprRefedBaseTypes.size(); + for (; I != E; ++I) + if (CU.ExprRefedBaseTypes[I].BitSize == BitSize && + CU.ExprRefedBaseTypes[I].Encoding == Encoding) + break; + + if (I == E) + CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding); + return I; +} + /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?". static bool isMemoryLocation(DIExpressionCursor ExprCursor) { while (ExprCursor) { @@ -365,11 +436,16 @@ void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor, unsigned FragmentOffsetInBits) { + auto N = ExprCursor.peek(); + // If we need to mask out a subregister, do it now, unless the next // operation would emit an OpPiece anyway. - auto N = ExprCursor.peek(); - if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment)) - maskSubRegister(); + if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment)) { + if (SubRegisterOffsetInBits > 0) + addShr(SubRegisterOffsetInBits); + uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL; + addAnd(Mask); + } Optional PrevConvertOp = None; @@ -411,7 +487,7 @@ // Emit the DW_OP_piece. addOpPiece(SizeInBits, SubRegisterOffsetInBits); - setSubRegisterPiece(0, 0); + setSuperRegisterPiece(0, 0); // Reset the location description kind. LocationKind = Unknown; return; @@ -455,16 +531,6 @@ dwarf::TypeKind Encoding = static_cast(Op->getArg(1)); if (DwarfVersion >= 5) { emitOp(dwarf::DW_OP_convert); - // Reuse the base_type if we already have one in this CU otherwise we - // create a new one. - unsigned I = 0, E = CU.ExprRefedBaseTypes.size(); - for (; I != E; ++I) - if (CU.ExprRefedBaseTypes[I].BitSize == BitSize && - CU.ExprRefedBaseTypes[I].Encoding == Encoding) - break; - - if (I == E) - CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding); // If targeting a location-list; simply emit the index into the raw // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been @@ -472,7 +538,7 @@ // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef // (containing the index and a resolve mechanism during emit) into the // DIE value list. - emitBaseTypeRef(I); + emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding)); } else { if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) { if (Encoding == dwarf::DW_ATE_signed) @@ -523,15 +589,6 @@ addStackValue(); } -/// add masking operations to stencil out a subregister. -void DwarfExpression::maskSubRegister() { - assert(SubRegisterSizeInBits && "no subregister was registered"); - if (SubRegisterOffsetInBits > 0) - addShr(SubRegisterOffsetInBits); - uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL; - addAnd(Mask); -} - void DwarfExpression::finalize() { assert(DwarfRegs.size() == 0 && "dwarf registers not emitted"); // Emit any outstanding DW_OP_piece operations to mask out subregisters. Index: llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir =================================================================== --- llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir +++ /dev/null @@ -1,123 +0,0 @@ -# RUN: llc -start-before=livedebugvalues -filetype=obj -o - %s | \ -# RUN: llvm-dwarfdump - | FileCheck %s -# -# This is an artificial example of a debug value residing in a composite -# location with a complex expression. Because the semantics of applying a DWARF -# expression to a composite location are ill-defined, the compiler should bail -# out of emitting a location. -# -# CHECK: .debug_info contents: -# CHECK: DW_TAG_variable -# CHECK-NOT: DW_AT_location -# CHECK: DW_TAG ---- | - ; Generated from: - ; typedef float vec2 __attribute__((vector_size(16))); - ; vec2 v(); - ; float f() { - ; vec2 vec = v(); - ; return vec[0] + vec[1]; - ; } - - target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" - target triple = "thumbv7s-apple-ios5.0.0" - - define float @f() local_unnamed_addr #0 !dbg !9 { - entry: - %call = tail call <4 x float> bitcast (<4 x float> (...)* @v to <4 x float> ()*)() #0, !dbg !19 - tail call void @llvm.dbg.value(metadata <4 x float> %call, i64 0, metadata !14, metadata !20), !dbg !21 - %vecext = extractelement <4 x float> %call, i32 0, !dbg !22 - %vecext1 = extractelement <4 x float> %call, i32 1, !dbg !23 - %add = fadd float %vecext, %vecext1, !dbg !24 - ret float %add, !dbg !25 - } - - declare arm_aapcs_vfpcc <4 x float> @v(...) local_unnamed_addr #0 - declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #0 - - attributes #0 = { nounwind readnone } - - !llvm.dbg.cu = !{!0} - !llvm.module.flags = !{!3, !4} - !llvm.ident = !{!8} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 286322) (llvm/trunk 286305)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) - !1 = !DIFile(filename: "v.c", directory: "/") - !2 = !{} - !3 = !{i32 2, !"Dwarf Version", i32 2} - !4 = !{i32 2, !"Debug Info Version", i32 3} - !8 = !{!"clang version 4.0.0 (trunk 286322) (llvm/trunk 286305)"} - !9 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 3, type: !10, isLocal: false, isDefinition: true, scopeLine: 3, isOptimized: true, unit: !0, retainedNodes: !13) - !10 = !DISubroutineType(types: !11) - !11 = !{!12} - !12 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) - !13 = !{!14} - !14 = !DILocalVariable(name: "vec", scope: !9, file: !1, line: 4, type: !15) - !15 = !DIDerivedType(tag: DW_TAG_typedef, name: "vec2", file: !1, line: 1, baseType: !16) - !16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !12, size: 128, flags: DIFlagVector, elements: !17) - !17 = !{!18} - !18 = !DISubrange(count: 4) - !19 = !DILocation(line: 4, column: 13, scope: !9) - !20 = !DIExpression(DW_OP_plus_uconst, 1, DW_OP_constu, 1, DW_OP_minus) - !21 = !DILocation(line: 4, column: 7, scope: !9) - !22 = !DILocation(line: 5, column: 9, scope: !9) - !23 = !DILocation(line: 5, column: 18, scope: !9) - !24 = !DILocation(line: 5, column: 16, scope: !9) - !25 = !DILocation(line: 5, column: 2, scope: !9) - -... ---- -name: f -alignment: 2 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -calleeSavedRegisters: [ '$lr', '$d8', '$d9', '$d10', '$d11', '$d12', '$d13', - '$d14', '$d15', '$q4', '$q5', '$q6', '$q7', '$r4', - '$r5', '$r6', '$r7', '$r8', '$r10', '$r11', '$s16', - '$s17', '$s18', '$s19', '$s20', '$s21', '$s22', - '$s23', '$s24', '$s25', '$s26', '$s27', '$s28', - '$s29', '$s30', '$s31', '$d8_d10', '$d9_d11', '$d10_d12', - '$d11_d13', '$d12_d14', '$d13_d15', '$q4_q5', '$q5_q6', - '$q6_q7', '$q4_q5_q6_q7', '$r4_r5', '$r6_r7', '$r10_r11', - '$d8_d9_d10', '$d9_d10_d11', '$d10_d11_d12', '$d11_d12_d13', - '$d12_d13_d14', '$d13_d14_d15', '$d8_d10_d12', - '$d9_d11_d13', '$d10_d12_d14', '$d11_d13_d15', - '$d8_d10_d12_d14', '$d9_d11_d13_d15', '$d9_d10', - '$d11_d12', '$d13_d14', '$d9_d10_d11_d12', '$d11_d12_d13_d14' ] -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 4 - offsetAdjustment: 0 - maxAlignment: 4 - adjustsStack: true - hasCalls: true - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -stack: - - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr' } -body: | - bb.0.entry: - liveins: $lr - - early-clobber $sp = frame-setup t2STR_PRE killed undef $lr, $sp, -4, 14, _ - frame-setup CFI_INSTRUCTION def_cfa_offset 4 - frame-setup CFI_INSTRUCTION offset $lr, -4 - tBL 14, _, @v, csr_ios, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $r0, implicit-def $r1, implicit-def $r2, implicit-def $r3, debug-location !19 - $d1 = VMOVDRR killed $r2, killed $r3, 14, _, implicit-def $q0, debug-location !19 - $d0 = VMOVDRR killed $r0, killed $r1, 14, _, implicit killed $q0, implicit-def $q0, debug-location !19 - DBG_VALUE $q0, _, !14, !20, debug-location !21 - $s4 = VMOVS $s1, 14, _, implicit-def $d2, debug-location !24 - $d0 = VADDfd $d0, killed $d2, 14, _, implicit killed $q0, debug-location !24 - $r0 = VMOVRS $s0, 14, _, implicit killed $d0, debug-location !25 - $lr, $sp = t2LDR_POST $sp, 4, 14, _, debug-location !25 - tBX_RET 14, _, implicit $r0, debug-location !25 - -... Index: llvm/test/DebugInfo/MIR/ARM/subregister-complex-expression.mir =================================================================== --- /dev/null +++ llvm/test/DebugInfo/MIR/ARM/subregister-complex-expression.mir @@ -0,0 +1,37 @@ +# RUN: llc -start-after=livedebugvalues -filetype=obj -o - %s | \ +# RUN: llvm-dwarfdump - | FileCheck %s +# +# Test applying a complex expression to a complex register. +# +# CHECK: .debug_info contents: +# CHECK: DW_TAG_variable +# CHECK-NOT: DW_TAG +# CHECK: DW_AT_location +# Q8 = {D16, D17} +# CHECK-NEXT: DW_OP_bregx D16+0, DW_OP_bregx D17+0, DW_OP_constu 0x40, DW_OP_shl, DW_OP_or, DW_OP_constu 0x20, DW_OP_shr +# CHECK-NOT: DW_TAG +# CHECK: DW_AT_name ("q8") + +--- | + target triple = "thumbv7s-apple-ios" + define hidden void @f() !dbg !5 { + for.body: + ret void, !dbg !20 + } + !llvm.module.flags = !{!1, !2} + !llvm.dbg.cu = !{!3} + !1 = !{i32 7, !"Dwarf Version", i32 4} + !2 = !{i32 2, !"Debug Info Version", i32 3} + !3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !4, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug) + !4 = !DIFile(filename: "t.cpp", directory: "/") + !5 = distinct !DISubprogram(name: "f", scope: !4, file: !4, line: 1, type: !6, scopeLine: 1, unit: !3) + !6 = !DISubroutineType(types: !{}) + !7 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "uint8x8x2_t", file: !4, line: 113, size: 128, flags: DIFlagTypePassByValue, elements: !{}) + !8 = !DILocalVariable(name: "q8", scope: !5, file: !4, line: 1, type: !7) + !20 = !DILocation(line: 0, scope: !5) +name: f +body: | + bb.2.for.body: + t2Bcc %bb.2.for.body, 0, killed $cpsr, debug-location !20 + DBG_VALUE $q8, $noreg, !8, !DIExpression(DW_OP_constu, 32, DW_OP_shr), debug-location !20 + tB %bb.2.for.body, 14, $noreg