Index: llvm/lib/CodeGen/ReachingDefAnalysis.cpp
===================================================================
--- llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -231,6 +231,9 @@
   MachineBasicBlock *MBB = Def->getParent();
   MachineBasicBlock::iterator MI = MachineBasicBlock::iterator(Def);
   while (++MI != MBB->end()) {
+    if (MI->isDebugInstr())
+      continue;
+
     // If/when we find a new reaching def, we know that there's no more uses
     // of 'Def'.
     if (getReachingMIDef(&*MI, PhysReg) != Def)
@@ -251,6 +254,8 @@
 ReachingDefAnalysis::getLiveInUses(MachineBasicBlock *MBB, int PhysReg,
                                    SmallPtrSetImpl<MachineInstr*> &Uses) const {
   for (auto &MI : *MBB) {
+    if (MI.isDebugInstr())
+      continue;
     for (auto &MO : MI.operands()) {
       if (!MO.isReg() || !MO.isUse() || MO.getReg() != PhysReg)
         continue;
Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
@@ -0,0 +1,638 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+
+# A decent size test with both scalar and vector low-overhead loops.
+# Test that debug information doesn't make everything fall over.
+
+--- |
+  define dso_local arm_aapcs_vfpcc signext i16 @matrix_test(i32 %d, i32* nocapture %e, i16* nocapture readonly %k, i16* nocapture readonly %l) local_unnamed_addr !dbg !8 {
+  entry:
+    call void @llvm.dbg.value(metadata i32 %d, metadata !18, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i32* %e, metadata !19, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i16* %k, metadata !20, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i16* %l, metadata !21, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i16 0, metadata !24, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i32 %d, metadata !30, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32* %e, metadata !35, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i16 0, metadata !36, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 0, metadata !38, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i16 0, metadata !42, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 0, metadata !41, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 0, metadata !40, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 undef, metadata !37, metadata !DIExpression()), !dbg !43
+    %cmp19.i = icmp sgt i32 %d, 0, !dbg !45
+    br i1 %cmp19.i, label %for.body.i.preheader, label %c.exit.thread, !dbg !48
+
+  for.body.i.preheader:                             ; preds = %entry
+    call void @llvm.set.loop.iterations.i32(i32 %d), !dbg !48
+    br label %for.body.i, !dbg !48
+
+  c.exit.thread:                                    ; preds = %entry
+    call void @llvm.dbg.value(metadata i16 undef, metadata !42, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i16 undef, metadata !23, metadata !DIExpression()), !dbg !29
+    %call169 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32)*)(i32 0), !dbg !49
+    %conv270 = sext i16 %call169 to i32, !dbg !49
+    call void @llvm.dbg.value(metadata i32 0, metadata !27, metadata !DIExpression()), !dbg !29
+    br label %c.exit59, !dbg !50
+
+  for.body.i:                                       ; preds = %for.body.i, %for.body.i.preheader
+    %lsr.iv15 = phi i32* [ %e, %for.body.i.preheader ], [ %scevgep16, %for.body.i ]
+    %h.022.i = phi i16 [ %h.1.i, %for.body.i ], [ 0, %for.body.i.preheader ]
+    %f.020.i = phi i32 [ %f.1.i, %for.body.i ], [ undef, %for.body.i.preheader ]
+    %0 = phi i32 [ %d, %for.body.i.preheader ], [ %2, %for.body.i ], !dbg !43
+    call void @llvm.dbg.value(metadata i16 %h.022.i, metadata !42, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 undef, metadata !41, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 %f.020.i, metadata !37, metadata !DIExpression()), !dbg !43
+    %1 = load i32, i32* %lsr.iv15, align 4, !dbg !52
+    call void @llvm.dbg.value(metadata i32 %1, metadata !39, metadata !DIExpression()), !dbg !43
+    %add.i = add nsw i32 %1, %f.020.i, !dbg !54
+    call void @llvm.dbg.value(metadata i32 %add.i, metadata !37, metadata !DIExpression()), !dbg !43
+    %cmp1.i = icmp sgt i32 %add.i, 0, !dbg !55
+    %cmp3.i = icmp sgt i32 %1, 0, !dbg !57
+    %f.1.i = select i1 %cmp1.i, i32 0, i32 %add.i, !dbg !57
+    %narrow.i = and i1 %cmp3.i, %cmp1.i, !dbg !57
+    %add6.i = zext i1 %narrow.i to i16, !dbg !57
+    %h.1.i = add i16 %h.022.i, %add6.i, !dbg !57
+    call void @llvm.dbg.value(metadata i16 %h.1.i, metadata !42, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 %f.1.i, metadata !37, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i32 undef, metadata !41, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !43
+    %scevgep16 = getelementptr i32, i32* %lsr.iv15, i32 1, !dbg !45
+    %2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1), !dbg !48
+    %3 = icmp ne i32 %2, 0, !dbg !48
+    br i1 %3, label %for.body.i, label %c.exit, !dbg !48, !llvm.loop !58
+
+  c.exit:                                           ; preds = %for.body.i
+    %4 = icmp sgt i32 %d, 0, !dbg !45
+    %phitmp = sext i16 %h.1.i to i32, !dbg !60
+    call void @llvm.dbg.value(metadata i16 undef, metadata !42, metadata !DIExpression()), !dbg !43
+    call void @llvm.dbg.value(metadata i16 undef, metadata !23, metadata !DIExpression()), !dbg !29
+    %call1 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32)*)(i32 %phitmp), !dbg !49
+    %conv2 = sext i16 %call1 to i32, !dbg !49
+    call void @llvm.dbg.value(metadata i32 %conv2, metadata !25, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i32 %conv2, metadata !25, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i32 0, metadata !27, metadata !DIExpression()), !dbg !29
+    br i1 %4, label %for.cond4.preheader.us.preheader, label %c.exit59, !dbg !50
+
+  for.cond4.preheader.us.preheader:                 ; preds = %c.exit
+    %n.rnd.up = add i32 %d, 3, !dbg !61
+    %n.vec = and i32 %n.rnd.up, -4, !dbg !61
+    %5 = shl i32 %d, 1, !dbg !50
+    %6 = add i32 %n.vec, -4, !dbg !50
+    %7 = lshr i32 %6, 2, !dbg !50
+    %8 = add nuw nsw i32 %7, 1, !dbg !50
+    %9 = shl i32 %7, 2, !dbg !50
+    %10 = sub i32 %d, %9, !dbg !50
+    br label %for.cond4.preheader.us, !dbg !50
+
+  for.cond4.preheader.us:                           ; preds = %middle.block, %for.cond4.preheader.us.preheader
+    %lsr.iv7 = phi i16* [ %28, %middle.block ], [ %k, %for.cond4.preheader.us.preheader ]
+    %i.064.us = phi i32 [ %inc15.us, %middle.block ], [ 0, %for.cond4.preheader.us.preheader ]
+    call void @llvm.dbg.value(metadata i32 %i.064.us, metadata !27, metadata !DIExpression()), !dbg !29
+    call void @llvm.dbg.value(metadata i32 0, metadata !28, metadata !DIExpression()), !dbg !29
+    %arrayidx12.us = getelementptr inbounds i32, i32* %e, i32 %i.064.us, !dbg !64
+    %arrayidx12.promoted.us = load i32, i32* %arrayidx12.us, align 4, !dbg !66
+    %11 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %arrayidx12.promoted.us, i32 0, !dbg !67
+    call void @llvm.set.loop.iterations.i32(i32 %8), !dbg !67
+    br label %vector.body, !dbg !67
+
+  vector.body:                                      ; preds = %vector.body, %for.cond4.preheader.us
+    %lsr.iv10 = phi i16* [ %scevgep11, %vector.body ], [ %lsr.iv7, %for.cond4.preheader.us ], !dbg !68
+    %lsr.iv4 = phi i16* [ %scevgep5, %vector.body ], [ %l, %for.cond4.preheader.us ], !dbg !68
+    %vec.phi = phi <4 x i32> [ %11, %for.cond4.preheader.us ], [ %19, %vector.body ]
+    %12 = phi i32 [ %8, %for.cond4.preheader.us ], [ %20, %vector.body ]
+    %13 = phi i32 [ %d, %for.cond4.preheader.us ], [ %15, %vector.body ]
+    %lsr.iv1012 = bitcast i16* %lsr.iv10 to <4 x i16>*
+    %lsr.iv46 = bitcast i16* %lsr.iv4 to <4 x i16>*
+    %14 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %13), !dbg !69
+    %15 = sub i32 %13, 4, !dbg !69
+    %wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1012, i32 2, <4 x i1> %14, <4 x i16> undef), !dbg !69
+    %16 = sext <4 x i16> %wide.masked.load to <4 x i32>, !dbg !69
+    %wide.masked.load76 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv46, i32 2, <4 x i1> %14, <4 x i16> undef), !dbg !70
+    %17 = sext <4 x i16> %wide.masked.load76 to <4 x i32>, !dbg !70
+    %18 = mul nsw <4 x i32> %17, %16, !dbg !71
+    %19 = add <4 x i32> %18, %vec.phi, !dbg !66
+    %scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 4, !dbg !68
+    %scevgep11 = getelementptr i16, i16* %lsr.iv10, i32 4, !dbg !68
+    %20 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %12, i32 1), !dbg !68
+    %21 = icmp ne i32 %20, 0, !dbg !68
+    br i1 %21, label %vector.body, label %middle.block, !dbg !68, !llvm.loop !72
+
+  middle.block:                                     ; preds = %vector.body
+    %vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]
+    %.lcssa = phi <4 x i32> [ %19, %vector.body ], !dbg !66
+    %22 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %10), !dbg !69
+    %23 = bitcast i16* %lsr.iv7 to i1*
+    %24 = select <4 x i1> %22, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa, !dbg !66
+    %25 = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %24), !dbg !67
+    %sunkaddr = mul i32 %i.064.us, 4, !dbg !66
+    %26 = bitcast i32* %e to i8*, !dbg !66
+    %sunkaddr17 = getelementptr inbounds i8, i8* %26, i32 %sunkaddr, !dbg !66
+    %27 = bitcast i8* %sunkaddr17 to i32*, !dbg !66
+    store i32 %25, i32* %27, align 4, !dbg !66
+    %inc15.us = add nuw nsw i32 %i.064.us, 1, !dbg !75
+    call void @llvm.dbg.value(metadata i32 %inc15.us, metadata !27, metadata !DIExpression()), !dbg !29
+    %scevgep9 = getelementptr i1, i1* %23, i32 %5, !dbg !50
+    %28 = bitcast i1* %scevgep9 to i16*, !dbg !50
+    %exitcond66 = icmp eq i32 %inc15.us, %d, !dbg !76
+    br i1 %exitcond66, label %for.end16, label %for.cond4.preheader.us, !dbg !50, !llvm.loop !77
+
+  for.end16:                                        ; preds = %middle.block
+    %29 = icmp sgt i32 %d, 0, !dbg !45
+    call void @llvm.dbg.value(metadata i32 %d, metadata !30, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32* %e, metadata !35, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i16 0, metadata !36, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 0, metadata !38, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i16 0, metadata !42, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 0, metadata !41, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 0, metadata !40, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 undef, metadata !37, metadata !DIExpression()), !dbg !79
+    br i1 %29, label %for.body.i57.preheader, label %c.exit59, !dbg !81
+
+  for.body.i57.preheader:                           ; preds = %for.end16
+    call void @llvm.set.loop.iterations.i32(i32 %d), !dbg !81
+    br label %for.body.i57, !dbg !81
+
+  for.body.i57:                                     ; preds = %for.body.i57, %for.body.i57.preheader
+    %lsr.iv1 = phi i32* [ %e, %for.body.i57.preheader ], [ %scevgep, %for.body.i57 ]
+    %h.022.i44 = phi i16 [ %h.1.i54, %for.body.i57 ], [ 0, %for.body.i57.preheader ]
+    %f.020.i46 = phi i32 [ %f.1.i51, %for.body.i57 ], [ undef, %for.body.i57.preheader ]
+    %30 = phi i32 [ %d, %for.body.i57.preheader ], [ %32, %for.body.i57 ], !dbg !79
+    call void @llvm.dbg.value(metadata i16 %h.022.i44, metadata !42, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 undef, metadata !41, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 %f.020.i46, metadata !37, metadata !DIExpression()), !dbg !79
+    %31 = load i32, i32* %lsr.iv1, align 4, !dbg !82
+    call void @llvm.dbg.value(metadata i32 %31, metadata !39, metadata !DIExpression()), !dbg !79
+    %add.i48 = add nsw i32 %31, %f.020.i46, !dbg !83
+    call void @llvm.dbg.value(metadata i32 %add.i48, metadata !37, metadata !DIExpression()), !dbg !79
+    %cmp1.i49 = icmp sgt i32 %add.i48, 0, !dbg !84
+    %cmp3.i50 = icmp sgt i32 %31, 0, !dbg !85
+    %f.1.i51 = select i1 %cmp1.i49, i32 0, i32 %add.i48, !dbg !85
+    %narrow.i52 = and i1 %cmp3.i50, %cmp1.i49, !dbg !85
+    %add6.i53 = zext i1 %narrow.i52 to i16, !dbg !85
+    %h.1.i54 = add i16 %h.022.i44, %add6.i53, !dbg !85
+    call void @llvm.dbg.value(metadata i16 %h.1.i54, metadata !42, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 %f.1.i51, metadata !37, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i32 undef, metadata !41, metadata !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value)), !dbg !79
+    %scevgep = getelementptr i32, i32* %lsr.iv1, i32 1, !dbg !86
+    %32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %30, i32 1), !dbg !81
+    %33 = icmp ne i32 %32, 0, !dbg !81
+    br i1 %33, label %for.body.i57, label %c.exit59.loopexit, !dbg !81
+
+  c.exit59.loopexit:                                ; preds = %for.body.i57
+    %phitmp67 = sext i16 %h.1.i54 to i32, !dbg !89
+    br label %c.exit59, !dbg !89
+
+  c.exit59:                                         ; preds = %c.exit59.loopexit, %for.end16, %c.exit, %c.exit.thread
+    %conv27173 = phi i32 [ %conv2, %for.end16 ], [ %conv2, %c.exit59.loopexit ], [ %conv2, %c.exit ], [ %conv270, %c.exit.thread ]
+    %h.0.lcssa.i58 = phi i32 [ 0, %for.end16 ], [ %phitmp67, %c.exit59.loopexit ], [ 0, %c.exit ], [ 0, %c.exit.thread ]
+    call void @llvm.dbg.value(metadata i16 undef, metadata !42, metadata !DIExpression()), !dbg !79
+    call void @llvm.dbg.value(metadata i16 undef, metadata !22, metadata !DIExpression()), !dbg !29
+    %call19 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32, i32)*)(i32 %h.0.lcssa.i58, i32 %conv27173), !dbg !90
+    call void @llvm.dbg.value(metadata i16 %call19, metadata !25, metadata !DIExpression(DW_OP_LLVM_convert, 16, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)), !dbg !29
+    ret i16 %call19, !dbg !91
+  }
+  declare dso_local arm_aapcs_vfpcc signext i16 @crc16(...) local_unnamed_addr
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+  declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
+  declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
+  declare void @llvm.set.loop.iterations.i32(i32)
+  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
+  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5, !6}
+  !llvm.ident = !{!7}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 10.0.0 (https://github.com/llvm/llvm-project.git 9c91d79dadc660cb6a0ec736389341debd8cd118)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None)
+  !1 = !DIFile(filename: "matrix-hang.c", directory: "/home/sampar01/src/tests/tail-predication")
+  !2 = !{}
+  !3 = !{i32 7, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"wchar_size", i32 4}
+  !6 = !{i32 1, !"min_enum_size", i32 4}
+  !7 = !{!"clang version 10.0.0 (https://github.com/llvm/llvm-project.git 9c91d79dadc660cb6a0ec736389341debd8cd118)"}
+  !8 = distinct !DISubprogram(name: "matrix_test", scope: !1, file: !1, line: 18, type: !9, scopeLine: 18, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17)
+  !9 = !DISubroutineType(types: !10)
+  !10 = !{!11, !12, !14, !16, !16}
+  !11 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
+  !12 = !DIDerivedType(tag: DW_TAG_typedef, name: "a", file: !1, line: 1, baseType: !13)
+  !13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !14 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !15, size: 32)
+  !15 = !DIDerivedType(tag: DW_TAG_typedef, name: "b", file: !1, line: 2, baseType: !13)
+  !16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !11, size: 32)
+  !17 = !{!18, !19, !20, !21, !22, !23, !24, !25, !27, !28}
+  !18 = !DILocalVariable(name: "d", arg: 1, scope: !8, file: !1, line: 18, type: !12)
+  !19 = !DILocalVariable(name: "e", arg: 2, scope: !8, file: !1, line: 18, type: !14)
+  !20 = !DILocalVariable(name: "k", arg: 3, scope: !8, file: !1, line: 18, type: !16)
+  !21 = !DILocalVariable(name: "l", arg: 4, scope: !8, file: !1, line: 18, type: !16)
+  !22 = !DILocalVariable(name: "m", scope: !8, file: !1, line: 19, type: !11)
+  !23 = !DILocalVariable(name: "n", scope: !8, file: !1, line: 19, type: !11)
+  !24 = !DILocalVariable(name: "clipval", scope: !8, file: !1, line: 19, type: !11)
+  !25 = !DILocalVariable(name: "crc", scope: !8, file: !1, line: 20, type: !26)
+  !26 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
+  !27 = !DILocalVariable(name: "i", scope: !8, file: !1, line: 23, type: !12)
+  !28 = !DILocalVariable(name: "j", scope: !8, file: !1, line: 23, type: !12)
+  !29 = !DILocation(line: 0, scope: !8)
+  !30 = !DILocalVariable(name: "d", arg: 1, scope: !31, file: !1, line: 4, type: !12)
+  !31 = distinct !DISubprogram(name: "c", scope: !1, file: !1, line: 4, type: !32, scopeLine: 4, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !34)
+  !32 = !DISubroutineType(types: !33)
+  !33 = !{!11, !12, !14, !11}
+  !34 = !{!30, !35, !36, !37, !38, !39, !40, !41, !42}
+  !35 = !DILocalVariable(name: "e", arg: 2, scope: !31, file: !1, line: 4, type: !14)
+  !36 = !DILocalVariable(name: "k", arg: 3, scope: !31, file: !1, line: 4, type: !11)
+  !37 = !DILocalVariable(name: "f", scope: !31, file: !1, line: 5, type: !15)
+  !38 = !DILocalVariable(name: "g", scope: !31, file: !1, line: 5, type: !15)
+  !39 = !DILocalVariable(name: "cur", scope: !31, file: !1, line: 5, type: !15)
+  !40 = !DILocalVariable(name: "i", scope: !31, file: !1, line: 5, type: !15)
+  !41 = !DILocalVariable(name: "j", scope: !31, file: !1, line: 5, type: !15)
+  !42 = !DILocalVariable(name: "h", scope: !31, file: !1, line: 6, type: !11)
+  !43 = !DILocation(line: 0, scope: !31, inlinedAt: !44)
+  !44 = distinct !DILocation(line: 21, column: 7, scope: !8)
+  !45 = !DILocation(line: 7, column: 21, scope: !46, inlinedAt: !44)
+  !46 = distinct !DILexicalBlock(scope: !47, file: !1, line: 7, column: 3)
+  !47 = distinct !DILexicalBlock(scope: !31, file: !1, line: 7, column: 3)
+  !48 = !DILocation(line: 7, column: 3, scope: !47, inlinedAt: !44)
+  !49 = !DILocation(line: 22, column: 9, scope: !8)
+  !50 = !DILocation(line: 24, column: 3, scope: !51)
+  !51 = distinct !DILexicalBlock(scope: !8, file: !1, line: 24, column: 3)
+  !52 = !DILocation(line: 8, column: 11, scope: !53, inlinedAt: !44)
+  !53 = distinct !DILexicalBlock(scope: !46, file: !1, line: 7, column: 31)
+  !54 = !DILocation(line: 9, column: 7, scope: !53, inlinedAt: !44)
+  !55 = !DILocation(line: 10, column: 11, scope: !56, inlinedAt: !44)
+  !56 = distinct !DILexicalBlock(scope: !53, file: !1, line: 10, column: 9)
+  !57 = !DILocation(line: 10, column: 9, scope: !53, inlinedAt: !44)
+  !58 = distinct !{!58, !48, !59}
+  !59 = !DILocation(line: 14, column: 3, scope: !47, inlinedAt: !44)
+  !60 = !DILocation(line: 22, column: 15, scope: !8)
+  !61 = !DILocation(line: 0, scope: !62)
+  !62 = distinct !DILexicalBlock(scope: !63, file: !1, line: 25, column: 5)
+  !63 = distinct !DILexicalBlock(scope: !51, file: !1, line: 24, column: 3)
+  !64 = !DILocation(line: 0, scope: !65)
+  !65 = distinct !DILexicalBlock(scope: !62, file: !1, line: 25, column: 5)
+  !66 = !DILocation(line: 26, column: 12, scope: !65)
+  !67 = !DILocation(line: 25, column: 5, scope: !62)
+  !68 = !DILocation(line: 25, column: 25, scope: !65)
+  !69 = !DILocation(line: 26, column: 15, scope: !65)
+  !70 = !DILocation(line: 26, column: 30, scope: !65)
+  !71 = !DILocation(line: 26, column: 28, scope: !65)
+  !72 = distinct !{!72, !67, !73, !74}
+  !73 = !DILocation(line: 26, column: 33, scope: !62)
+  !74 = !{!"llvm.loop.isvectorized", i32 1}
+  !75 = !DILocation(line: 24, column: 23, scope: !63)
+  !76 = !DILocation(line: 24, column: 17, scope: !63)
+  !77 = distinct !{!77, !50, !78}
+  !78 = !DILocation(line: 26, column: 33, scope: !51)
+  !79 = !DILocation(line: 0, scope: !31, inlinedAt: !80)
+  !80 = distinct !DILocation(line: 27, column: 9, scope: !8)
+  !81 = !DILocation(line: 7, column: 3, scope: !47, inlinedAt: !80)
+  !82 = !DILocation(line: 8, column: 11, scope: !53, inlinedAt: !80)
+  !83 = !DILocation(line: 9, column: 7, scope: !53, inlinedAt: !80)
+  !84 = !DILocation(line: 10, column: 11, scope: !56, inlinedAt: !80)
+  !85 = !DILocation(line: 10, column: 9, scope: !53, inlinedAt: !80)
+  !86 = !DILocation(line: 7, column: 21, scope: !46, inlinedAt: !80)
+  !87 = distinct !{!87, !81, !88}
+  !88 = !DILocation(line: 14, column: 3, scope: !47, inlinedAt: !80)
+  !89 = !DILocation(line: 28, column: 15, scope: !8)
+  !90 = !DILocation(line: 28, column: 9, scope: !8)
+  !91 = !DILocation(line: 29, column: 3, scope: !8)
+
+...
+---
+name:            matrix_test
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r2', virtual-reg: '' }
+  - { reg: '$r3', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       40
+  offsetAdjustment: -32
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 8, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: matrix_test
+  ; CHECK: bb.1.for.body.i.preheader:
+  ; CHECK:   $lr = t2DLS killed renamable $r0
+  ; CHECK: bb.2.for.body.i:
+  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2, debug-location !48
+  ; CHECK: bb.5.for.cond4.preheader.us:
+  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
+  ; CHECK: bb.6.vector.body:
+  ; CHECK:   $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q2
+  ; CHECK:   renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 0, $noreg, debug-location !69 :: (load 8 from %ir.lsr.iv1012, align 2)
+  ; CHECK:   renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 0, killed $noreg, debug-location !70 :: (load 8 from %ir.lsr.iv46, align 2)
+  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1, debug-location !71
+  ; CHECK:   renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1, debug-location !66
+  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.6, debug-location !68
+  ; CHECK: bb.7.middle.block:
+  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r10, 0, $noreg, debug-location !69
+  ; CHECK:   renamable $r4 = tADDhirr killed renamable $r4, renamable $r3, 14, $noreg, debug-location !50
+  ; CHECK:   renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, debug-location !66
+  ; CHECK: bb.9.for.body.i57.preheader:
+  ; CHECK:   $lr = t2DLS killed renamable $lr, debug-location !81
+  ; CHECK: bb.10.for.body.i57:
+  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.10, debug-location !81
+  bb.0.entry:
+    successors: %bb.1(0x50000000), %bb.12(0x30000000)
+    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10, $r11
+
+    DBG_VALUE $r0, $noreg, !18, !DIExpression(), debug-location !29
+    DBG_VALUE $r1, $noreg, !19, !DIExpression(), debug-location !29
+    DBG_VALUE $r2, $noreg, !20, !DIExpression(), debug-location !29
+    DBG_VALUE $r3, $noreg, !21, !DIExpression(), debug-location !29
+    DBG_VALUE $r0, $noreg, !30, !DIExpression(), debug-location !43
+    DBG_VALUE $r1, $noreg, !35, !DIExpression(), debug-location !43
+    DBG_VALUE $r3, $noreg, !21, !DIExpression(), debug-location !29
+    DBG_VALUE $r2, $noreg, !20, !DIExpression(), debug-location !29
+    DBG_VALUE 0, $noreg, !36, !DIExpression(), debug-location !43
+    DBG_VALUE $r1, $noreg, !35, !DIExpression(), debug-location !43
+    DBG_VALUE $r0, $noreg, !30, !DIExpression(), debug-location !43
+    DBG_VALUE $r1, $noreg, !19, !DIExpression(), debug-location !29
+    DBG_VALUE $r0, $noreg, !18, !DIExpression(), debug-location !29
+    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 20
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    frame-setup CFI_INSTRUCTION offset $r6, -12
+    frame-setup CFI_INSTRUCTION offset $r5, -16
+    frame-setup CFI_INSTRUCTION offset $r4, -20
+    $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
+    frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+    $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r10, killed $r11
+    frame-setup CFI_INSTRUCTION offset $r11, -24
+    frame-setup CFI_INSTRUCTION offset $r10, -28
+    frame-setup CFI_INSTRUCTION offset $r9, -32
+    frame-setup CFI_INSTRUCTION offset $r8, -36
+    $sp = frame-setup tSUBspi $sp, 1, 14, $noreg
+    DBG_VALUE $noreg, $noreg, !37, !DIExpression(), debug-location !43
+    DBG_VALUE 0, $noreg, !40, !DIExpression(), debug-location !43
+    DBG_VALUE 0, $noreg, !41, !DIExpression(), debug-location !43
+    DBG_VALUE 0, $noreg, !42, !DIExpression(), debug-location !43
+    DBG_VALUE 0, $noreg, !38, !DIExpression(), debug-location !43
+    DBG_VALUE 0, $noreg, !24, !DIExpression(), debug-location !29
+    tCMPi8 renamable $r0, 1, 14, $noreg, implicit-def $cpsr, debug-location !48
+    t2Bcc %bb.12, 11, killed $cpsr, debug-location !48
+
+  bb.1.for.body.i.preheader:
+    successors: %bb.2(0x80000000)
+    liveins: $r0, $r1, $r2, $r3
+
+    $r4 = tMOVr killed $r2, 14, $noreg
+    DBG_VALUE $r4, $noreg, !20, !DIExpression(), debug-location !29
+    $r8 = tMOVr killed $r3, 14, $noreg
+    DBG_VALUE $r8, $noreg, !21, !DIExpression(), debug-location !29
+    $r9 = tMOVr $r1, 14, $noreg
+    DBG_VALUE $r9, $noreg, !19, !DIExpression(), debug-location !29
+    DBG_VALUE $r9, $noreg, !35, !DIExpression(), debug-location !43
+    renamable $r5, dead $cpsr = tMOVi8 0, 14, $noreg
+    renamable $r2 = IMPLICIT_DEF
+    $r11 = tMOVr $r0, 14, $noreg
+    $lr = tMOVr $r0, 14, $noreg
+    t2DoLoopStart killed renamable $r0, debug-location !48
+
+  bb.2.for.body.i:
+    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $lr, $r1, $r2, $r4, $r5, $r8, $r9, $r11
+
+    DBG_VALUE $r5, $noreg, !42, !DIExpression(), debug-location !43
+    DBG_VALUE $noreg, $noreg, !41, !DIExpression(), debug-location !43
+    DBG_VALUE $r2, $noreg, !37, !DIExpression(), debug-location !43
+    renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14, $noreg, debug-location !52 :: (load 4 from %ir.lsr.iv15)
+    DBG_VALUE $r3, $noreg, !39, !DIExpression(), debug-location !43
+    renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !48
+    renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14, $noreg, debug-location !54
+    DBG_VALUE $r2, $noreg, !37, !DIExpression(), debug-location !43
+    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr, debug-location !55
+    renamable $r6 = t2CSINC $zr, $zr, 13, implicit killed $cpsr, debug-location !55
+    tCMPi8 killed renamable $r3, 0, 14, $noreg, implicit-def $cpsr, debug-location !57
+    renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr, debug-location !57
+    tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr, debug-location !57
+    renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r6, 14, $noreg, $noreg, debug-location !57
+    t2IT 12, 8, implicit-def $itstate, debug-location !57
+    $r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate, debug-location !57
+    DBG_VALUE $noreg, $noreg, !41, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !43
+    DBG_VALUE $r2, $noreg, !37, !DIExpression(), debug-location !43
+    renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r3, 14, $noreg, debug-location !57
+    DBG_VALUE $r5, $noreg, !42, !DIExpression(), debug-location !43
+    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr, debug-location !48
+    tB %bb.3, 14, $noreg, debug-location !48
+
+  bb.3.c.exit:
+    successors: %bb.4(0x50000000), %bb.14(0x30000000)
+    liveins: $r4, $r5, $r8, $r9, $r11
+
+    DBG_VALUE $noreg, $noreg, !42, !DIExpression(), debug-location !43
+    DBG_VALUE $noreg, $noreg, !23, !DIExpression(), debug-location !29
+    renamable $r0 = tSXTH killed renamable $r5, 14, $noreg, debug-location !60
+    tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0, debug-location !49
+    $r12 = tMOVr killed $r0, 14, $noreg, debug-location !49
+    DBG_VALUE $r12, $noreg, !25, !DIExpression(), debug-location !29
+    renamable $r5, dead $cpsr = tMOVi8 0, 14, $noreg
+    DBG_VALUE 0, $noreg, !27, !DIExpression(), debug-location !29
+    t2CMPri $r11, 1, 14, $noreg, implicit-def $cpsr, debug-location !50
+    tBcc %bb.14, 11, killed $cpsr, debug-location !50
+
+  bb.4.for.cond4.preheader.us.preheader:
+    successors: %bb.5(0x80000000)
+    liveins: $r4, $r5, $r8, $r9, $r11, $r12
+
+    renamable $r0 = t2ADDri $r11, 3, 14, $noreg, $noreg, debug-location !61
+    $lr = tMOVr $r11, 14, $noreg
+    renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg, debug-location !61
+    renamable $r3 = t2LSLri $r11, 1, 14, $noreg, $noreg, debug-location !50
+    renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg, debug-location !50
+    renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg
+    renamable $q0 = MVE_VDUP32 renamable $r5, 0, $noreg, undef renamable $q0
+    renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg, debug-location !50
+    renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg, debug-location !50
+    renamable $r10 = t2SUBrs $r11, killed renamable $r1, 18, 14, $noreg, $noreg, debug-location !50
+
+  bb.5.for.cond4.preheader.us:
+    successors: %bb.6(0x80000000)
+    liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r8, $r9, $r10, $r11, $r12
+
+    DBG_VALUE $r5, $noreg, !27, !DIExpression(), debug-location !29
+    DBG_VALUE 0, $noreg, !28, !DIExpression(), debug-location !29
+    renamable $r1 = t2LDRs renamable $r9, renamable $r5, 2, 14, $noreg, debug-location !66 :: (load 4 from %ir.arrayidx12.us)
+    $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1, debug-location !67
+    $r2 = tMOVr killed $lr, 14, $noreg
+    renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg, debug-location !67
+    $r6 = tMOVr $r4, 14, $noreg, debug-location !68
+    $r1 = tMOVr $r8, 14, $noreg, debug-location !68
+    $lr = tMOVr $r0, 14, $noreg
+    t2DoLoopStart renamable $r0, debug-location !67
+
+  bb.6.vector.body:
+    successors: %bb.6(0x7c000000), %bb.7(0x04000000)
+    liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
+
+    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, debug-location !69
+    $q2 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q2
+    MVE_VPST 4, implicit $vpr, debug-location !69
+    renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, debug-location !69 :: (load 8 from %ir.lsr.iv1012, align 2)
+    renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, debug-location !70 :: (load 8 from %ir.lsr.iv46, align 2)
+    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg, debug-location !69
+    renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, undef renamable $q1, debug-location !71
+    renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !68
+    renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, undef renamable $q1, debug-location !66
+    t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr, debug-location !68
+    tB %bb.7, 14, $noreg, debug-location !68
+
+  bb.7.middle.block:
+    successors: %bb.8(0x04000000), %bb.5(0x7c000000)
+    liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r8, $r9, $r10, $r11, $r12
+
+    renamable $vpr = MVE_VCTP32 renamable $r10, 0, $noreg, debug-location !69
+    renamable $r4 = tADDhirr killed renamable $r4, renamable $r3, 14, $noreg, debug-location !50
+    renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, debug-location !66
+    $lr = tMOVr $r11, 14, $noreg
+    renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, debug-location !67
+    t2STRs killed renamable $r2, renamable $r9, renamable $r5, 2, 14, $noreg, debug-location !66 :: (store 4 into %ir.27)
+    renamable $r5, dead $cpsr = nuw nsw tADDi8 killed renamable $r5, 1, 14, $noreg, debug-location !75
+    DBG_VALUE $r5, $noreg, !27, !DIExpression(), debug-location !29
+    tCMPhir renamable $r5, $r11, 14, $noreg, implicit-def $cpsr, debug-location !50
+    tBcc %bb.5, 1, killed $cpsr, debug-location !50
+
+  bb.8.for.end16:
+    successors: %bb.9(0x50000000), %bb.13(0x30000000)
+    liveins: $lr, $r9, $r12
+
+    DBG_VALUE $lr, $noreg, !30, !DIExpression(), debug-location !79
+    DBG_VALUE $r9, $noreg, !35, !DIExpression(), debug-location !79
+    DBG_VALUE 0, $noreg, !36, !DIExpression(), debug-location !79
+    DBG_VALUE 0, $noreg, !38, !DIExpression(), debug-location !79
+    DBG_VALUE 0, $noreg, !42, !DIExpression(), debug-location !79
+    DBG_VALUE 0, $noreg, !41, !DIExpression(), debug-location !79
+    DBG_VALUE 0, $noreg, !40, !DIExpression(), debug-location !79
+    DBG_VALUE $noreg, $noreg, !37, !DIExpression(), debug-location !79
+    t2CMPri renamable $lr, 1, 14, $noreg, implicit-def $cpsr, debug-location !81
+    tBcc %bb.13, 11, killed $cpsr, debug-location !81
+
+  bb.9.for.body.i57.preheader:
+    successors: %bb.10(0x80000000)
+    liveins: $lr, $r9, $r12
+
+    renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg
+    renamable $r1 = IMPLICIT_DEF
+    t2DoLoopStart renamable $lr, debug-location !81
+
+  bb.10.for.body.i57:
+    successors: %bb.10(0x7c000000), %bb.11(0x04000000)
+    liveins: $lr, $r0, $r1, $r9, $r12
+
+    DBG_VALUE $r0, $noreg, !42, !DIExpression(), debug-location !79
+    DBG_VALUE $noreg, $noreg, !41, !DIExpression(), debug-location !79
+    DBG_VALUE $r1, $noreg, !37, !DIExpression(), debug-location !79
+    renamable $r2, renamable $r9 = t2LDR_POST killed renamable $r9, 4, 14, $noreg, debug-location !82 :: (load 4 from %ir.lsr.iv1)
+    DBG_VALUE $r2, $noreg, !39, !DIExpression(), debug-location !79
+    renamable $lr = t2LoopDec killed renamable $lr, 1, debug-location !81
+    renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14, $noreg, debug-location !83
+    DBG_VALUE $r1, $noreg, !37, !DIExpression(), debug-location !79
+    tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr, debug-location !84
+    renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr, debug-location !84
+    tCMPi8 killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr, debug-location !85
+    renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr, debug-location !85
+    tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr, debug-location !85
+    renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg, debug-location !85
+    t2IT 12, 8, implicit-def $itstate, debug-location !85
+    $r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate, debug-location !85
+    DBG_VALUE $noreg, $noreg, !41, !DIExpression(DW_OP_plus_uconst, 1, DW_OP_stack_value), debug-location !79
+    DBG_VALUE $r1, $noreg, !37, !DIExpression(), debug-location !79
+    renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg, debug-location !85
+    DBG_VALUE $r0, $noreg, !42, !DIExpression(), debug-location !79
+    t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr, debug-location !81
+    tB %bb.11, 14, $noreg, debug-location !81
+
+  bb.11.c.exit59.loopexit:
+    successors: %bb.14(0x80000000)
+    liveins: $r0, $r12
+
+    renamable $r5 = tSXTH killed renamable $r0, 14, $noreg, debug-location !89
+    tB %bb.14, 14, $noreg
+
+  bb.12.c.exit.thread:
+    successors: %bb.14(0x80000000)
+
+    DBG_VALUE $noreg, $noreg, !42, !DIExpression(), debug-location !43
+    DBG_VALUE $noreg, $noreg, !23, !DIExpression(), debug-location !29
+    $r0, dead $cpsr = tMOVi8 0, 14, $noreg, debug-location !49
+    renamable $r5, dead $cpsr = tMOVi8 0, 14, $noreg
+    tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0, debug-location !49
+    $r12 = tMOVr killed $r0, 14, $noreg, debug-location !49
+    DBG_VALUE 0, $noreg, !27, !DIExpression(), debug-location !29
+    tB %bb.14, 14, $noreg
+
+  bb.13:
+    successors: %bb.14(0x80000000)
+    liveins: $r12
+
+    renamable $r5, dead $cpsr = tMOVi8 0, 14, $noreg
+
+  bb.14.c.exit59:
+    liveins: $r5, $r12
+
+    DBG_VALUE $noreg, $noreg, !42, !DIExpression(), debug-location !79
+    DBG_VALUE $noreg, $noreg, !22, !DIExpression(), debug-location !29
+    $r0 = tMOVr killed $r5, 14, $noreg, debug-location !90
+    $r1 = tMOVr killed $r12, 14, $noreg, debug-location !90
+    $sp = tADDspi $sp, 1, 14, $noreg, debug-location !90
+    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r10, def $r11, debug-location !90
+    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $lr, debug-location !90
+    tTAILJMPdND @crc16, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1, debug-location !90
+
+...