diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -224,7 +224,7 @@
 // VE Multiclasses for common instruction formats
 //===----------------------------------------------------------------------===//
 
-multiclass RMm<string opcStr, bits<8>opc,
+multiclass RMm<string opcStr, bits<8>opc, SDNode OpNode,
                RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
   def rri : RM<
     opc, (outs RC:$sx), (ins RC:$sy, RC:$sz, immOp2:$imm32),
@@ -235,7 +235,8 @@
   }
   def rzi : RM<
     opc, (outs RC:$sx), (ins RC:$sz, immOp2:$imm32),
-    !strconcat(opcStr, " $sx, ${imm32}(${sz})")> {
+    !strconcat(opcStr, " $sx, ${imm32}(${sz})"),
+    [(set Ty:$sx, (OpNode Ty:$sz, (Ty simm32:$imm32)))]> {
     let cy = 0;
     let sy = 0;
     let cz = 1;
@@ -263,14 +264,6 @@
            { let cy = 1; let cz = 1; let hasSideEffects = 0; }
 }
 
-multiclass RRNDmrr<string opcStr, bits<8>opc,
-                 RegisterClass RCo, ValueType Tyo,
-                 RegisterClass RCi, ValueType Tyi> {
-  def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
-              !strconcat(opcStr, " $sx, $sy, $sz")>
-           { let cy = 1; let cz = 1; let hasSideEffects = 0; }
-}
-
 multiclass RRmri<string opcStr, bits<8>opc, SDNode OpNode,
                  RegisterClass RCo, ValueType Tyo,
                  RegisterClass RCi, ValueType Tyi, Operand immOp> {
@@ -340,7 +333,7 @@
 multiclass RRNDm<string opcStr, bits<8>opc,
                  RegisterClass RC, ValueType Ty,
                  Operand immOp, Operand immOp2> :
-  RRNDmrr<opcStr, opc, RC, Ty, RC, Ty>,
+  RRmrr<opcStr, opc, null_frag, RC, Ty, RC, Ty>,
   //RRNDmir<opcStr, opc, RC, Ty, RC, Ty, immOp>,
   //RRNDmiz<opcStr, opc, RC, Ty, RC, Ty, immOp>,
   RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
@@ -419,12 +412,12 @@
 
 // LEA and LEASL instruction (load 32 bit imm to low or high part)
 let cx = 0 in
-defm LEA : RMm<"lea", 0x06, I64, i64, simm7Op64, simm32Op64>;
+defm LEA : RMm<"lea", 0x06, null_frag, I64, i64, simm7Op64, simm32Op64>;
 let cx = 1 in
-defm LEASL : RMm<"lea.sl", 0x06, I64, i64, simm7Op64, simm32Op64>;
+defm LEASL : RMm<"lea.sl", 0x06, null_frag, I64, i64, simm7Op64, simm32Op64>;
 let isCodeGenOnly = 1 in {
 let cx = 0 in
-defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>;
+defm LEA32 : RMm<"lea", 0x06, null_frag, I32, i32, simm7Op32, simm32Op32>;
 }