diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -10,44 +10,6 @@ // //===----------------------------------------------------------------------===// -class ExpandImmAsmOp : AsmOperandClass { - let Name = !strconcat("ExpandImm", shift); - let PredicateMethod = !strconcat("isExpImm<", shift, ">"); - let RenderMethod = "addImmOperands"; -} -class InvertedExpandImmAsmOp : AsmOperandClass { - let Name = !strconcat("InvertedExpandImm", shift, "_", size); - let PredicateMethod = !strconcat("isInvertedExpImm<", shift, ",", size, ">"); - let RenderMethod = "addImmOperands"; -} - -class ExpandImm : Operand { - let ParserMatchClass = ExpandImmAsmOp; - let EncoderMethod = !strconcat("getExpandedImmOpValue<",shift,",false>"); - let DecoderMethod = !strconcat("DecodeExpandedImmOperand<",shift,">"); - let PrintMethod = "printExpandedImmOperand"; -} -class InvertedExpandImm : Operand { - let ParserMatchClass = InvertedExpandImmAsmOp; - let EncoderMethod = !strconcat("getExpandedImmOpValue<",shift,",true>"); - let PrintMethod = "printExpandedImmOperand"; - // No decoder method needed, because this operand type is only used - // by aliases (VAND and VORN) -} - -def expzero00 : ExpandImm<"0">; -def expzero08 : ExpandImm<"8">; -def expzero16 : ExpandImm<"16">; -def expzero24 : ExpandImm<"24">; - -def expzero00inv16 : InvertedExpandImm<"0", "16">; -def expzero08inv16 : InvertedExpandImm<"8", "16">; - -def expzero00inv32 : InvertedExpandImm<"0", "32">; -def expzero08inv32 : InvertedExpandImm<"8", "32">; -def expzero16inv32 : InvertedExpandImm<"16", "32">; -def expzero24inv32 : InvertedExpandImm<"24", "32">; - // VPT condition mask def vpt_mask : Operand { let PrintMethod = "printVPTMask"; @@ -1383,10 +1345,10 @@ defm : MVE_bit_op_with_inv; defm : MVE_bit_op_with_inv; -class MVE_bit_cmode cmode, dag inOps> +class MVE_bit_cmode : MVE_p<(outs MQPR:$Qd), inOps, NoItinerary, iname, suffix, "$Qd, $imm", vpred_n, "$Qd = $Qd_src"> { - bits<8> imm; + bits<12> imm; bits<4> Qd; let Inst{28} = imm{7}; @@ -1396,66 +1358,45 @@ let Inst{18-16} = imm{6-4}; let Inst{15-13} = Qd{2-0}; let Inst{12} = 0b0; - let Inst{11-8} = cmode; + let Inst{11} = halfword; + let Inst{10} = !if(halfword, 0, imm{10}); + let Inst{9} = imm{9}; + let Inst{8} = 0b1; let Inst{7-6} = 0b01; let Inst{4} = 0b1; let Inst{3-0} = imm{3-0}; } -class MVE_VORR cmode, ExpandImm imm_type> - : MVE_bit_cmode<"vorr", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> { +class MVE_VORR + : MVE_bit_cmode<"vorr", suffix, hw, (ins MQPR:$Qd_src, imm_type:$imm)> { let Inst{5} = 0b0; let validForTailPredication = 1; } -def MVE_VORRIZ0v4i32 : MVE_VORR<"i32", 0b0001, expzero00>; -def MVE_VORRIZ0v8i16 : MVE_VORR<"i16", 0b1001, expzero00>; -def MVE_VORRIZ8v4i32 : MVE_VORR<"i32", 0b0011, expzero08>; -def MVE_VORRIZ8v8i16 : MVE_VORR<"i16", 0b1011, expzero08>; -def MVE_VORRIZ16v4i32 : MVE_VORR<"i32", 0b0101, expzero16>; -def MVE_VORRIZ24v4i32 : MVE_VORR<"i32", 0b0111, expzero24>; - -def MVE_VORNIZ0v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm", - (ins MQPR:$Qd_src, expzero00inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>; -def MVE_VORNIZ0v8i16 : MVEAsmPseudo<"vorn${vp}.i16\t$Qd, $imm", - (ins MQPR:$Qd_src, expzero00inv16:$imm, vpred_n:$vp), (outs MQPR:$Qd)>; -def MVE_VORNIZ8v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm", - (ins MQPR:$Qd_src, expzero08inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>; -def MVE_VORNIZ8v8i16 : MVEAsmPseudo<"vorn${vp}.i16\t$Qd, $imm", - (ins MQPR:$Qd_src, expzero08inv16:$imm, vpred_n:$vp), (outs MQPR:$Qd)>; -def MVE_VORNIZ16v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm", - (ins MQPR:$Qd_src, expzero16inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>; -def MVE_VORNIZ24v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm", - (ins MQPR:$Qd_src, expzero24inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>; +def MVE_VORRimmi16 : MVE_VORR<"i16", 1, nImmSplatI16>; +def MVE_VORRimmi32 : MVE_VORR<"i32", 0, nImmSplatI32>; + +def MVE_VORNimmi16 : MVEInstAlias<"vorn${vp}.i16\t$Qd, $imm", + (MVE_VORRimmi16 MQPR:$Qd, nImmSplatNotI16:$imm, vpred_n:$vp), 0>; +def MVE_VORNimmi32 : MVEInstAlias<"vorn${vp}.i32\t$Qd, $imm", + (MVE_VORRimmi32 MQPR:$Qd, nImmSplatNotI32:$imm, vpred_n:$vp), 0>; def MVE_VMOV : MVEInstAlias<"vmov${vp}\t$Qd, $Qm", (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp)>; -class MVE_VBIC cmode, ExpandImm imm_type> - : MVE_bit_cmode<"vbic", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> { +class MVE_VBIC + : MVE_bit_cmode<"vbic", suffix, hw, (ins MQPR:$Qd_src, imm_type:$imm)> { let Inst{5} = 0b1; let validForTailPredication = 1; } -def MVE_VBICIZ0v4i32 : MVE_VBIC<"i32", 0b0001, expzero00>; -def MVE_VBICIZ0v8i16 : MVE_VBIC<"i16", 0b1001, expzero00>; -def MVE_VBICIZ8v4i32 : MVE_VBIC<"i32", 0b0011, expzero08>; -def MVE_VBICIZ8v8i16 : MVE_VBIC<"i16", 0b1011, expzero08>; -def MVE_VBICIZ16v4i32 : MVE_VBIC<"i32", 0b0101, expzero16>; -def MVE_VBICIZ24v4i32 : MVE_VBIC<"i32", 0b0111, expzero24>; - -def MVE_VANDIZ0v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm", - (ins MQPR:$Qda_src, expzero00inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>; -def MVE_VANDIZ0v8i16 : MVEAsmPseudo<"vand${vp}.i16\t$Qda, $imm", - (ins MQPR:$Qda_src, expzero00inv16:$imm, vpred_n:$vp), (outs MQPR:$Qda)>; -def MVE_VANDIZ8v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm", - (ins MQPR:$Qda_src, expzero08inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>; -def MVE_VANDIZ8v8i16 : MVEAsmPseudo<"vand${vp}.i16\t$Qda, $imm", - (ins MQPR:$Qda_src, expzero08inv16:$imm, vpred_n:$vp), (outs MQPR:$Qda)>; -def MVE_VANDIZ16v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm", - (ins MQPR:$Qda_src, expzero16inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>; -def MVE_VANDIZ24v4i32 : MVEAsmPseudo<"vand${vp}.i32\t$Qda, $imm", - (ins MQPR:$Qda_src, expzero24inv32:$imm, vpred_n:$vp), (outs MQPR:$Qda)>; +def MVE_VBICimmi16 : MVE_VBIC<"i16", 1, nImmSplatI16>; +def MVE_VBICimmi32 : MVE_VBIC<"i32", 0, nImmSplatI32>; + +def MVE_VANDimmi16 : MVEInstAlias<"vand${vp}.i16\t$Qd, $imm", + (MVE_VBICimmi16 MQPR:$Qd, nImmSplatNotI16:$imm, vpred_n:$vp), 0>; +def MVE_VANDimmi32 : MVEInstAlias<"vand${vp}.i32\t$Qd, $imm", + (MVE_VBICimmi32 MQPR:$Qd, nImmSplatNotI32:$imm, vpred_n:$vp), 0>; class MVE_VMOV_lane_direction { bit bit_20; diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8223,50 +8223,6 @@ } switch (Inst.getOpcode()) { - case ARM::MVE_VORNIZ0v4i32: - case ARM::MVE_VORNIZ0v8i16: - case ARM::MVE_VORNIZ8v4i32: - case ARM::MVE_VORNIZ8v8i16: - case ARM::MVE_VORNIZ16v4i32: - case ARM::MVE_VORNIZ24v4i32: - case ARM::MVE_VANDIZ0v4i32: - case ARM::MVE_VANDIZ0v8i16: - case ARM::MVE_VANDIZ8v4i32: - case ARM::MVE_VANDIZ8v8i16: - case ARM::MVE_VANDIZ16v4i32: - case ARM::MVE_VANDIZ24v4i32: { - unsigned Opcode; - bool imm16 = false; - switch(Inst.getOpcode()) { - case ARM::MVE_VORNIZ0v4i32: Opcode = ARM::MVE_VORRIZ0v4i32; break; - case ARM::MVE_VORNIZ0v8i16: Opcode = ARM::MVE_VORRIZ0v8i16; imm16 = true; break; - case ARM::MVE_VORNIZ8v4i32: Opcode = ARM::MVE_VORRIZ8v4i32; break; - case ARM::MVE_VORNIZ8v8i16: Opcode = ARM::MVE_VORRIZ8v8i16; imm16 = true; break; - case ARM::MVE_VORNIZ16v4i32: Opcode = ARM::MVE_VORRIZ16v4i32; break; - case ARM::MVE_VORNIZ24v4i32: Opcode = ARM::MVE_VORRIZ24v4i32; break; - case ARM::MVE_VANDIZ0v4i32: Opcode = ARM::MVE_VBICIZ0v4i32; break; - case ARM::MVE_VANDIZ0v8i16: Opcode = ARM::MVE_VBICIZ0v8i16; imm16 = true; break; - case ARM::MVE_VANDIZ8v4i32: Opcode = ARM::MVE_VBICIZ8v4i32; break; - case ARM::MVE_VANDIZ8v8i16: Opcode = ARM::MVE_VBICIZ8v8i16; imm16 = true; break; - case ARM::MVE_VANDIZ16v4i32: Opcode = ARM::MVE_VBICIZ16v4i32; break; - case ARM::MVE_VANDIZ24v4i32: Opcode = ARM::MVE_VBICIZ24v4i32; break; - default: llvm_unreachable("unexpected opcode"); - } - - MCInst TmpInst; - TmpInst.setOpcode(Opcode); - TmpInst.addOperand(Inst.getOperand(0)); - TmpInst.addOperand(Inst.getOperand(1)); - - // invert immediate - unsigned imm = ~Inst.getOperand(2).getImm() & (imm16 ? 0xffff : 0xffffffff); - TmpInst.addOperand(MCOperand::createImm(imm)); - - TmpInst.addOperand(Inst.getOperand(3)); - TmpInst.addOperand(Inst.getOperand(4)); - Inst = TmpInst; - return true; - } // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction. case ARM::LDRT_POST: case ARM::LDRBT_POST: { diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -538,10 +538,6 @@ static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -template -static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder); template static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, @@ -6395,16 +6391,6 @@ return S; } -template -static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val, - uint64_t Address, - const void *Decoder) { - Val <<= shift; - - Inst.addOperand(MCOperand::createImm(Val)); - return MCDisassembler::Success; -} - template static DecodeStatus DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -260,8 +260,6 @@ const MCSubtargetInfo &STI, raw_ostream &O); void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); - void printExpandedImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, raw_ostream &O); void printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O); private: diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp @@ -1669,15 +1669,6 @@ } } -void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum, - const MCSubtargetInfo &STI, - raw_ostream &O) { - uint32_t Val = MI->getOperand(OpNum).getImm(); - O << markup(""); -} - void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) { diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -413,14 +413,6 @@ unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; - template - unsigned getExpandedImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups, - const MCSubtargetInfo &STI) const { - static_assert(shift <= 32, "Shift count must be less than or equal to 32."); - const MCOperand MO = MI.getOperand(Op); - return (invert ? (MO.getImm() ^ 0xff) : MO.getImm()) >> shift; - } unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue, diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp --- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -62,12 +62,8 @@ case MVE_VADDi8: case MVE_VAND: case MVE_VBIC: - case MVE_VBICIZ0v4i32: - case MVE_VBICIZ0v8i16: - case MVE_VBICIZ16v4i32: - case MVE_VBICIZ24v4i32: - case MVE_VBICIZ8v4i32: - case MVE_VBICIZ8v8i16: + case MVE_VBICimmi16: + case MVE_VBICimmi32: case MVE_VBRSR16: case MVE_VBRSR32: case MVE_VBRSR8: @@ -296,12 +292,8 @@ case MVE_VNEGs8: case MVE_VORN: case MVE_VORR: - case MVE_VORRIZ0v4i32: - case MVE_VORRIZ0v8i16: - case MVE_VORRIZ16v4i32: - case MVE_VORRIZ24v4i32: - case MVE_VORRIZ8v4i32: - case MVE_VORRIZ8v8i16: + case MVE_VORRimmi16: + case MVE_VORRimmi32: case MVE_VPST: case MVE_VQABSs16: case MVE_VQABSs32: