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Differential D73171

[VE] setcc isel patterns
ClosedPublic

Authored by simoll on Jan 22 2020, 3:48 AM.

Details

Reviewers
arsenm
rengolin
craig.topper
k-ishizaka
Commits
rGdc69265eea88: [VE] setcc isel patterns
Summary

SETCC isel patterns and tests for i32/64 and fp32/64 comparison

Diff Detail

Event Timeline

simoll created this revision.Jan 22 2020, 3:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 22 2020, 3:48 AM
Herald added subscribers: llvm-commits, hiraditya, wdng. · View Herald Transcript
merge_guards_bot added a subscriber: merge_guards_bot.Jan 22 2020, 4:06 AM

Unit tests: pass. 62095 tests passed, 0 failed and 794 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B44564: Diff 239530.Jan 22 2020, 4:07 AM
simoll added a parent revision: D71338: [VE,#1] Scalar code generation.Jan 22 2020, 4:10 AM
arsenm added inline comments.Jan 22 2020, 5:24 AM
llvm/lib/Target/VE/VEInstrInfo.td
50–58

You can achieve this with something like:
def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;

which will also work with the GlobalISel emitter

llvm/test/CodeGen/VE/setcc.ll
11 ↗(On Diff #239530)

Enumerating all of the compare types is usually helpful

arsenm added inline comments.Jan 22 2020, 5:28 AM
llvm/test/CodeGen/VE/setcc.ll
11 ↗(On Diff #239530)

Actually these seem to be in the other test files, so I'm not sure what this one is for

simoll planned changes to this revision.Jan 22 2020, 6:19 AM
simoll marked 4 inline comments as done.
simoll added inline comments.
llvm/lib/Target/VE/VEInstrInfo.td
50–58

If we use PatFrags here TableGen will crash when a CCUIOp node is named (as in the patterns below). TableGen asserts that named nodes have only one tree.

llvm/test/CodeGen/VE/setcc.ll
11 ↗(On Diff #239530)

I'll remove the redundant test file.

simoll updated this revision to Diff 239568.Jan 22 2020, 6:31 AM
simoll marked an inline comment as done.
  • Rebased
  • Removed redundant test
arsenm accepted this revision.Jan 22 2020, 6:41 AM

LGTM

This revision is now accepted and ready to land.Jan 22 2020, 6:41 AM
merge_guards_bot added a comment.Jan 22 2020, 6:43 AM

Unit tests: pass. 62100 tests passed, 0 failed and 793 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B44586: Diff 239568.Jan 22 2020, 6:43 AM
Closed by commit rGdc69265eea88: [VE] setcc isel patterns (authored by kaz7, committed by simoll). · Explain WhyJan 22 2020, 6:53 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
2 lines
191 lines
test/
CodeGen/
VE/
187 lines
211 lines
187 lines
199 lines
121 lines
131 lines
121 lines
131 lines

Diff 239580

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Linesconst char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
case VEISD::RET_FLAG: case VEISD::RET_FLAG:
return "VEISD::RET_FLAG"; return "VEISD::RET_FLAG";
} }
return nullptr; return nullptr;
} }
EVT VETargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT VETargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
EVT VT) const { EVT VT) const {
return MVT::i64; return MVT::i32;
} }

llvm/lib/Target/VE/VEInstrInfo.td

Show All 31 Linesdef lomsbzero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0x80000000)
== 0; }]>; == 0; }]>;
def lozero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0xffffffff) def lozero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0xffffffff)
== 0; }]>; == 0; }]>;
def fplomsbzero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt() def fplomsbzero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt()
.getZExtValue() & 0x80000000) == 0; }]>; .getZExtValue() & 0x80000000) == 0; }]>;
def fplozero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt() def fplozero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt()
.getZExtValue() & 0xffffffff) == 0; }]>; .getZExtValue() & 0xffffffff) == 0; }]>;
def CCSIOp : PatLeaf<(cond), [{
switch (N->get()) {
default: return true;
case ISD::SETULT:
case ISD::SETULE:
case ISD::SETUGT:
case ISD::SETUGE: return false;
}
}]>;
def CCUIOp : PatLeaf<(cond), [{
switch (N->get()) {
default: return true;
case ISD::SETLT:
case ISD::SETLE:
case ISD::SETGT:
case ISD::SETGE: return false;
}
}]>;
arsenmUnsubmitted
Not Done
ReplyInline Actions

You can achieve this with something like:
def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ), (OtherVT SETEQ)]>;

which will also work with the GlobalISel emitter

arsenm: You can achieve this with something like: def COND_OEQ : PatFrags<(ops), [(OtherVT SETOEQ)…
simollAuthorUnsubmitted
Done
ReplyInline Actions

If we use PatFrags here TableGen will crash when a CCUIOp node is named (as in the patterns below). TableGen asserts that named nodes have only one tree.

simoll: If we use PatFrags here TableGen will crash when a CCUIOp node is named (as in the patterns…
def LOFP32 : SDNodeXForm<fpimm, [{ def LOFP32 : SDNodeXForm<fpimm, [{
// Get a integer immediate from fpimm // Get a integer immediate from fpimm
const APInt& imm = N->getValueAPF().bitcastToAPInt(); const APInt& imm = N->getValueAPF().bitcastToAPInt();
return CurDAG->getTargetConstant(Lo_32(imm.getZExtValue() & 0xffffffff), return CurDAG->getTargetConstant(Lo_32(imm.getZExtValue() & 0xffffffff),
SDLoc(N), MVT::i64); SDLoc(N), MVT::i64);
}]>; }]>;
def HIFP32 : SDNodeXForm<fpimm, [{ def HIFP32 : SDNodeXForm<fpimm, [{
Show All 9 Lines
}]>; }]>;
def HI32 : SDNodeXForm<imm, [{ def HI32 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits. // Transformation function: shift the immediate value down into the low bits.
return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()), return CurDAG->getTargetConstant(Hi_32(N->getZExtValue()),
SDLoc(N), MVT::i32); SDLoc(N), MVT::i32);
}]>; }]>;
def icond2cc : SDNodeXForm<cond, [{
VECC::CondCodes cc;
switch (N->get()) {
default: llvm_unreachable("Unknown integer condition code!");
case ISD::SETEQ: cc = VECC::CC_IEQ; break;
case ISD::SETNE: cc = VECC::CC_INE; break;
case ISD::SETLT: cc = VECC::CC_IL; break;
case ISD::SETGT: cc = VECC::CC_IG; break;
case ISD::SETLE: cc = VECC::CC_ILE; break;
case ISD::SETGE: cc = VECC::CC_IGE; break;
case ISD::SETULT: cc = VECC::CC_IL; break;
case ISD::SETULE: cc = VECC::CC_ILE; break;
case ISD::SETUGT: cc = VECC::CC_IG; break;
case ISD::SETUGE: cc = VECC::CC_IGE; break;
}
return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
}]>;
def fcond2cc : SDNodeXForm<cond, [{
VECC::CondCodes cc;
switch (N->get()) {
default: llvm_unreachable("Unknown float condition code!");
case ISD::SETFALSE: cc = VECC::CC_AF; break;
case ISD::SETEQ:
case ISD::SETOEQ: cc = VECC::CC_EQ; break;
case ISD::SETNE:
case ISD::SETONE: cc = VECC::CC_NE; break;
case ISD::SETLT:
case ISD::SETOLT: cc = VECC::CC_L; break;
case ISD::SETGT:
case ISD::SETOGT: cc = VECC::CC_G; break;
case ISD::SETLE:
case ISD::SETOLE: cc = VECC::CC_LE; break;
case ISD::SETGE:
case ISD::SETOGE: cc = VECC::CC_GE; break;
case ISD::SETO: cc = VECC::CC_NUM; break;
case ISD::SETUO: cc = VECC::CC_NAN; break;
case ISD::SETUEQ: cc = VECC::CC_EQNAN; break;
case ISD::SETUNE: cc = VECC::CC_NENAN; break;
case ISD::SETULT: cc = VECC::CC_LNAN; break;
case ISD::SETUGT: cc = VECC::CC_GNAN; break;
case ISD::SETULE: cc = VECC::CC_LENAN; break;
case ISD::SETUGE: cc = VECC::CC_GENAN; break;
case ISD::SETTRUE: cc = VECC::CC_AT; break;
}
return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
}]>;
// ASX format of memory address // ASX format of memory address
def MEMri : Operand<iPTR> { def MEMri : Operand<iPTR> {
let PrintMethod = "printMemASXOperand"; let PrintMethod = "printMemASXOperand";
let MIOperandInfo = (ops ptr_rc, i64imm); let MIOperandInfo = (ops ptr_rc, i64imm);
} }
// AS format of memory address // AS format of memory address
def MEMASri : Operand<iPTR> { def MEMASri : Operand<iPTR> {
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Linesmulticlass RRmrr<string opcStr, bits<8>opc, SDNode OpNode,
RegisterClass RCo, ValueType Tyo, RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi> { RegisterClass RCi, ValueType Tyi> {
def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz), def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
!strconcat(opcStr, " $sx, $sy, $sz"), !strconcat(opcStr, " $sx, $sy, $sz"),
[(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]> [(set Tyo:$sx, (OpNode Tyi:$sy, Tyi:$sz))]>
{ let cy = 1; let cz = 1; let hasSideEffects = 0; } { let cy = 1; let cz = 1; let hasSideEffects = 0; }
} }
multiclass RRNDmrr<string opcStr, bits<8>opc,
RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi> {
def rr : RR<opc, (outs RCo:$sx), (ins RCi:$sy, RCi:$sz),
!strconcat(opcStr, " $sx, $sy, $sz")>
{ let cy = 1; let cz = 1; let hasSideEffects = 0; }
}
multiclass RRmri<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRmri<string opcStr, bits<8>opc, SDNode OpNode,
RegisterClass RCo, ValueType Tyo, RegisterClass RCo, ValueType Tyo,
RegisterClass RCi, ValueType Tyi, Operand immOp> { RegisterClass RCi, ValueType Tyi, Operand immOp> {
// VE calculates (OpNode $sy, $sz), but llvm requires to have immediate // VE calculates (OpNode $sy, $sz), but llvm requires to have immediate
// in RHS, so we use following definition. // in RHS, so we use following definition.
def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy), def ri : RR<opc, (outs RCo:$sx), (ins RCi:$sz, immOp:$sy),
!strconcat(opcStr, " $sx, $sy, $sz"), !strconcat(opcStr, " $sx, $sy, $sz"),
[(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi simm7:$sy)))]> [(set Tyo:$sx, (OpNode Tyi:$sz, (Tyi simm7:$sy)))]>
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
multiclass RRm<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRm<string opcStr, bits<8>opc, SDNode OpNode,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> : RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> :
RRmrr<opcStr, opc, OpNode, RC, Ty, RC, Ty>, RRmrr<opcStr, opc, OpNode, RC, Ty, RC, Ty>,
RRmri<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>, RRmri<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>,
RRmiz<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>, RRmiz<opcStr, opc, OpNode, RC, Ty, RC, Ty, immOp>,
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>, RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>; RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
// Used by cmp instruction
// The order of operands are "$sx, $sy, $sz"
multiclass RRNDm<string opcStr, bits<8>opc,
RegisterClass RC, ValueType Ty,
Operand immOp, Operand immOp2> :
RRNDmrr<opcStr, opc, RC, Ty, RC, Ty>,
//RRNDmir<opcStr, opc, RC, Ty, RC, Ty, immOp>,
//RRNDmiz<opcStr, opc, RC, Ty, RC, Ty, immOp>,
RRNDmrm<opcStr, opc, RC, Ty, RC, Ty, immOp2>,
RRNDmim<opcStr, opc, RC, Ty, RC, Ty, immOp, immOp2>;
// Multiclass for RR type instructions // Multiclass for RR type instructions
// Used by sra, sla, sll, and similar instructions // Used by sra, sla, sll, and similar instructions
// The order of operands are "$sx, $sz, $sy" // The order of operands are "$sx, $sz, $sy"
multiclass RRIm<string opcStr, bits<8>opc, SDNode OpNode, multiclass RRIm<string opcStr, bits<8>opc, SDNode OpNode,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
def ri : RR< def ri : RR<
opc, (outs RC:$sx), (ins RC:$sz, immOp:$sy), opc, (outs RC:$sx), (ins RC:$sz, immOp:$sy),
!strconcat(opcStr, " $sx, $sz, $sy"), !strconcat(opcStr, " $sx, $sz, $sy"),
[(set Ty:$sx, (OpNode Ty:$sz, (i32 simm7:$sy)))]> { [(set Ty:$sx, (OpNode Ty:$sz, (i32 simm7:$sy)))]> {
let cy = 0; let cy = 0;
let cz = 1; let cz = 1;
let hasSideEffects = 0; let hasSideEffects = 0;
} }
} }
// Multiclass for RR type instructions
// Used by cmov instruction
let Constraints = "$sx = $sd", DisableEncoding = "$sd" in
multiclass RRCMOVm<string opcStr, bits<8>opc,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
def rm0 : RR<
opc, (outs I64:$sx), (ins CCOp:$cf, RC:$sy, immOp2:$sz, I64:$sd),
!strconcat(opcStr, " $sx, (${sz})0, $sy")> {
let cy = 1;
let cz = 0;
let sz{6} = 1;
let hasSideEffects = 0;
}
}
// Branch multiclass // Branch multiclass
let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
multiclass BCRm<string opcStr, string opcStrAt, bits<8> opc, multiclass BCRm<string opcStr, string opcStrAt, bits<8> opc,
RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
def rr : CF< def rr : CF<
opc, (outs), opc, (outs),
(ins CCOp:$cf, RC:$sy, RC:$sz, brtarget32:$imm32), (ins CCOp:$cf, RC:$sy, RC:$sz, brtarget32:$imm32),
!strconcat(opcStr, " $sy, $sz, $imm32")> { !strconcat(opcStr, " $sy, $sz, $imm32")> {
let cy = 1; let cy = 1;
let cz = 1; let cz = 1;
let hasSideEffects = 0; let hasSideEffects = 0;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// CMOV instructions
let cx = 0, cw = 0, cw2 = 0 in
defm CMOVL : RRCMOVm<"cmov.l.${cf}", 0x3B, I64, i64, simm7Op64, uimm6Op64>;
let cx = 0, cw = 1, cw2 = 0 in
defm CMOVW : RRCMOVm<"cmov.w.${cf}", 0x3B, I32, i32, simm7Op64, uimm6Op32>;
let cx = 0, cw = 0, cw2 = 1 in
defm CMOVD : RRCMOVm<"cmov.d.${cf}", 0x3B, I64, f64, simm7Op64, uimm6Op64>;
let cx = 0, cw = 1, cw2 = 1 in
defm CMOVS : RRCMOVm<"cmov.s.${cf}", 0x3B, F32, f32, simm7Op64, uimm6Op32>;
// LEA and LEASL instruction (load 32 bit imm to low or high part) // LEA and LEASL instruction (load 32 bit imm to low or high part)
let cx = 0 in let cx = 0 in
defm LEA : RMm<"lea", 0x06, I64, i64, simm7Op64, simm32Op64>; defm LEA : RMm<"lea", 0x06, I64, i64, simm7Op64, simm32Op64>;
let cx = 1 in let cx = 1 in
defm LEASL : RMm<"lea.sl", 0x06, I64, i64, simm7Op64, simm32Op64>; defm LEASL : RMm<"lea.sl", 0x06, I64, i64, simm7Op64, simm32Op64>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
let cx = 0 in let cx = 0 in
defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>; defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>;
} }
// 5.3.2.2. Fixed-Point Arithmetic Operation Instructions // 5.3.2.2. Fixed-Point Arithmetic Operation Instructions
// ADS instruction // ADS instruction
let cx = 0 in let cx = 0 in
defm ADS : RRm<"adds.w.sx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>; defm ADS : RRm<"adds.w.sx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>;
let cx = 1 in let cx = 1 in
defm ADSU : RRm<"adds.w.zx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>; defm ADSU : RRm<"adds.w.zx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>;
// ADX instruction // ADX instruction
let cx = 0 in let cx = 0 in
defm ADX : RRm<"adds.l", 0x59, add, I64, i64, simm7Op64, uimm6Op64>; defm ADX : RRm<"adds.l", 0x59, add, I64, i64, simm7Op64, uimm6Op64>;
// CMP instruction
let cx = 0 in
defm CMP : RRNDm<"cmpu.l", 0x55, I64, i64, simm7Op64, uimm6Op64>;
let cx = 1 in
defm CMPUW : RRNDm<"cmpu.w", 0x55, I32, i32, simm7Op32, uimm6Op32>;
// CPS instruction
let cx = 0 in
defm CPS : RRNDm<"cmps.w.sx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
let cx = 1 in
defm CPSU : RRNDm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>;
// CPX instruction
let cx = 0 in
defm CPX : RRNDm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>;
// 5.3.2.3. Logical Arithmetic Operation Instructions // 5.3.2.3. Logical Arithmetic Operation Instructions
let cx = 0 in { let cx = 0 in {
defm AND : RRm<"and", 0x44, and, I64, i64, simm7Op64, uimm6Op64>; defm AND : RRm<"and", 0x44, and, I64, i64, simm7Op64, uimm6Op64>;
defm OR : RRm<"or", 0x45, or, I64, i64, simm7Op64, uimm6Op64>; defm OR : RRm<"or", 0x45, or, I64, i64, simm7Op64, uimm6Op64>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
defm AND32 : RRm<"and", 0x44, and, I32, i32, simm7Op32, uimm6Op32>; defm AND32 : RRm<"and", 0x44, and, I32, i32, simm7Op32, uimm6Op32>;
defm OR32 : RRm<"or", 0x45, or, I32, i32, simm7Op32, uimm6Op32>; defm OR32 : RRm<"or", 0x45, or, I32, i32, simm7Op32, uimm6Op32>;
defm XOR32 : RRm<"xor", 0x46, xor, I32, i32, simm7Op32, uimm6Op32>;
} }
} }
// 5.3.2.4 Shift Instructions // 5.3.2.4 Shift Instructions
let cx = 0 in let cx = 0 in
defm SRAX : RRIm<"sra.l", 0x77, sra, I64, i64, simm7Op32, uimm6Op64>; defm SRAX : RRIm<"sra.l", 0x77, sra, I64, i64, simm7Op32, uimm6Op64>;
let cx = 0 in let cx = 0 in
defm SRA : RRIm<"sra.w.sx", 0x76, sra, I32, i32, simm7Op32, uimm6Op32>; defm SRA : RRIm<"sra.w.sx", 0x76, sra, I32, i32, simm7Op32, uimm6Op32>;
let cx = 0 in let cx = 0 in
defm SLL : RRIm<"sll", 0x65, shl, I64, i64, simm7Op32, uimm6Op64>; defm SLL : RRIm<"sll", 0x65, shl, I64, i64, simm7Op32, uimm6Op64>;
let cx = 0 in let cx = 0 in
defm SLA : RRIm<"sla.w.sx", 0x66, shl, I32, i32, simm7Op32, uimm6Op32>; defm SLA : RRIm<"sla.w.sx", 0x66, shl, I32, i32, simm7Op32, uimm6Op32>;
// FCP instruction
let cx = 0 in
defm FCP : RRNDm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>;
let cx = 1 in
defm FCPS : RRNDm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>;
// Load and Store instructions // Load and Store instructions
// As 1st step, only uses sz and imm32 to represent $addr // As 1st step, only uses sz and imm32 to represent $addr
let mayLoad = 1, hasSideEffects = 0 in { let mayLoad = 1, hasSideEffects = 0 in {
let cy = 0, sy = 0, cz = 1 in { let cy = 0, sy = 0, cz = 1 in {
let cx = 0 in let cx = 0 in
def LDSri : RM< def LDSri : RM<
0x01, (outs I64:$sx), (ins MEMri:$addr), 0x01, (outs I64:$sx), (ins MEMri:$addr),
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
def EXTEND_STACK : Pseudo<(outs), (ins), def EXTEND_STACK : Pseudo<(outs), (ins),
"# EXTEND STACK", "# EXTEND STACK",
[]>; []>;
let hasSideEffects = 0 in let hasSideEffects = 0 in
def EXTEND_STACK_GUARD : Pseudo<(outs), (ins), def EXTEND_STACK_GUARD : Pseudo<(outs), (ins),
"# EXTEND STACK GUARD", "# EXTEND STACK GUARD",
[]>; []>;
// SETCC pattern matches
//
// CMP %tmp, lhs, rhs ; compare lhs and rhs
// or %res, 0, (0)1 ; initialize by 0
// CMOV %res, (63)0, %tmp ; set 1 if %tmp is true
def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCSIOp:$cond)),
(EXTRACT_SUBREG
(CMOVLrm0 (icond2cc $cond),
(CPXrr i64:$LHS, i64:$RHS),
63,
(ORim1 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCUIOp:$cond)),
(EXTRACT_SUBREG
(CMOVLrm0 (icond2cc $cond),
(CMPrr i64:$LHS, i64:$RHS),
63,
(ORim1 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCSIOp:$cond)),
(EXTRACT_SUBREG
(CMOVWrm0 (icond2cc $cond),
(CPSrr i32:$LHS, i32:$RHS),
63,
(ORim1 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCUIOp:$cond)),
(EXTRACT_SUBREG
(CMOVWrm0 (icond2cc $cond),
(CMPUWrr i32:$LHS, i32:$RHS),
63,
(ORim1 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc f64:$LHS, f64:$RHS, cond:$cond)),
(EXTRACT_SUBREG
(CMOVDrm0 (fcond2cc $cond),
(FCPrr f64:$LHS, f64:$RHS),
63,
(ORim1 0, 0)), sub_i32)>;
def : Pat<(i32 (setcc f32:$LHS, f32:$RHS, cond:$cond)),
(EXTRACT_SUBREG
(CMOVSrm0 (fcond2cc $cond),
(FCPSrr f32:$LHS, f32:$RHS),
63,
(ORim1 0, 0)), sub_i32)>;
// Several special pattern matches to optimize code // Several special pattern matches to optimize code
def : Pat<(i32 (and i32:$lhs, 0xff)), def : Pat<(i32 (and i32:$lhs, 0xff)),
(AND32rm0 $lhs, 56)>; (AND32rm0 $lhs, 56)>;
def : Pat<(i32 (and i32:$lhs, 0xffff)), def : Pat<(i32 (and i32:$lhs, 0xffff)),
(AND32rm0 $lhs, 48)>; (AND32rm0 $lhs, 48)>;
def : Pat<(i32 (and i32:$lhs, 0xffffffff)), def : Pat<(i32 (and i32:$lhs, 0xffffffff)),
(AND32rm0 $lhs, 32)>; (AND32rm0 $lhs, 32)>;

llvm/test/CodeGen/VE/setccf32.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(float, float) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp false float %0, %1
ret i1 %3
}
define zeroext i1 @setccat(float, float) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp true float %0, %1
ret i1 %3
}
define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq float %0, %1
ret i1 %3
}
define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one float %0, %1
ret i1 %3
}
define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt float %0, %1
ret i1 %3
}
define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge float %0, %1
ret i1 %3
}
define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt float %0, %1
ret i1 %3
}
define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole float %0, %1
ret i1 %3
}
define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.num %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord float %0, %1
ret i1 %3
}
define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.nan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno float %0, %1
ret i1 %3
}
define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.eqnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq float %0, %1
ret i1 %3
}
define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.nenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une float %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.gtnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt float %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.genan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge float %0, %1
ret i1 %3
}
define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.ltnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult float %0, %1
ret i1 %3
}
define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.lenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule float %0, %1
ret i1 %3
}

llvm/test/CodeGen/VE/setccf32i.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(float, float) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp false float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccat(float, float) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp true float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoeq(float, float) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccone(float, float) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccogt(float, float) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoge(float, float) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccolt(float, float) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccole(float, float) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccord(float, float) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.num %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuno(float, float) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.s %s1, %s0, %s0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.nan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccueq(float, float) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.eqnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccune(float, float) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.nenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccugt(float, float) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.gtnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuge(float, float) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.genan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccult(float, float) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.ltnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult float %0, 0.0
ret i1 %3
}
define zeroext i1 @setccule(float, float) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: or %s1, 0, %s1
; CHECK-NEXT: fcmp.s %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.s.lenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule float %0, 0.0
ret i1 %3
}

llvm/test/CodeGen/VE/setccf64.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(double, double) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp false double %0, %1
ret i1 %3
}
define zeroext i1 @setccat(double, double) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp true double %0, %1
ret i1 %3
}
define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq double %0, %1
ret i1 %3
}
define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one double %0, %1
ret i1 %3
}
define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt double %0, %1
ret i1 %3
}
define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge double %0, %1
ret i1 %3
}
define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt double %0, %1
ret i1 %3
}
define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole double %0, %1
ret i1 %3
}
define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.num %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord double %0, %1
ret i1 %3
}
define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.nan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno double %0, %1
ret i1 %3
}
define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.eqnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq double %0, %1
ret i1 %3
}
define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.nenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une double %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.gtnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt double %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.genan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge double %0, %1
ret i1 %3
}
define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.ltnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult double %0, %1
ret i1 %3
}
define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.lenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule double %0, %1
ret i1 %3
}

llvm/test/CodeGen/VE/setccf64i.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setccaf(double, double) {
; CHECK-LABEL: setccaf:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp false double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccat(double, double) {
; CHECK-LABEL: setccat:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s0, 1, (0)1
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp true double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoeq(double, double) {
; CHECK-LABEL: setccoeq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oeq double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccone(double, double) {
; CHECK-LABEL: setccone:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp one double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccogt(double, double) {
; CHECK-LABEL: setccogt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ogt double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccoge(double, double) {
; CHECK-LABEL: setccoge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp oge double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccolt(double, double) {
; CHECK-LABEL: setccolt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp olt double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccole(double, double) {
; CHECK-LABEL: setccole:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ole double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccord(double, double) {
; CHECK-LABEL: setccord:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.num %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ord double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuno(double, double) {
; CHECK-LABEL: setccuno:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: fcmp.d %s1, %s0, %s0
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.nan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uno double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccueq(double, double) {
; CHECK-LABEL: setccueq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.eqnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ueq double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccune(double, double) {
; CHECK-LABEL: setccune:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.nenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp une double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccugt(double, double) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.gtnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ugt double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccuge(double, double) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.genan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp uge double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccult(double, double) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.ltnan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ult double %0, 0.0
ret i1 %3
}
define zeroext i1 @setccule(double, double) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: lea.sl %s1, 0
; CHECK-NEXT: fcmp.d %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.d.lenan %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = fcmp ule double %0, 0.0
ret i1 %3
}

llvm/test/CodeGen/VE/setcci32.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i32 %0, %1
ret i1 %3
}
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i32 %0, %1
ret i1 %3
}

llvm/test/CodeGen/VE/setcci32i.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i32, i32) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccne(i32, i32) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccugt(i32, i32) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccuge(i32, i32) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccult(i32, i32) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccule(i32, i32) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.w %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccsgt(i32, i32) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccsge(i32, i32) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccslt(i32, i32) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i32 %0, 12
ret i1 %3
}
define zeroext i1 @setccsle(i32, i32) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i32 %0, 12
ret i1 %3
}

llvm/test/CodeGen/VE/setcci64.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.ge %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i64 %0, %1
ret i1 %3
}
define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.le %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i64 %0, %1
ret i1 %3
}

llvm/test/CodeGen/VE/setcci64i.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define zeroext i1 @setcceq(i64, i64) {
; CHECK-LABEL: setcceq:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp eq i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccne(i64, i64) {
; CHECK-LABEL: setccne:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.ne %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ne i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccugt(i64, i64) {
; CHECK-LABEL: setccugt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ugt i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccuge(i64, i64) {
; CHECK-LABEL: setccuge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp uge i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccult(i64, i64) {
; CHECK-LABEL: setccult:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ult i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccule(i64, i64) {
; CHECK-LABEL: setccule:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmpu.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp ule i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccsgt(i64, i64) {
; CHECK-LABEL: setccsgt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sgt i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccsge(i64, i64) {
; CHECK-LABEL: setccsge:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 11, (0)1
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sge i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccslt(i64, i64) {
; CHECK-LABEL: setccslt:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 12, (0)1
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp slt i64 %0, 12
ret i1 %3
}
define zeroext i1 @setccsle(i64, i64) {
; CHECK-LABEL: setccsle:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: or %s1, 13, (0)1
; CHECK-NEXT: cmps.l %s1, %s0, %s1
; CHECK-NEXT: or %s0, 0, (0)1
; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: or %s11, 0, %s9
%3 = icmp sle i64 %0, 12
ret i1 %3
}