diff --git a/llvm/lib/Target/VE/VECallingConv.td b/llvm/lib/Target/VE/VECallingConv.td --- a/llvm/lib/Target/VE/VECallingConv.td +++ b/llvm/lib/Target/VE/VECallingConv.td @@ -17,14 +17,40 @@ def CC_VE : CallingConv<[ // All arguments get passed in generic registers if there is space. + // Promote i1/i8/i16 arguments to i32. + CCIfType<[i1, i8, i16], CCPromoteToType>, + + // bool, char, int, enum, long --> generic integer 32 bit registers + CCIfType<[i32], CCAssignToRegWithShadow< + [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7], + [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, + + // float --> generic floating point 32 bit registers + CCIfType<[f32], CCAssignToRegWithShadow< + [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7], + [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, + // long long/double --> generic 64 bit registers - CCIfType<[i64], + CCIfType<[i64, f64], CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, ]>; def RetCC_VE : CallingConv<[ + // Promote i1/i8/i16 arguments to i32. + CCIfType<[i1, i8, i16], CCPromoteToType>, + + // bool, char, int, enum, long --> generic integer 32 bit registers + CCIfType<[i32], CCAssignToRegWithShadow< + [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7], + [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, + + // float --> generic floating point 32 bit registers + CCIfType<[f32], CCAssignToRegWithShadow< + [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7], + [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, + // long long/double --> generic 64 bit registers - CCIfType<[i64], + CCIfType<[i64, f64], CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, ]>; diff --git a/llvm/lib/Target/VE/VEISelLowering.h b/llvm/lib/Target/VE/VEISelLowering.h --- a/llvm/lib/Target/VE/VEISelLowering.h +++ b/llvm/lib/Target/VE/VEISelLowering.h @@ -56,6 +56,9 @@ const SmallVectorImpl &Outs, const SmallVectorImpl &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override; + + bool isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const override; }; } // namespace llvm diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -89,6 +89,24 @@ llvm_unreachable("Unknown loc info!"); } + // The custom bit on an i32 return value indicates that it should be passed + // in the high bits of the register. + if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { + OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, + DAG.getConstant(32, DL, MVT::i32)); + + // The next value may go in the low bits of the same register. + // Handle both at once. + if (i + 1 < RVLocs.size() && + RVLocs[i + 1].getLocReg() == VA.getLocReg()) { + SDValue NV = + DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i + 1]); + OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); + // Skip the next value, it's already done. + ++i; + } + } + Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); // Guarantee that all emitted copies are stuck together with flags. @@ -136,8 +154,10 @@ MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); - assert((VA.getValVT() == MVT::i64) && - "TODO implement other argument types than i64"); + // Get the high bits for i32 struct elements. + if (VA.getValVT() == MVT::i32 && VA.needsCustom()) + Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, + DAG.getConstant(32, DL, MVT::i32)); // The caller promoted the argument, so insert an Assert?ext SDNode so we // won't promote the value again in this function. @@ -193,6 +213,14 @@ // TargetLowering Implementation //===----------------------------------------------------------------------===// +/// isFPImmLegal - Returns true if the target can instruction select the +/// specified FP immediate natively. If false, the legalizer will +/// materialize the FP immediate as a load from a constant pool. +bool VETargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, + bool ForCodeSize) const { + return VT == MVT::f32 || VT == MVT::f64; +} + VETargetLowering::VETargetLowering(const TargetMachine &TM, const VESubtarget &STI) : TargetLowering(TM), Subtarget(&STI) { @@ -204,8 +232,17 @@ setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); + // VE doesn't have instructions for fp<->uint, so expand them by llvm + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64 + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64 + setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + // Set up the register classes. + addRegisterClass(MVT::i32, &VE::I32RegClass); addRegisterClass(MVT::i64, &VE::I64RegClass); + addRegisterClass(MVT::f32, &VE::F32RegClass); + addRegisterClass(MVT::f64, &VE::I64RegClass); setStackPointerRegisterToSaveRestore(VE::SX11); diff --git a/llvm/lib/Target/VE/VEInstrFormats.td b/llvm/lib/Target/VE/VEInstrFormats.td --- a/llvm/lib/Target/VE/VEInstrFormats.td +++ b/llvm/lib/Target/VE/VEInstrFormats.td @@ -44,8 +44,8 @@ let Inst{63-32} = imm32; } -class RRopVal, dag outs, dag ins, string asmstr> - : RM { +class RRopVal, dag outs, dag ins, string asmstr, list pattern=[]> + : RM { bits<1> cw = 0; bits<1> cw2 = 0; bits<4> cfw = 0; diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -38,12 +38,18 @@ : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI(), Subtarget(ST) {} +static bool IsAliasOfSX(Register Reg) { + return VE::I8RegClass.contains(Reg) || VE::I16RegClass.contains(Reg) || + VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || + VE::F32RegClass.contains(Reg); +} + void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const { - if (VE::I64RegClass.contains(SrcReg) && VE::I64RegClass.contains(DestReg)) { + if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { BuildMI(MBB, I, DL, get(VE::ORri), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) .addImm(0); diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -32,6 +32,24 @@ == 0; }]>; def lozero : PatLeaf<(imm), [{ return (N->getZExtValue() & 0xffffffff) == 0; }]>; +def fplomsbzero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt() + .getZExtValue() & 0x80000000) == 0; }]>; +def fplozero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt() + .getZExtValue() & 0xffffffff) == 0; }]>; + +def LOFP32 : SDNodeXFormgetValueAPF().bitcastToAPInt(); + return CurDAG->getTargetConstant(Lo_32(imm.getZExtValue() & 0xffffffff), + SDLoc(N), MVT::i64); +}]>; + +def HIFP32 : SDNodeXFormgetValueAPF().bitcastToAPInt(); + return CurDAG->getTargetConstant(Hi_32(imm.getZExtValue()), + SDLoc(N), MVT::i64); +}]>; def LO32 : SDNodeXFormgetTargetConstant(Lo_32(N->getZExtValue()), @@ -61,14 +79,26 @@ let EncoderMethod = "getBranchTarget32OpValue"; } +def simm7Op32 : Operand { + let DecoderMethod = "DecodeSIMM7"; +} + def simm7Op64 : Operand { let DecoderMethod = "DecodeSIMM7"; } +def simm32Op32 : Operand { + let DecoderMethod = "DecodeSIMM32"; +} + def simm32Op64 : Operand { let DecoderMethod = "DecodeSIMM32"; } +def uimm6Op32 : Operand { + let DecoderMethod = "DecodeUIMM6"; +} + def uimm6Op64 : Operand { let DecoderMethod = "DecodeUIMM6"; } @@ -194,6 +224,12 @@ // it fails to infer from a pattern. let hasSideEffects = 0; } + def rm1 : RR { + let cy = 1; + let cz = 0; + let hasSideEffects = 0; + } } multiclass RRNDmimopc, @@ -219,6 +255,21 @@ RRNDmrm, RRNDmim; +// Multiclass for RR type instructions +// Used by sra, sla, sll, and similar instructions +// The order of operands are "$sx, $sz, $sy" + +multiclass RRImopc, + RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { + def ri : RR< + opc, (outs RC:$sx), (ins RC:$sz, immOp:$sy), + !strconcat(opcStr, " $sx, $sz, $sy")> { + let cy = 0; + let cz = 1; + let hasSideEffects = 0; + } +} + // Branch multiclass let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in multiclass BCRm opc, @@ -233,7 +284,6 @@ } } - //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -243,9 +293,21 @@ defm LEA : RMm<"lea", 0x06, I64, i64, simm7Op64, simm32Op64>; let cx = 1 in defm LEASL : RMm<"lea.sl", 0x06, I64, i64, simm7Op64, simm32Op64>; +let isCodeGenOnly = 1 in { +let cx = 0 in +defm LEA32 : RMm<"lea", 0x06, I32, i32, simm7Op32, simm32Op32>; +} + // 5.3.2.2. Fixed-Point Arithmetic Operation Instructions +// ADS instruction +let cx = 0 in +defm ADS : RRm<"adds.w.sx", 0x4A, I32, i32, simm7Op32, uimm6Op32>; +let cx = 1 in +defm ADSU : RRm<"adds.w.zx", 0x4A, I32, i32, simm7Op32, uimm6Op32>; + + // ADX instruction let cx = 0 in defm ADX : RRm<"adds.l", 0x59, I64, i64, simm7Op64, uimm6Op64>; @@ -255,8 +317,26 @@ let cx = 0 in { defm AND : RRm<"and", 0x44, I64, i64, simm7Op64, uimm6Op64>; defm OR : RRm<"or", 0x45, I64, i64, simm7Op64, uimm6Op64>; + let isCodeGenOnly = 1 in { + defm AND32 : RRm<"and", 0x44, I32, i32, simm7Op32, uimm6Op32>; + defm OR32 : RRm<"or", 0x45, I32, i32, simm7Op32, uimm6Op32>; + } } + +// 5.3.2.4 Shift Instructions + +let cx = 0 in +defm SRAX : RRIm<"sra.l", 0x77, I64, i64, simm7Op32, uimm6Op64>; +let cx = 0 in +defm SRA : RRIm<"sra.w.sx", 0x76, I32, i32, simm7Op32, uimm6Op32>; + +let cx = 0 in +defm SLL : RRIm<"sll", 0x65, I64, i64, simm7Op32, uimm6Op64>; +let cx = 0 in +defm SLA : RRIm<"sla.w.sx", 0x66, I32, i32, simm7Op32, uimm6Op32>; + + // Load and Store instructions // As 1st step, only uses sz and imm32 to represent $addr let mayLoad = 1, hasSideEffects = 0 in { @@ -307,8 +387,10 @@ //===----------------------------------------------------------------------===// // Small immediates. +def : Pat<(i32 simm7:$val), (OR32im1 imm:$val, 0)>; def : Pat<(i64 simm7:$val), (ORim1 imm:$val, 0)>; // Medium immediates. +def : Pat<(i32 simm32:$val), (LEA32zzi imm:$val)>; def : Pat<(i64 simm32:$val), (LEAzzi imm:$val)>; def : Pat<(i64 uimm32:$val), (ANDrm0 (LEAzzi imm:$val), 32)>; // Arbitrary immediates. @@ -320,6 +402,64 @@ (LEASLrzi (ANDrm0 (LEAzzi (LO32 imm:$val)), 32), (HI32 imm:$val))>; +// floating point +def : Pat<(f32 fpimm:$val), + (COPY_TO_REGCLASS (LEASLzzi (LOFP32 $val)), F32)>; +def : Pat<(f64 fplozero:$val), + (LEASLzzi (HIFP32 $val))>; +def : Pat<(f64 fplomsbzero:$val), + (LEASLrzi (LEAzzi (LOFP32 $val)), (HIFP32 $val))>; +def : Pat<(f64 fpimm:$val), + (LEASLrzi (ANDrm0 (LEAzzi (LOFP32 $val)), 32), + (HIFP32 $val))>; + +// The same integer registers are used for i32 and i64 values. +// When registers hold i32 values, the high bits are unused. + +// Cast to i1 +def : Pat<(sext_inreg I32:$src, i1), + (SRAri (SLAri $src, 31), 31)>; +def : Pat<(sext_inreg I64:$src, i1), + (SRAXri (SLLri $src, 63), 63)>; + +// Cast to i8 +def : Pat<(sext_inreg I32:$src, i8), + (SRAri (SLAri $src, 24), 24)>; +def : Pat<(sext_inreg I64:$src, i8), + (SRAXri (SLLri $src, 56), 56)>; +def : Pat<(sext_inreg (i32 (trunc i64:$src)), i8), + (EXTRACT_SUBREG (SRAXri (SLLri $src, 56), 56), sub_i32)>; +def : Pat<(and (trunc i64:$src), 0xff), + (AND32rm0 (EXTRACT_SUBREG $src, sub_i32), 56)>; + +// Cast to i16 +def : Pat<(sext_inreg I32:$src, i16), + (SRAri (SLAri $src, 16), 16)>; +def : Pat<(sext_inreg I64:$src, i16), + (SRAXri (SLLri $src, 48), 48)>; +def : Pat<(sext_inreg (i32 (trunc i64:$src)), i16), + (EXTRACT_SUBREG (SRAXri (SLLri $src, 48), 48), sub_i32)>; +def : Pat<(and (trunc i64:$src), 0xffff), + (AND32rm0 (EXTRACT_SUBREG $src, sub_i32), 48)>; + +// Cast to i32 +def : Pat<(i32 (trunc i64:$src)), + (ADSrm1 (EXTRACT_SUBREG $src, sub_i32), 0)>; + +// Cast to i64 +def : Pat<(sext_inreg I64:$src, i32), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (ADSrm1 (EXTRACT_SUBREG $src, sub_i32), 0), sub_i32)>; +def : Pat<(i64 (sext i32:$sy)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADSrm1 $sy, 0), sub_i32)>; +def : Pat<(i64 (zext i32:$sy)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADSUrm1 $sy, 0), sub_i32)>; + +def : Pat<(i64 (anyext i32:$sy)), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $sy, sub_i32)>; + + + //===----------------------------------------------------------------------===// // Pseudo Instructions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/VE/VERegisterInfo.cpp b/llvm/lib/Target/VE/VERegisterInfo.cpp --- a/llvm/lib/Target/VE/VERegisterInfo.cpp +++ b/llvm/lib/Target/VE/VERegisterInfo.cpp @@ -48,21 +48,29 @@ BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - Reserved.set(VE::SX8); // stack limit - Reserved.set(VE::SX9); // frame pointer - Reserved.set(VE::SX10); // link register (return address) - Reserved.set(VE::SX11); // stack pointer - Reserved.set(VE::SX12); // outer register - Reserved.set(VE::SX13); // id register for dynamic linker - - Reserved.set(VE::SX14); // thread pointer - Reserved.set(VE::SX15); // global offset table register - Reserved.set(VE::SX16); // procedure linkage table register - Reserved.set(VE::SX17); // linkage-area register - - // sx18-sx33 are callee-saved registers - // sx34-sx63 are temporary registers + const Register ReservedRegs[] = { + VE::SX8, // Stack limit + VE::SX9, // Frame pointer + VE::SX10, // Link register (return address) + VE::SX11, // Stack pointer + + // FIXME: maybe not need to be reserved + VE::SX12, // Outer register + VE::SX13, // Id register for dynamic linker + + VE::SX14, // Thread pointer + VE::SX15, // Global offset table register + VE::SX16, // Procedure linkage table register + VE::SX17, // Linkage-area register + // sx18-sx33 are callee-saved registers + // sx34-sx63 are temporary registers + }; + + for (auto R : ReservedRegs) + for (MCRegAliasIterator ItAlias(R, this, true); ItAlias.isValid(); + ++ItAlias) + Reserved.set(*ItAlias); return Reserved; } diff --git a/llvm/lib/Target/VE/VERegisterInfo.td b/llvm/lib/Target/VE/VERegisterInfo.td --- a/llvm/lib/Target/VE/VERegisterInfo.td +++ b/llvm/lib/Target/VE/VERegisterInfo.td @@ -16,6 +16,13 @@ let Namespace = "VE"; } +let Namespace = "VE" in { + def sub_i8 : SubRegIndex<8, 56>; // Low 8 bit (56..63) + def sub_i16 : SubRegIndex<16, 48>; // Low 16 bit (48..63) + def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63) + def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31) +} + // Registers are identified with 7-bit ID numbers. // R - 64-bit integer or floating-point registers class R Enc, string n, list subregs = [], @@ -24,14 +31,53 @@ let Aliases = aliases; } +// Generic integer registers - 8 bits wide +foreach I = 0-63 in + def SB#I : R, DwarfRegNum<[I]>; + +// Generic integer registers - 16 bits wide +let SubRegIndices = [sub_i8] in +foreach I = 0-63 in + def SH#I : R("SB"#I)]>, DwarfRegNum<[I]>; + +// Generic integer registers - 32 bits wide +let SubRegIndices = [sub_i16] in +foreach I = 0-63 in + def SW#I : R("SH"#I)]>, DwarfRegNum<[I]>; + +// Generic floating point registers - 32 bits wide +// NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation +// problem. +foreach I = 0-63 in + def SF#I : R("SW"#I)]>, DwarfRegNum<[I]>; + // Generic integer registers - 64 bits wide +let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in foreach I = 0-63 in - def SX#I : R, + def SX#I : R("SW"#I), !cast("SF"#I)]>, DwarfRegNum<[I]>; // Register classes. // // The register order is defined in terms of the preferred // allocation order. -def I64 : RegisterClass<"VE", [i64], 64, - (sequence "SX%u", 0, 63)>; +def I8 : RegisterClass<"VE", [i8], 8, + (add (sequence "SB%u", 0, 7), + (sequence "SB%u", 34, 63), + (sequence "SB%u", 8, 33))>; +def I16 : RegisterClass<"VE", [i16], 16, + (add (sequence "SH%u", 0, 7), + (sequence "SH%u", 34, 63), + (sequence "SH%u", 8, 33))>; +def I32 : RegisterClass<"VE", [i32], 32, + (add (sequence "SW%u", 0, 7), + (sequence "SW%u", 34, 63), + (sequence "SW%u", 8, 33))>; +def I64 : RegisterClass<"VE", [i64, f64], 64, + (add (sequence "SX%u", 0, 7), + (sequence "SX%u", 34, 63), + (sequence "SX%u", 8, 33))>; +def F32 : RegisterClass<"VE", [f32], 32, + (add (sequence "SF%u", 0, 7), + (sequence "SF%u", 34, 63), + (sequence "SF%u", 8, 33))>; diff --git a/llvm/test/CodeGen/VE/constants.ll b/llvm/test/CodeGen/VE/constants.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/VE/constants.ll @@ -0,0 +1,355 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define i8 @p0i8() { +; CHECK-LABEL: p0i8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 0 +} + +define signext i8 @p0si8() { +; CHECK-LABEL: p0si8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 0 +} + +define zeroext i8 @p0zi8() { +; CHECK-LABEL: p0zi8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 0 +} + +define i8 @p128i8() { +; CHECK-LABEL: p128i8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 128 +} + +define signext i8 @p128si8() { +; CHECK-LABEL: p128si8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 128 +} + +define zeroext i8 @p128zi8() { +; CHECK-LABEL: p128zi8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 128 +} + +define i8 @p256i8() { +; CHECK-LABEL: p256i8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 256 +} + +define signext i8 @p256si8() { +; CHECK-LABEL: p256si8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 256 +} + +define zeroext i8 @p256zi8() { +; CHECK-LABEL: p256zi8: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i8 256 +} + +define i16 @p0i16() { +; CHECK-LABEL: p0i16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i16 0 +} + +define signext i16 @p0si16() { +; CHECK-LABEL: p0si16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i16 0 +} + +define zeroext i16 @p0zi16() { +; CHECK-LABEL: p0zi16: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i16 0 +} + +define i32 @p0i32() { +; CHECK-LABEL: p0i32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i32 0 +} + +define signext i32 @p0si32() { +; CHECK-LABEL: p0si32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i32 0 +} + +define zeroext i32 @p0zi32() { +; CHECK-LABEL: p0zi32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i32 0 +} + +define i32 @p128i32() { +; CHECK-LABEL: p128i32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i32 128 +} + +define signext i32 @p128si32() { +; CHECK-LABEL: p128si32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i32 128 +} + +define zeroext i32 @p128zi32() { +; CHECK-LABEL: p128zi32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i32 128 +} + +define i64 @p0i64() { +; CHECK-LABEL: p0i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 0 +} + +define signext i64 @p0si64() { +; CHECK-LABEL: p0si64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 0 +} + +define zeroext i64 @p0zi64() { +; CHECK-LABEL: p0zi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 0 +} + +define i64 @p128i64() { +; CHECK-LABEL: p128i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 128 +} + +define signext i64 @p128si64() { +; CHECK-LABEL: p128si64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 128 +} + +define zeroext i64 @p128zi64() { +; CHECK-LABEL: p128zi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 128 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 128 +} + +define i64 @p2264924160i64() { +; CHECK-LABEL: p2264924160i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -2030043136 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 2264924160 +} + +define signext i64 @p2264924160si64() { +; CHECK-LABEL: p2264924160si64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -2030043136 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 2264924160 +} + +define zeroext i64 @p2264924160zi64() { +; CHECK-LABEL: p2264924160zi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -2030043136 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 2264924160 +} + +define i64 @p2147483647i64() { +; CHECK-LABEL: p2147483647i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 2147483647 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 2147483647 +} + +define signext i64 @p2147483647si64() { +; CHECK-LABEL: p2147483647si64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 2147483647 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 2147483647 +} + +define zeroext i64 @p2147483647zi64() { +; CHECK-LABEL: p2147483647zi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 2147483647 +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 2147483647 +} + +define i64 @p15032385535i64() { +; CHECK-LABEL: p15032385535i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 2147483647 +; CHECK-NEXT: lea.sl %s0, 3(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 15032385535 +} + +define signext i64 @p15032385535si64() { +; CHECK-LABEL: p15032385535si64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 2147483647 +; CHECK-NEXT: lea.sl %s0, 3(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 15032385535 +} + +define zeroext i64 @p15032385535zi64() { +; CHECK-LABEL: p15032385535zi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 2147483647 +; CHECK-NEXT: lea.sl %s0, 3(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 15032385535 +} + +define i64 @p15032385536i64() { +; CHECK-LABEL: p15032385536i64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -2147483648 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, 3(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 15032385536 +} + +define signext i64 @p15032385536si64() { +; CHECK-LABEL: p15032385536si64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -2147483648 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, 3(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 15032385536 +} + +define zeroext i64 @p15032385536zi64() { +; CHECK-LABEL: p15032385536zi64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -2147483648 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, 3(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret i64 15032385536 +} + +define float @m5f32() { +; CHECK-LABEL: m5f32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s0, -1063256064 +; CHECK-NEXT: or %s0, 0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + ret float -5.000000e+00 +} + +define double @m5f64() { +; CHECK-LABEL: m5f64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s0, -1072431104 +; CHECK-NEXT: or %s11, 0, %s9 + ret double -5.000000e+00 +} + +define float @p2p3f32() { +; CHECK-LABEL: p2p3f32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s0, 1075000115 +; CHECK-NEXT: or %s0, 0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + ret float 0x4002666660000000 ; 2.3 +} + +define double @p2p3f64() { +; CHECK-LABEL: p2p3f64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, 1717986918 +; CHECK-NEXT: lea.sl %s0, 1073899110(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret double 2.3 +} + +define float @p128p3f32() { +; CHECK-LABEL: p128p3f32: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s0, 1124093133 +; CHECK-NEXT: or %s0, 0, %s0 +; CHECK-NEXT: or %s11, 0, %s9 + ret float 0x40600999A0000000 ; 128.3 +} + +define double @p128p3f64() { +; CHECK-LABEL: p128p3f64: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea %s0, -1717986918 +; CHECK-NEXT: and %s0, %s0, (32)0 +; CHECK-NEXT: lea.sl %s0, 1080035737(%s0) +; CHECK-NEXT: or %s11, 0, %s9 + ret double 128.3 +} diff --git a/llvm/test/CodeGen/VE/constants_i64.ll b/llvm/test/CodeGen/VE/constants_i64.ll deleted file mode 100644 --- a/llvm/test/CodeGen/VE/constants_i64.ll +++ /dev/null @@ -1,157 +0,0 @@ -; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s - -define i64 @p0i64() { -; CHECK-LABEL: p0i64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 0 -} - -define signext i64 @p0si64() { -; CHECK-LABEL: p0si64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 0 -} - -define zeroext i64 @p0zi64() { -; CHECK-LABEL: p0zi64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: or %s0, 0, (0)1 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 0 -} - -define i64 @p128i64() { -; CHECK-LABEL: p128i64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 128 -} - -define signext i64 @p128si64() { -; CHECK-LABEL: p128si64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 128 -} - -define zeroext i64 @p128zi64() { -; CHECK-LABEL: p128zi64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 128 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 128 -} - -define i64 @p2264924160i64() { -; CHECK-LABEL: p2264924160i64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, -2030043136 -; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 2264924160 -} - -define signext i64 @p2264924160si64() { -; CHECK-LABEL: p2264924160si64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, -2030043136 -; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 2264924160 -} - -define zeroext i64 @p2264924160zi64() { -; CHECK-LABEL: p2264924160zi64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, -2030043136 -; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 2264924160 -} - -define i64 @p2147483647i64() { -; CHECK-LABEL: p2147483647i64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 2147483647 -} - -define signext i64 @p2147483647si64() { -; CHECK-LABEL: p2147483647si64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 2147483647 -} - -define zeroext i64 @p2147483647zi64() { -; CHECK-LABEL: p2147483647zi64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 2147483647 -} - -define i64 @p15032385535i64() { -; CHECK-LABEL: p15032385535i64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: lea.sl %s0, 3(%s0) -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 15032385535 -} - -define signext i64 @p15032385535si64() { -; CHECK-LABEL: p15032385535si64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: lea.sl %s0, 3(%s0) -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 15032385535 -} - -define zeroext i64 @p15032385535zi64() { -; CHECK-LABEL: p15032385535zi64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, 2147483647 -; CHECK-NEXT: lea.sl %s0, 3(%s0) -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 15032385535 -} - -define i64 @p15032385536i64() { -; CHECK-LABEL: p15032385536i64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, -2147483648 -; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: lea.sl %s0, 3(%s0) -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 15032385536 -} - -define signext i64 @p15032385536si64() { -; CHECK-LABEL: p15032385536si64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, -2147483648 -; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: lea.sl %s0, 3(%s0) -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 15032385536 -} - -define zeroext i64 @p15032385536zi64() { -; CHECK-LABEL: p15032385536zi64: -; CHECK: .LBB{{[0-9]+}}_2: -; CHECK-NEXT: lea %s0, -2147483648 -; CHECK-NEXT: and %s0, %s0, (32)0 -; CHECK-NEXT: lea.sl %s0, 3(%s0) -; CHECK-NEXT: or %s11, 0, %s9 - ret i64 15032385536 -}