diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -7350,16 +7350,17 @@
   return ILV.getOrCreateScalarValue(V, Instance);
 }
 
-void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPInterleaveRecipe::print(raw_ostream &O, const Twine &Indent,
+                               VPSlotTracker &SlotTracker) const {
   O << " +\n"
     << Indent << "\"INTERLEAVE-GROUP with factor " << IG->getFactor() << " at ";
   IG->getInsertPos()->printAsOperand(O, false);
   O << ", ";
-  getAddr()->printAsOperand(O);
+  getAddr()->printAsOperand(O, SlotTracker);
   VPValue *Mask = getMask();
   if (Mask) {
     O << ", ";
-    Mask->printAsOperand(O);
+    Mask->printAsOperand(O, SlotTracker);
   }
   O << "\\l\"";
   for (unsigned i = 0; i < IG->getFactor(); ++i)
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -621,7 +621,8 @@
   virtual void execute(struct VPTransformState &State) = 0;
 
   /// Each recipe prints itself.
-  virtual void print(raw_ostream &O, const Twine &Indent) const = 0;
+  virtual void print(raw_ostream &O, const Twine &Indent,
+                     VPSlotTracker &SlotTracker) const = 0;
 
   /// Insert an unlinked recipe into a basic block immediately before
   /// the specified recipe.
@@ -707,10 +708,11 @@
   void execute(VPTransformState &State) override;
 
   /// Print the Recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 
   /// Print the VPInstruction.
-  void print(raw_ostream &O) const;
+  void print(raw_ostream &O, VPSlotTracker &SlotTracker) const;
 
   /// Return true if this instruction may modify memory.
   bool mayWriteToMemory() const {
@@ -756,7 +758,8 @@
   }
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// A recipe for handling GEP instructions.
@@ -786,7 +789,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// A recipe for handling phi nodes of integer and floating-point inductions,
@@ -811,7 +815,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// A recipe for handling all phi nodes except for integer and FP inductions.
@@ -832,7 +837,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// A recipe for vectorizing a phi-node as a sequence of mask-based select
@@ -863,7 +869,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// VPInterleaveRecipe is a recipe for transforming an interleave group of load
@@ -903,7 +910,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 
   const InterleaveGroup<Instruction> *getInterleaveGroup() { return IG; }
 };
@@ -953,7 +961,8 @@
   void setAlsoPack(bool Pack) { AlsoPack = Pack; }
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// A recipe for generating conditional branches on the bits of a mask.
@@ -977,10 +986,11 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override {
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override {
     O << " +\n" << Indent << "\"BRANCH-ON-MASK ";
     if (User)
-      O << *User->getOperand(0);
+      User->getOperand(0)->print(O, SlotTracker);
     else
       O << " All-One";
     O << "\\l\"";
@@ -1012,7 +1022,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// A Recipe for widening load/store operations.
@@ -1052,7 +1063,8 @@
   void execute(VPTransformState &State) override;
 
   /// Print the recipe.
-  void print(raw_ostream &O, const Twine &Indent) const override;
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override;
 };
 
 /// VPBasicBlock serves as the leaf of the Hierarchical Control-Flow Graph. It
@@ -1340,6 +1352,7 @@
   }
 };
 
+class VPSlotTracker;
 /// VPlan models a candidate for vectorization, encoding various decisions take
 /// to produce efficient output IR, including which branches, basic-blocks and
 /// output IR instructions to generate, and their cost. VPlan holds a
@@ -1347,6 +1360,7 @@
 /// VPBlock.
 class VPlan {
   friend class VPlanPrinter;
+  friend class VPSlotTracker;
 
 private:
   /// Hold the single entry to the Hierarchical CFG of the VPlan.
@@ -1480,6 +1494,8 @@
   unsigned BID = 0;
   SmallDenseMap<const VPBlockBase *, unsigned> BlockID;
 
+  VPSlotTracker SlotTracker;
+
   VPlanPrinter(raw_ostream &O, const VPlan &P) : OS(O), Plan(P) {}
 
   /// Handle indentation.
@@ -1703,6 +1719,8 @@
     }
   };
 
+  VPlan &Plan;
+
   /// Mapping of values in the original VPlan to a combined VPInstruction.
   DenseMap<SmallVector<VPValue *, 4>, VPInstruction *, BundleDenseMapInfo>
       BundleToCombined;
@@ -1755,7 +1773,8 @@
   void dumpBundle(ArrayRef<VPValue *> Values);
 
 public:
-  VPlanSlp(VPInterleavedAccessInfo &IAI, VPBasicBlock &BB) : IAI(IAI), BB(BB) {}
+  VPlanSlp(VPlan &Plan, VPInterleavedAccessInfo &IAI, VPBasicBlock &BB)
+      : Plan(Plan), IAI(IAI), BB(BB) {}
 
   ~VPlanSlp() {
     for (auto &KV : BundleToCombined)
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -48,12 +48,11 @@
 
 #define DEBUG_TYPE "vplan"
 
-raw_ostream &llvm::operator<<(raw_ostream &OS, const VPValue &V) {
-  if (const VPInstruction *Instr = dyn_cast<VPInstruction>(&V))
-    Instr->print(OS);
+void VPValue::print(raw_ostream &OS, VPSlotTracker &SlotTracker) const {
+  if (const VPInstruction *Instr = dyn_cast<VPInstruction>(this))
+    Instr->print(OS, SlotTracker);
   else
-    V.printAsOperand(OS);
-  return OS;
+    printAsOperand(OS, SlotTracker);
 }
 
 /// \return the VPBasicBlock that is the entry of Block, possibly indirectly.
@@ -352,14 +351,15 @@
     generateInstruction(State, Part);
 }
 
-void VPInstruction::print(raw_ostream &O, const Twine &Indent) const {
+void VPInstruction::print(raw_ostream &O, const Twine &Indent,
+                          VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"EMIT ";
-  print(O);
+  print(O, SlotTracker);
   O << "\\l\"";
 }
 
-void VPInstruction::print(raw_ostream &O) const {
-  printAsOperand(O);
+void VPInstruction::print(raw_ostream &O, VPSlotTracker &SlotTracker) const {
+  printAsOperand(O, SlotTracker);
   O << " = ";
 
   switch (getOpcode()) {
@@ -381,7 +381,7 @@
 
   for (const VPValue *Operand : operands()) {
     O << " ";
-    Operand->printAsOperand(O);
+    Operand->printAsOperand(O, SlotTracker);
   }
 }
 
@@ -527,6 +527,7 @@
 }
 
 void VPlanPrinter::dump() {
+  SlotTracker.assignSlots(Plan);
   Depth = 1;
   bumpIndent(0);
   OS << "digraph VPlan {\n";
@@ -535,10 +536,14 @@
     OS << "\\n" << DOT::EscapeString(Plan.getName());
   if (!Plan.Value2VPValue.empty() || Plan.BackedgeTakenCount) {
     OS << ", where:";
-    if (Plan.BackedgeTakenCount)
-      OS << "\\n" << *Plan.BackedgeTakenCount << " := BackedgeTakenCount";
+    if (Plan.BackedgeTakenCount) {
+      OS << "\\n";
+      Plan.BackedgeTakenCount->print(OS, SlotTracker);
+      OS << " := BackedgeTakenCount";
+    }
     for (auto Entry : Plan.Value2VPValue) {
-      OS << "\\n" << *Entry.second;
+      OS << "\\n";
+      Entry.second->print(OS, SlotTracker);
       OS << DOT::EscapeString(" := ");
       Entry.first->printAsOperand(OS, false);
     }
@@ -605,25 +610,25 @@
   if (Pred) {
     OS << " +\n" << Indent << " \"BlockPredicate: ";
     if (const VPInstruction *PredI = dyn_cast<VPInstruction>(Pred)) {
-      PredI->printAsOperand(OS);
+      PredI->printAsOperand(OS, SlotTracker);
       OS << " (" << DOT::EscapeString(PredI->getParent()->getName())
          << ")\\l\"";
     } else
-      Pred->printAsOperand(OS);
+      Pred->printAsOperand(OS, SlotTracker);
   }
 
   for (const VPRecipeBase &Recipe : *BasicBlock)
-    Recipe.print(OS, Indent);
+    Recipe.print(OS, Indent, SlotTracker);
 
   // Dump the condition bit.
   const VPValue *CBV = BasicBlock->getCondBit();
   if (CBV) {
     OS << " +\n" << Indent << " \"CondBit: ";
     if (const VPInstruction *CBI = dyn_cast<VPInstruction>(CBV)) {
-      CBI->printAsOperand(OS);
+      CBI->printAsOperand(OS, SlotTracker);
       OS << " (" << DOT::EscapeString(CBI->getParent()->getName()) << ")\\l\"";
     } else {
-      CBV->printAsOperand(OS);
+      CBV->printAsOperand(OS, SlotTracker);
       OS << "\"";
     }
   }
@@ -670,14 +675,15 @@
   O << DOT::EscapeString(IngredientString);
 }
 
-void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPWidenRecipe::print(raw_ostream &O, const Twine &Indent,
+                          VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"WIDEN\\l\"";
   for (auto &Instr : make_range(Begin, End))
     O << " +\n" << Indent << "\"  " << VPlanIngredient(&Instr) << "\\l\"";
 }
 
-void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O,
-                                          const Twine &Indent) const {
+void VPWidenIntOrFpInductionRecipe::print(raw_ostream &O, const Twine &Indent,
+                                          VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"WIDEN-INDUCTION";
   if (Trunc) {
     O << "\\l\"";
@@ -687,7 +693,8 @@
     O << " " << VPlanIngredient(IV) << "\\l\"";
 }
 
-void VPWidenGEPRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPWidenGEPRecipe::print(raw_ostream &O, const Twine &Indent,
+                             VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"WIDEN-GEP ";
   O << (IsPtrLoopInvariant ? "Inv" : "Var");
   size_t IndicesNumber = IsIndexLoopInvariant.size();
@@ -697,11 +704,13 @@
   O << " +\n" << Indent << "\"  "  << VPlanIngredient(GEP) << "\\l\"";
 }
 
-void VPWidenPHIRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPWidenPHIRecipe::print(raw_ostream &O, const Twine &Indent,
+                             VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"WIDEN-PHI " << VPlanIngredient(Phi) << "\\l\"";
 }
 
-void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPBlendRecipe::print(raw_ostream &O, const Twine &Indent,
+                          VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"BLEND ";
   Phi->printAsOperand(O, false);
   O << " =";
@@ -715,13 +724,14 @@
       O << " ";
       Phi->getIncomingValue(I)->printAsOperand(O, false);
       O << "/";
-      User->getOperand(I)->printAsOperand(O);
+      User->getOperand(I)->printAsOperand(O, SlotTracker);
     }
   }
   O << "\\l\"";
 }
 
-void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPReplicateRecipe::print(raw_ostream &O, const Twine &Indent,
+                              VPSlotTracker &SlotTracker) const {
   O << " +\n"
     << Indent << "\"" << (IsUniform ? "CLONE " : "REPLICATE ")
     << VPlanIngredient(Ingredient);
@@ -730,21 +740,22 @@
   O << "\\l\"";
 }
 
-void VPPredInstPHIRecipe::print(raw_ostream &O, const Twine &Indent) const {
+void VPPredInstPHIRecipe::print(raw_ostream &O, const Twine &Indent,
+                                VPSlotTracker &SlotTracker) const {
   O << " +\n"
     << Indent << "\"PHI-PREDICATED-INSTRUCTION " << VPlanIngredient(PredInst)
     << "\\l\"";
 }
 
-void VPWidenMemoryInstructionRecipe::print(raw_ostream &O,
-                                           const Twine &Indent) const {
+void VPWidenMemoryInstructionRecipe::print(raw_ostream &O, const Twine &Indent,
+                                           VPSlotTracker &SlotTracker) const {
   O << " +\n" << Indent << "\"WIDEN " << VPlanIngredient(&Instr);
   O << ", ";
-  getAddr()->printAsOperand(O);
+  getAddr()->printAsOperand(O, SlotTracker);
   VPValue *Mask = getMask();
   if (Mask) {
     O << ", ";
-    Mask->printAsOperand(O);
+    Mask->printAsOperand(O, SlotTracker);
   }
   O << "\\l\"";
 }
@@ -758,6 +769,10 @@
         User->setOperand(I, New);
 }
 
+void VPValue::printAsOperand(raw_ostream &OS, VPSlotTracker &Tracker) const {
+  OS << "%vp" << Tracker.getSlot(this);
+}
+
 void VPInterleavedAccessInfo::visitRegion(VPRegionBlock *Region,
                                           Old2NewTy &Old2New,
                                           InterleavedAccessInfo &IAI) {
@@ -803,3 +818,48 @@
   Old2NewTy Old2New;
   visitRegion(cast<VPRegionBlock>(Plan.getEntry()), Old2New, IAI);
 }
+
+void VPSlotTracker::assignSlot(const VPValue *V) {
+  assert(Slots.find(V) == Slots.end() && "VPValue already has a slot!");
+  Slots[V] = NextSlot++;
+}
+
+void VPSlotTracker::assignSlots(const VPBlockBase *VPBB) {
+  if (auto *Region = dyn_cast<VPRegionBlock>(VPBB))
+    assignSlots(Region);
+  else
+    assignSlots(cast<VPBasicBlock>(VPBB));
+}
+
+void VPSlotTracker::assignSlots(const VPRegionBlock *Region) {
+  ReversePostOrderTraversal<const VPBlockBase *> RPOT(Region->getEntry());
+  for (const VPBlockBase *Block : RPOT)
+    assignSlots(Block);
+}
+
+void VPSlotTracker::assignSlots(const VPBasicBlock *VPBB) {
+  for (const VPRecipeBase &Recipe : *VPBB) {
+    if (const auto *VPI = dyn_cast<VPInstruction>(&Recipe))
+      assignSlot(VPI);
+  }
+}
+
+void VPSlotTracker::assignSlots(const VPlan &Plan) {
+
+  for (const VPValue *V : Plan.VPExternalDefs)
+    assignSlot(V);
+
+  for (auto &E : Plan.Value2VPValue)
+    if (!isa<VPInstruction>(E.second))
+      assignSlot(E.second);
+
+  for (const VPValue *V : Plan.VPCBVs)
+    assignSlot(V);
+
+  if (Plan.BackedgeTakenCount)
+    assignSlot(Plan.BackedgeTakenCount);
+
+  ReversePostOrderTraversal<const VPBlockBase *> RPOT(Plan.getEntry());
+  for (const VPBlockBase *Block : RPOT)
+    assignSlots(Block);
+}
diff --git a/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp b/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
--- a/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp
@@ -463,8 +463,12 @@
   auto *VPI = new VPInstruction(Opcode, CombinedOperands);
   VPI->setUnderlyingInstr(cast<VPInstruction>(Values[0])->getUnderlyingInstr());
 
-  LLVM_DEBUG(dbgs() << "Create VPInstruction "; VPI->print(dbgs());
-             cast<VPInstruction>(Values[0])->print(dbgs()); dbgs() << "\n");
+  VPSlotTracker SlotTracker;
+  SlotTracker.assignSlots(Plan);
+  LLVM_DEBUG(dbgs() << "Create VPInstruction "; VPI->print(dbgs(), SlotTracker);
+             cast<VPInstruction>(Values[0])->print(dbgs(), SlotTracker);
+             dbgs() << "\n");
+  (void)SlotTracker;
   addCombined(Values, VPI);
   return VPI;
 }
diff --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h b/llvm/lib/Transforms/Vectorize/VPlanValue.h
--- a/llvm/lib/Transforms/Vectorize/VPlanValue.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h
@@ -31,6 +31,8 @@
 // Forward declarations.
 class VPUser;
 
+class VPSlotTracker;
+
 // This is the base class of the VPlan Def/Use graph, used for modeling the data
 // flow into, within and out of the VPlan. VPValues can stand for live-ins
 // coming from the input IR, instructions which VPlan will generate if executed
@@ -85,9 +87,8 @@
   /// for any other purpose, as the values may change as LLVM evolves.
   unsigned getVPValueID() const { return SubclassID; }
 
-  void printAsOperand(raw_ostream &OS) const {
-    OS << "%vp" << (unsigned short)(unsigned long long)this;
-  }
+  void printAsOperand(raw_ostream &OS, VPSlotTracker &Tracker) const;
+  void print(raw_ostream &OS, VPSlotTracker &Tracker) const;
 
   unsigned getNumUsers() const { return Users.size(); }
   void addUser(VPUser &User) { Users.push_back(&User); }
@@ -124,7 +125,7 @@
 typedef DenseMap<Value *, VPValue *> Value2VPValueTy;
 typedef DenseMap<VPValue *, Value *> VPValue2ValueTy;
 
-raw_ostream &operator<<(raw_ostream &OS, const VPValue &V);
+// raw_ostream &operator<<(raw_ostream &OS, const VPValue &V);
 
 /// This class augments VPValue with operands which provide the inverse def-use
 /// edges from VPValue's users to their defs.
@@ -180,6 +181,32 @@
     return const_operand_range(op_begin(), op_end());
   }
 };
+class VPlan;
+class VPBasicBlock;
+class VPRegionBlock;
+
+/// This class can be used to assign consecutive numbers to all VPValues in a VPlan and allows querying the numbering for printing, similar to the ModuleSlotTracker for IR values.
+class VPSlotTracker {
+private:
+  DenseMap<const VPValue *, unsigned> Slots;
+  unsigned NextSlot = 0;
+
+  void assignSlots(const VPBlockBase *VPBB);
+  void assignSlots(const VPRegionBlock *Region);
+  void assignSlots(const VPBasicBlock *VPBB);
+  void assignSlot(const VPValue *V);
+
+public:
+  VPSlotTracker() {}
+
+  void assignSlots(const VPlan &Plan);
+
+  unsigned getSlot(const VPValue *V) const {
+    auto I = Slots.find(V);
+    assert(I != Slots.end() && "Not slot for VPValue!");
+    return I->second;
+  }
+};
 
 } // namespace llvm
 
diff --git a/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp
--- a/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp
+++ b/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp
@@ -103,7 +103,7 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(Body->begin(), 12));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 14));
 
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   VPInstruction *CombinedStore = Slp.buildGraph(StoreRoot);
   EXPECT_EQ(64u, Slp.getWidestBundleBits());
@@ -172,7 +172,7 @@
 
   auto VPIAI = getInterleavedAccessInfo(*F, LI->getLoopFor(LoopHeader), *Plan);
 
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   VPInstruction *CombinedStore = Slp.buildGraph(StoreRoot);
   EXPECT_EQ(64u, Slp.getWidestBundleBits());
@@ -237,7 +237,7 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(Body->begin(), 8));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 10));
 
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   VPInstruction *CombinedStore = Slp.buildGraph(StoreRoot);
   EXPECT_EQ(64u, Slp.getWidestBundleBits());
@@ -296,16 +296,16 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(Body->begin(), 5));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 10));
 
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   Slp.buildGraph(StoreRoot);
   EXPECT_FALSE(Slp.isCompletelySLP());
 }
 
-static void checkReorderExample(VPInstruction *Store1, VPInstruction *Store2,
-                                VPBasicBlock *Body,
+static void checkReorderExample(VPlan &Plan, VPInstruction *Store1,
+                                VPInstruction *Store2, VPBasicBlock *Body,
                                 VPInterleavedAccessInfo &&IAI) {
-  VPlanSlp Slp(IAI, *Body);
+  VPlanSlp Slp(Plan, IAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   VPInstruction *CombinedStore = Slp.buildGraph(StoreRoot);
 
@@ -425,7 +425,7 @@
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 26));
 
   checkReorderExample(
-      Store1, Store2, Body,
+      *Plan, Store1, Store2, Body,
       getInterleavedAccessInfo(*F, LI->getLoopFor(LoopHeader), *Plan));
 }
 
@@ -497,7 +497,7 @@
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 26));
 
   checkReorderExample(
-      Store1, Store2, Body,
+      *Plan, Store1, Store2, Body,
       getInterleavedAccessInfo(*F, LI->getLoopFor(LoopHeader), *Plan));
 }
 
@@ -569,7 +569,7 @@
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 26));
 
   auto VPIAI = getInterleavedAccessInfo(*F, LI->getLoopFor(LoopHeader), *Plan);
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   EXPECT_EQ(nullptr, Slp.buildGraph(StoreRoot));
 
@@ -645,7 +645,7 @@
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 26));
 
   checkReorderExample(
-      Store1, Store2, Body,
+      *Plan, Store1, Store2, Body,
       getInterleavedAccessInfo(*F, LI->getLoopFor(LoopHeader), *Plan));
 }
 
@@ -706,7 +706,7 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(BB2->begin(), 3));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(BB2->begin(), 5));
 
-  VPlanSlp Slp(VPIAI, *BB2);
+  VPlanSlp Slp(*Plan, VPIAI, *BB2);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   EXPECT_EQ(nullptr, Slp.buildGraph(StoreRoot));
   EXPECT_EQ(0u, Slp.getWidestBundleBits());
@@ -769,7 +769,7 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(BB2->begin(), 1));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(BB2->begin(), 3));
 
-  VPlanSlp Slp(VPIAI, *BB2);
+  VPlanSlp Slp(*Plan, VPIAI, *BB2);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   EXPECT_EQ(nullptr, Slp.buildGraph(StoreRoot));
   EXPECT_EQ(0u, Slp.getWidestBundleBits());
@@ -828,7 +828,7 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(Body->begin(), 12));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 14));
 
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   EXPECT_EQ(nullptr, Slp.buildGraph(StoreRoot));
   EXPECT_FALSE(Slp.isCompletelySLP());
@@ -887,7 +887,7 @@
   VPInstruction *Store1 = cast<VPInstruction>(&*std::next(Body->begin(), 12));
   VPInstruction *Store2 = cast<VPInstruction>(&*std::next(Body->begin(), 14));
 
-  VPlanSlp Slp(VPIAI, *Body);
+  VPlanSlp Slp(*Plan, VPIAI, *Body);
   SmallVector<VPValue *, 4> StoreRoot = {Store1, Store2};
   Slp.buildGraph(StoreRoot);
   EXPECT_FALSE(Slp.isCompletelySLP());