diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -416,22 +416,19 @@
   DebugLoc DL = MI.getDebugLoc();
   MachineFunction *MF = MBB.getParent();
   auto LoopHeadMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
-  auto LoopIfBodyMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
   auto LoopTailMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
   auto DoneMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
 
   // Insert new MBBs.
   MF->insert(++MBB.getIterator(), LoopHeadMBB);
-  MF->insert(++LoopHeadMBB->getIterator(), LoopIfBodyMBB);
-  MF->insert(++LoopIfBodyMBB->getIterator(), LoopTailMBB);
+  MF->insert(++LoopHeadMBB->getIterator(), LoopTailMBB);
   MF->insert(++LoopTailMBB->getIterator(), DoneMBB);
 
   // Set up successors and transfer remaining instructions to DoneMBB.
-  LoopHeadMBB->addSuccessor(LoopIfBodyMBB);
   LoopHeadMBB->addSuccessor(LoopTailMBB);
-  LoopIfBodyMBB->addSuccessor(LoopTailMBB);
-  LoopTailMBB->addSuccessor(LoopHeadMBB);
+  LoopHeadMBB->addSuccessor(DoneMBB);
   LoopTailMBB->addSuccessor(DoneMBB);
+  LoopTailMBB->addSuccessor(LoopHeadMBB);
   DoneMBB->splice(DoneMBB->end(), &MBB, MI, MBB.end());
   DoneMBB->transferSuccessors(&MBB);
   MBB.addSuccessor(LoopHeadMBB);
@@ -452,7 +449,7 @@
   //   and scratch2, destreg, mask
   //   mv scratch1, destreg
   //   [sext scratch2 if signed min/max]
-  //   ifnochangeneeded scratch2, incr, .looptail
+  //   ifnochangeneeded scratch2, incr, done
   BuildMI(LoopHeadMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg)
       .addReg(AddrReg);
   BuildMI(LoopHeadMBB, DL, TII->get(RISCV::AND), Scratch2Reg)
@@ -470,7 +467,7 @@
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
         .addReg(Scratch2Reg)
         .addReg(IncrReg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   }
   case AtomicRMWInst::Min: {
@@ -478,33 +475,31 @@
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGE))
         .addReg(IncrReg)
         .addReg(Scratch2Reg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   }
   case AtomicRMWInst::UMax:
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
         .addReg(Scratch2Reg)
         .addReg(IncrReg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   case AtomicRMWInst::UMin:
     BuildMI(LoopHeadMBB, DL, TII->get(RISCV::BGEU))
         .addReg(IncrReg)
         .addReg(Scratch2Reg)
-        .addMBB(LoopTailMBB);
+        .addMBB(DoneMBB);
     break;
   }
 
-  // .loopifbody:
+  // .looptail:
   //   xor scratch1, destreg, incr
   //   and scratch1, scratch1, mask
   //   xor scratch1, destreg, scratch1
-  insertMaskedMerge(TII, DL, LoopIfBodyMBB, Scratch1Reg, DestReg, IncrReg,
-                    MaskReg, Scratch1Reg);
-
-  // .looptail:
   //   sc.w scratch1, scratch1, (addr)
   //   bnez scratch1, loop
+  insertMaskedMerge(TII, DL, LoopTailMBB, Scratch1Reg, DestReg, IncrReg,
+                    MaskReg, Scratch1Reg);
   BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW32(Ordering)), Scratch1Reg)
       .addReg(AddrReg)
       .addReg(Scratch1Reg);
@@ -518,7 +513,6 @@
 
   LivePhysRegs LiveRegs;
   computeAndAddLiveIns(LiveRegs, *LoopHeadMBB);
-  computeAndAddLiveIns(LiveRegs, *LoopIfBodyMBB);
   computeAndAddLiveIns(LiveRegs, *LoopTailMBB);
   computeAndAddLiveIns(LiveRegs, *DoneMBB);
 
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -2137,10 +2137,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB35_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB35_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -2212,10 +2211,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB35_3: # in Loop: Header=BB35_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB35_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB35_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b monotonic
@@ -2291,10 +2289,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB36_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB36_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -2366,10 +2363,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB36_3: # in Loop: Header=BB36_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB36_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB36_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acquire
@@ -2445,10 +2441,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB37_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB37_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -2520,10 +2515,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB37_3: # in Loop: Header=BB37_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB37_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB37_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b release
@@ -2599,10 +2593,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB38_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB38_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -2674,10 +2667,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB38_3: # in Loop: Header=BB38_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB38_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB38_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b acq_rel
@@ -2753,10 +2745,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB39_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB39_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -2828,10 +2819,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB39_3: # in Loop: Header=BB39_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB39_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB39_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i8* %a, i8 %b seq_cst
@@ -2907,10 +2897,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB40_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB40_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -2982,10 +2971,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB40_3: # in Loop: Header=BB40_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB40_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB40_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b monotonic
@@ -3061,10 +3049,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB41_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB41_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -3136,10 +3123,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB41_3: # in Loop: Header=BB41_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB41_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB41_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acquire
@@ -3215,10 +3201,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB42_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB42_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -3290,10 +3275,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB42_3: # in Loop: Header=BB42_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB42_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB42_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b release
@@ -3369,10 +3353,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB43_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB43_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -3444,10 +3427,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB43_3: # in Loop: Header=BB43_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB43_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB43_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b acq_rel
@@ -3523,10 +3505,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB44_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB44_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -3598,10 +3579,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB44_3: # in Loop: Header=BB44_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB44_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB44_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i8* %a, i8 %b seq_cst
@@ -3670,10 +3650,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB45_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB45_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -3738,10 +3717,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB45_3: # in Loop: Header=BB45_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB45_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB45_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b monotonic
@@ -3810,10 +3788,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB46_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB46_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -3878,10 +3855,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB46_3: # in Loop: Header=BB46_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB46_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB46_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b acquire
@@ -3950,10 +3926,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB47_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB47_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4018,10 +3993,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB47_3: # in Loop: Header=BB47_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB47_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB47_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b release
@@ -4090,10 +4064,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB48_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB48_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4158,10 +4131,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB48_3: # in Loop: Header=BB48_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB48_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB48_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b acq_rel
@@ -4230,10 +4202,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB49_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB49_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4298,10 +4269,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB49_3: # in Loop: Header=BB49_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB49_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB49_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i8* %a, i8 %b seq_cst
@@ -4370,10 +4340,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB50_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB50_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4438,10 +4407,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB50_3: # in Loop: Header=BB50_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB50_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB50_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b monotonic
@@ -4510,10 +4478,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB51_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB51_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4578,10 +4545,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB51_3: # in Loop: Header=BB51_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB51_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB51_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b acquire
@@ -4650,10 +4616,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB52_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB52_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4718,10 +4683,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB52_3: # in Loop: Header=BB52_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB52_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB52_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b release
@@ -4790,10 +4754,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB53_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB53_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4858,10 +4821,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB53_3: # in Loop: Header=BB53_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB53_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB53_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b acq_rel
@@ -4930,10 +4892,9 @@
 ; RV32IA-NEXT:    xor a5, a4, a1
 ; RV32IA-NEXT:    and a5, a5, a3
 ; RV32IA-NEXT:    xor a5, a4, a5
-; RV32IA-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB54_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB54_3:
 ; RV32IA-NEXT:    srl a0, a4, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -4998,10 +4959,9 @@
 ; RV64IA-NEXT:    xor a5, a4, a1
 ; RV64IA-NEXT:    and a5, a5, a3
 ; RV64IA-NEXT:    xor a5, a4, a5
-; RV64IA-NEXT:  .LBB54_3: # in Loop: Header=BB54_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB54_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB54_3:
 ; RV64IA-NEXT:    srlw a0, a4, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i8* %a, i8 %b seq_cst
@@ -7228,10 +7188,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB90_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB90_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -7304,10 +7263,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB90_3: # in Loop: Header=BB90_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB90_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB90_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b monotonic
@@ -7384,10 +7342,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB91_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB91_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -7460,10 +7417,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB91_3: # in Loop: Header=BB91_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB91_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB91_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b acquire
@@ -7540,10 +7496,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB92_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB92_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -7616,10 +7571,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB92_3: # in Loop: Header=BB92_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB92_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB92_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b release
@@ -7696,10 +7650,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB93_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB93_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -7772,10 +7725,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB93_3: # in Loop: Header=BB93_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB93_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB93_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b acq_rel
@@ -7852,10 +7804,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB94_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB94_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -7928,10 +7879,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB94_3: # in Loop: Header=BB94_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB94_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB94_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw max i16* %a, i16 %b seq_cst
@@ -8008,10 +7958,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB95_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB95_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -8084,10 +8033,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB95_3: # in Loop: Header=BB95_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB95_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB95_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b monotonic
@@ -8164,10 +8112,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
 ; RV32IA-NEXT:    sc.w a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB96_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB96_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -8240,10 +8187,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB96_3: # in Loop: Header=BB96_1 Depth=1
 ; RV64IA-NEXT:    sc.w a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB96_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB96_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b acquire
@@ -8320,10 +8266,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB97_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB97_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -8396,10 +8341,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB97_3: # in Loop: Header=BB97_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB97_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB97_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b release
@@ -8476,10 +8420,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB98_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB98_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -8552,10 +8495,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB98_3: # in Loop: Header=BB98_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB98_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB98_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b acq_rel
@@ -8632,10 +8574,9 @@
 ; RV32IA-NEXT:    xor a2, a5, a1
 ; RV32IA-NEXT:    and a2, a2, a7
 ; RV32IA-NEXT:    xor a2, a5, a2
-; RV32IA-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV32IA-NEXT:    bnez a2, .LBB99_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB99_3:
 ; RV32IA-NEXT:    srl a0, a5, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -8708,10 +8649,9 @@
 ; RV64IA-NEXT:    xor a2, a5, a1
 ; RV64IA-NEXT:    and a2, a2, a7
 ; RV64IA-NEXT:    xor a2, a5, a2
-; RV64IA-NEXT:  .LBB99_3: # in Loop: Header=BB99_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a2, a2, (a6)
 ; RV64IA-NEXT:    bnez a2, .LBB99_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB99_3:
 ; RV64IA-NEXT:    srlw a0, a5, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw min i16* %a, i16 %b seq_cst
@@ -8785,10 +8725,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB100_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB100_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -8858,10 +8797,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB100_3: # in Loop: Header=BB100_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB100_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB100_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b monotonic
@@ -8935,10 +8873,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB101_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB101_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9008,10 +8945,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB101_3: # in Loop: Header=BB101_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB101_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB101_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b acquire
@@ -9085,10 +9021,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB102_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB102_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9158,10 +9093,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB102_3: # in Loop: Header=BB102_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB102_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB102_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b release
@@ -9235,10 +9169,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB103_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB103_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9308,10 +9241,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB103_3: # in Loop: Header=BB103_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB103_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB103_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b acq_rel
@@ -9385,10 +9317,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB104_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB104_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9458,10 +9389,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB104_3: # in Loop: Header=BB104_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB104_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB104_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umax i16* %a, i16 %b seq_cst
@@ -9535,10 +9465,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB105_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB105_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9608,10 +9537,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB105_3: # in Loop: Header=BB105_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB105_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB105_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b monotonic
@@ -9685,10 +9613,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
 ; RV32IA-NEXT:    sc.w a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB106_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB106_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9758,10 +9685,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB106_3: # in Loop: Header=BB106_1 Depth=1
 ; RV64IA-NEXT:    sc.w a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB106_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB106_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b acquire
@@ -9835,10 +9761,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB107_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB107_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -9908,10 +9833,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB107_3: # in Loop: Header=BB107_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB107_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB107_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b release
@@ -9985,10 +9909,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
 ; RV32IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB108_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB108_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -10058,10 +9981,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB108_3: # in Loop: Header=BB108_1 Depth=1
 ; RV64IA-NEXT:    sc.w.rl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB108_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB108_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b acq_rel
@@ -10135,10 +10057,9 @@
 ; RV32IA-NEXT:    xor a5, a3, a1
 ; RV32IA-NEXT:    and a5, a5, a4
 ; RV32IA-NEXT:    xor a5, a3, a5
-; RV32IA-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
 ; RV32IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV32IA-NEXT:    bnez a5, .LBB109_1
-; RV32IA-NEXT:  # %bb.4:
+; RV32IA-NEXT:  .LBB109_3:
 ; RV32IA-NEXT:    srl a0, a3, a0
 ; RV32IA-NEXT:    ret
 ;
@@ -10208,10 +10129,9 @@
 ; RV64IA-NEXT:    xor a5, a3, a1
 ; RV64IA-NEXT:    and a5, a5, a4
 ; RV64IA-NEXT:    xor a5, a3, a5
-; RV64IA-NEXT:  .LBB109_3: # in Loop: Header=BB109_1 Depth=1
 ; RV64IA-NEXT:    sc.w.aqrl a5, a5, (a6)
 ; RV64IA-NEXT:    bnez a5, .LBB109_1
-; RV64IA-NEXT:  # %bb.4:
+; RV64IA-NEXT:  .LBB109_3:
 ; RV64IA-NEXT:    srlw a0, a3, a0
 ; RV64IA-NEXT:    ret
   %1 = atomicrmw umin i16* %a, i16 %b seq_cst
@@ -13143,7 +13063,7 @@
 ; RV32I-NEXT:    call __atomic_compare_exchange_4
 ; RV32I-NEXT:    lw a3, 12(sp)
 ; RV32I-NEXT:    bnez a0, .LBB162_4
-; RV32I-NEXT:  LBB162_2: # %atomicrmw.start
+; RV32I-NEXT:  .LBB162_2: # %atomicrmw.start
 ; RV32I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32I-NEXT:    mv a2, a3
 ; RV32I-NEXT:    bgeu s1, a3, .LBB162_1
@@ -14848,7 +14768,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB200_5
-; RV32I-NEXT:  .LBB200_4:
+; RV32I-NEXT:  .LBB200_4: # in Loop: Header=BB200_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB200_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB200_2 Depth=1
@@ -14905,7 +14825,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB200_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB200_5
-; RV32IA-NEXT:  .LBB200_4:
+; RV32IA-NEXT:  .LBB200_4: # in Loop: Header=BB200_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB200_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB200_2 Depth=1
@@ -15010,7 +14930,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB201_5
-; RV32I-NEXT:  .LBB201_4:
+; RV32I-NEXT:  .LBB201_4: # in Loop: Header=BB201_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB201_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB201_2 Depth=1
@@ -15067,7 +14987,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB201_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB201_5
-; RV32IA-NEXT:  .LBB201_4:
+; RV32IA-NEXT:  .LBB201_4: # in Loop: Header=BB201_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB201_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB201_2 Depth=1
@@ -15172,7 +15092,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB202_5
-; RV32I-NEXT:  .LBB202_4:
+; RV32I-NEXT:  .LBB202_4: # in Loop: Header=BB202_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB202_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB202_2 Depth=1
@@ -15229,7 +15149,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB202_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB202_5
-; RV32IA-NEXT:  .LBB202_4:
+; RV32IA-NEXT:  .LBB202_4: # in Loop: Header=BB202_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB202_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB202_2 Depth=1
@@ -15334,7 +15254,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB203_5
-; RV32I-NEXT:  .LBB203_4:
+; RV32I-NEXT:  .LBB203_4: # in Loop: Header=BB203_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB203_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB203_2 Depth=1
@@ -15391,7 +15311,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB203_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB203_5
-; RV32IA-NEXT:  .LBB203_4:
+; RV32IA-NEXT:  .LBB203_4: # in Loop: Header=BB203_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB203_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB203_2 Depth=1
@@ -15496,7 +15416,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB204_5
-; RV32I-NEXT:  .LBB204_4:
+; RV32I-NEXT:  .LBB204_4: # in Loop: Header=BB204_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB204_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB204_2 Depth=1
@@ -15553,7 +15473,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB204_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB204_5
-; RV32IA-NEXT:  .LBB204_4:
+; RV32IA-NEXT:  .LBB204_4: # in Loop: Header=BB204_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB204_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB204_2 Depth=1
@@ -15658,7 +15578,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB205_5
-; RV32I-NEXT:  .LBB205_4:
+; RV32I-NEXT:  .LBB205_4: # in Loop: Header=BB205_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB205_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB205_2 Depth=1
@@ -15716,7 +15636,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB205_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB205_5
-; RV32IA-NEXT:  .LBB205_4:
+; RV32IA-NEXT:  .LBB205_4: # in Loop: Header=BB205_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB205_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB205_2 Depth=1
@@ -15822,7 +15742,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB206_5
-; RV32I-NEXT:  .LBB206_4:
+; RV32I-NEXT:  .LBB206_4: # in Loop: Header=BB206_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB206_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB206_2 Depth=1
@@ -15880,7 +15800,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB206_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB206_5
-; RV32IA-NEXT:  .LBB206_4:
+; RV32IA-NEXT:  .LBB206_4: # in Loop: Header=BB206_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB206_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB206_2 Depth=1
@@ -15986,7 +15906,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB207_5
-; RV32I-NEXT:  .LBB207_4:
+; RV32I-NEXT:  .LBB207_4: # in Loop: Header=BB207_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB207_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB207_2 Depth=1
@@ -16044,7 +15964,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB207_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB207_5
-; RV32IA-NEXT:  .LBB207_4:
+; RV32IA-NEXT:  .LBB207_4: # in Loop: Header=BB207_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB207_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB207_2 Depth=1
@@ -16150,7 +16070,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB208_5
-; RV32I-NEXT:  .LBB208_4:
+; RV32I-NEXT:  .LBB208_4: # in Loop: Header=BB208_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB208_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB208_2 Depth=1
@@ -16208,7 +16128,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB208_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB208_5
-; RV32IA-NEXT:  .LBB208_4:
+; RV32IA-NEXT:  .LBB208_4: # in Loop: Header=BB208_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB208_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB208_2 Depth=1
@@ -16314,7 +16234,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32I-NEXT:    slt a0, s1, a5
 ; RV32I-NEXT:    j .LBB209_5
-; RV32I-NEXT:  .LBB209_4:
+; RV32I-NEXT:  .LBB209_4: # in Loop: Header=BB209_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB209_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB209_2 Depth=1
@@ -16372,7 +16292,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB209_2 Depth=1
 ; RV32IA-NEXT:    slt a0, s1, a5
 ; RV32IA-NEXT:    j .LBB209_5
-; RV32IA-NEXT:  .LBB209_4:
+; RV32IA-NEXT:  .LBB209_4: # in Loop: Header=BB209_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB209_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB209_2 Depth=1
@@ -16478,7 +16398,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB210_5
-; RV32I-NEXT:  .LBB210_4:
+; RV32I-NEXT:  .LBB210_4: # in Loop: Header=BB210_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB210_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB210_2 Depth=1
@@ -16535,7 +16455,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB210_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB210_5
-; RV32IA-NEXT:  .LBB210_4:
+; RV32IA-NEXT:  .LBB210_4: # in Loop: Header=BB210_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB210_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB210_2 Depth=1
@@ -16640,7 +16560,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB211_5
-; RV32I-NEXT:  .LBB211_4:
+; RV32I-NEXT:  .LBB211_4: # in Loop: Header=BB211_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB211_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB211_2 Depth=1
@@ -16697,7 +16617,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB211_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB211_5
-; RV32IA-NEXT:  .LBB211_4:
+; RV32IA-NEXT:  .LBB211_4: # in Loop: Header=BB211_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB211_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB211_2 Depth=1
@@ -16802,7 +16722,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB212_5
-; RV32I-NEXT:  .LBB212_4:
+; RV32I-NEXT:  .LBB212_4: # in Loop: Header=BB212_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB212_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB212_2 Depth=1
@@ -16859,7 +16779,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB212_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB212_5
-; RV32IA-NEXT:  .LBB212_4:
+; RV32IA-NEXT:  .LBB212_4: # in Loop: Header=BB212_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB212_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB212_2 Depth=1
@@ -16964,7 +16884,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB213_5
-; RV32I-NEXT:  .LBB213_4:
+; RV32I-NEXT:  .LBB213_4: # in Loop: Header=BB213_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB213_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB213_2 Depth=1
@@ -17021,7 +16941,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB213_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB213_5
-; RV32IA-NEXT:  .LBB213_4:
+; RV32IA-NEXT:  .LBB213_4: # in Loop: Header=BB213_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB213_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB213_2 Depth=1
@@ -17126,7 +17046,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB214_5
-; RV32I-NEXT:  .LBB214_4:
+; RV32I-NEXT:  .LBB214_4: # in Loop: Header=BB214_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB214_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB214_2 Depth=1
@@ -17183,7 +17103,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB214_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB214_5
-; RV32IA-NEXT:  .LBB214_4:
+; RV32IA-NEXT:  .LBB214_4: # in Loop: Header=BB214_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB214_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB214_2 Depth=1
@@ -17288,7 +17208,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB215_5
-; RV32I-NEXT:  .LBB215_4:
+; RV32I-NEXT:  .LBB215_4: # in Loop: Header=BB215_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB215_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB215_2 Depth=1
@@ -17346,7 +17266,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB215_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB215_5
-; RV32IA-NEXT:  .LBB215_4:
+; RV32IA-NEXT:  .LBB215_4: # in Loop: Header=BB215_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB215_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB215_2 Depth=1
@@ -17452,7 +17372,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB216_5
-; RV32I-NEXT:  .LBB216_4:
+; RV32I-NEXT:  .LBB216_4: # in Loop: Header=BB216_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB216_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB216_2 Depth=1
@@ -17510,7 +17430,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB216_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB216_5
-; RV32IA-NEXT:  .LBB216_4:
+; RV32IA-NEXT:  .LBB216_4: # in Loop: Header=BB216_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB216_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB216_2 Depth=1
@@ -17616,7 +17536,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB217_5
-; RV32I-NEXT:  .LBB217_4:
+; RV32I-NEXT:  .LBB217_4: # in Loop: Header=BB217_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB217_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB217_2 Depth=1
@@ -17674,7 +17594,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB217_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB217_5
-; RV32IA-NEXT:  .LBB217_4:
+; RV32IA-NEXT:  .LBB217_4: # in Loop: Header=BB217_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB217_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB217_2 Depth=1
@@ -17780,7 +17700,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB218_5
-; RV32I-NEXT:  .LBB218_4:
+; RV32I-NEXT:  .LBB218_4: # in Loop: Header=BB218_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB218_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB218_2 Depth=1
@@ -17838,7 +17758,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB218_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB218_5
-; RV32IA-NEXT:  .LBB218_4:
+; RV32IA-NEXT:  .LBB218_4: # in Loop: Header=BB218_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB218_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB218_2 Depth=1
@@ -17944,7 +17864,7 @@
 ; RV32I-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s1, a5
 ; RV32I-NEXT:    j .LBB219_5
-; RV32I-NEXT:  .LBB219_4:
+; RV32I-NEXT:  .LBB219_4: # in Loop: Header=BB219_2 Depth=1
 ; RV32I-NEXT:    sltu a0, s2, a4
 ; RV32I-NEXT:  .LBB219_5: # %atomicrmw.start
 ; RV32I-NEXT:    # in Loop: Header=BB219_2 Depth=1
@@ -18002,7 +17922,7 @@
 ; RV32IA-NEXT:    # in Loop: Header=BB219_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s1, a5
 ; RV32IA-NEXT:    j .LBB219_5
-; RV32IA-NEXT:  .LBB219_4:
+; RV32IA-NEXT:  .LBB219_4: # in Loop: Header=BB219_2 Depth=1
 ; RV32IA-NEXT:    sltu a0, s2, a4
 ; RV32IA-NEXT:  .LBB219_5: # %atomicrmw.start
 ; RV32IA-NEXT:    # in Loop: Header=BB219_2 Depth=1