diff --git a/mlir/docs/ConversionToLLVMDialect.md b/mlir/docs/ConversionToLLVMDialect.md --- a/mlir/docs/ConversionToLLVMDialect.md +++ b/mlir/docs/ConversionToLLVMDialect.md @@ -400,7 +400,7 @@ ```mlir // Compute the linearized index from strides. Each block below extracts one -// stride from the descriptor, multipllies it with the index and accumulates +// stride from the descriptor, multiplies it with the index and accumulates // the total offset. %stride1 = llvm.extractvalue[4, 0] : !llvm<"{float*, float*, i64, i64[4], i64[4]}"> %idx1 = llvm.mlir.constant(1 : index) !llvm.i64 diff --git a/mlir/docs/Dialects/Vector.md b/mlir/docs/Dialects/Vector.md --- a/mlir/docs/Dialects/Vector.md +++ b/mlir/docs/Dialects/Vector.md @@ -428,7 +428,7 @@ appropriate constant. Then, the existing lowering to LLVM-IR immediately applies, with extensions for accelerator-specific intrinsics. -It is the role of an Accelerator-specfic vector dialect (see codegen flow in +It is the role of an Accelerator-specific vector dialect (see codegen flow in the figure above) to lower the `vector.cast`. Accelerator -> LLVM lowering would then consist of a bunch of `Accelerator -> Accelerator` rewrites to perform the casts composed with `Accelerator -> LLVM` conversions + intrinsics diff --git a/mlir/docs/ShapeInference.md b/mlir/docs/ShapeInference.md --- a/mlir/docs/ShapeInference.md +++ b/mlir/docs/ShapeInference.md @@ -44,7 +44,7 @@ `TestReturnTypeDriver` in the test dialect. The driver performs two checks: 1. Verification that the return types specified matches the infered types. This - explicit check will be removed and made part of Op verificaton instead. + explicit check will be removed and made part of Op verification instead. 2. Test the creation of Ops without specifying the return type explicitly in function `testCreateFunctions` by creating new binary Ops (Op classes specified in `TestReturnTypeDriver`) using 1) all operands to diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td @@ -68,9 +68,10 @@ MemRefType is contiguous, the resulting memref may require explicit alloc and copies. - A reassociation is defined as a continous grouping of dimensions and is - represented with an affine map array attribute. In the future, non-continous - groupings may be allowed (i.e. permutations, reindexings etc). + A reassociation is defined as a continuous grouping of dimensions and is + represented with an affine map array attribute. In the future, + non-continuous groupings may be allowed (i.e. permutations, reindexings + etc). For now, it is assumed that either: 1. a reassociation produces and consumes contiguous MemRefType or, diff --git a/mlir/include/mlir/Dialect/LoopOps/LoopOps.td b/mlir/include/mlir/Dialect/LoopOps/LoopOps.td --- a/mlir/include/mlir/Dialect/LoopOps/LoopOps.td +++ b/mlir/include/mlir/Dialect/LoopOps/LoopOps.td @@ -182,8 +182,8 @@ def ReduceOp : Loop_Op<"reduce", [HasParent<"ParallelOp">]> { let summary = "reduce operation for parallel for"; let description = [{ - "loop.reduce" is an operation occuring inside "loop.parallel" operations. It - consists of one block with two arguments which have the same type as the + "loop.reduce" is an operation occurring inside "loop.parallel" operations. + It consists of one block with two arguments which have the same type as the operand of "loop.reduce". "loop.reduce" is used to model the value for reduction computations of a diff --git a/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td --- a/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td +++ b/mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td @@ -137,7 +137,7 @@ extensions for the implementing SPIR-V operation. The returned value is a nested vector whose element is `mlir::spirv::Extension`s. The outer vector's elements (which are vectors) should be interpreted as conjunction - while the innner vector's elements (which are `mlir::spirv::Extension`s) + while the inner vector's elements (which are `mlir::spirv::Extension`s) should be interpreted as disjunction. For example, given ``` @@ -174,9 +174,9 @@ This interface provides a `getCapabilities()` method to query the required capabilities for the implementing SPIR-V operation. The returned value - is a neted vector whose element is `mlir::spirv::Capability`s. The outer + is a nested vector whose element is `mlir::spirv::Capability`s. The outer vector's elements (which are vectors) should be interpreted as conjunction - while the innner vector's elements (which are `mlir::spirv::Capability`s) + while the inner vector's elements (which are `mlir::spirv::Capability`s) should be interpreted as disjunction. For example, given ``` diff --git a/mlir/include/mlir/IR/StandardTypes.h b/mlir/include/mlir/IR/StandardTypes.h --- a/mlir/include/mlir/IR/StandardTypes.h +++ b/mlir/include/mlir/IR/StandardTypes.h @@ -579,7 +579,7 @@ /// Return a version of `t` with identity layout if it can be determined /// statically that the layout is the canonical contiguous strided layout. /// Otherwise pass `t`'s layout into `simplifyAffineMap` and return a copy of -/// `t` with simplifed layout. +/// `t` with simplified layout. MemRefType canonicalizeStridedLayout(MemRefType t); /// Return true if the layout for `t` is compatible with strided semantics. diff --git a/mlir/include/mlir/Support/STLExtras.h b/mlir/include/mlir/Support/STLExtras.h --- a/mlir/include/mlir/Support/STLExtras.h +++ b/mlir/include/mlir/Support/STLExtras.h @@ -187,7 +187,8 @@ /// drop_front/slice/etc.. Derived range classes must implement the following /// static methods: /// * ReferenceT dereference_iterator(const BaseT &base, ptrdiff_t index) -/// - Derefence an iterator pointing to the base object at the given index. +/// - Dereference an iterator pointing to the base object at the given +/// index. /// * BaseT offset_base(const BaseT &base, ptrdiff_t index) /// - Return a new base that is offset from the provide base by 'index' /// elements. @@ -287,7 +288,7 @@ /// instead. Derived range classes are expected to implement the following /// static method: /// * ReferenceT dereference(const BaseT &base, ptrdiff_t index) -/// - Derefence an iterator pointing to a parent base at the given index. +/// - Dereference an iterator pointing to a parent base at the given index. template class indexed_accessor_range diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -159,7 +159,7 @@ // TODO(ajcbik): consider replacing this one-pattern lowering // with a two-pattern lowering using other vector // ops once all insert/extract/shuffle operations - // are available with lowering implemention. + // are available with lowering implementation. // Value expandRanks(Value value, Location loc, VectorType srcVectorType, VectorType dstVectorType, diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp @@ -830,7 +830,7 @@ // Builder, printer and verifier for LLVM::GlobalOp. //===----------------------------------------------------------------------===// -/// Returns the name used for the linkge attribute. This *must* correspond to +/// Returns the name used for the linkage attribute. This *must* correspond to /// the name of the attribute in ODS. static StringRef getLinkageAttrName() { return "linkage"; } diff --git a/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp b/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp --- a/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp +++ b/mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp @@ -285,7 +285,7 @@ // Make sure this op's required extensions are allowed to use. For each op, // we return a vector of vector for its extension requirements following - // ((Extension::A OR Extenion::B) AND (Extension::C OR Extension::D)) + // ((Extension::A OR Extension::B) AND (Extension::C OR Extension::D)) // convention. Ops not implementing QueryExtensionInterface do not require // extensions to be available. if (auto extensions = dyn_cast(op)) { @@ -302,7 +302,7 @@ // Make sure this op's required extensions are allowed to use. For each op, // we return a vector of vector for its capability requirements following - // ((Capability::A OR Extenion::B) AND (Capability::C OR Capability::D)) + // ((Capability::A OR Extension::B) AND (Capability::C OR Capability::D)) // convention. Ops not implementing QueryExtensionInterface do not require // extensions to be available. if (auto capabilities = dyn_cast(op)) { diff --git a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp --- a/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp +++ b/mlir/lib/Dialect/VectorOps/VectorTransforms.cpp @@ -471,7 +471,7 @@ unsigned resultIndex; if (auto contractionOp = dyn_cast(op)) { - // Popultate state for vector ContractionOp. + // Populate state for vector ContractionOp. getVectorContractionOpUnrollState(contractionOp, targetShape, iterationBounds, vectors, resultIndex); } else { @@ -529,7 +529,7 @@ PatternMatchResult matchAndRewrite(vector::TransferReadOp xferReadOp, PatternRewriter &rewriter) const override { - // TODO(andydavis, ntv) Support spliting TransferReadOp with non-identity + // TODO(andydavis, ntv) Support splitting TransferReadOp with non-identity // permutation maps. Repurpose code from MaterializeVectors transformation. if (!xferReadOp.permutation_map().isIdentity()) return matchFailure(); @@ -582,7 +582,7 @@ PatternMatchResult matchAndRewrite(vector::TransferWriteOp xferWriteOp, PatternRewriter &rewriter) const override { - // TODO(andydavis, ntv) Support spliting TransferWriteOp with non-identity + // TODO(andydavis, ntv) Support splitting TransferWriteOp with non-identity // permutation maps. Repurpose code from MaterializeVectors transformation. if (!xferWriteOp.permutation_map().isIdentity()) return matchFailure(); diff --git a/mlir/lib/IR/AsmPrinter.cpp b/mlir/lib/IR/AsmPrinter.cpp --- a/mlir/lib/IR/AsmPrinter.cpp +++ b/mlir/lib/IR/AsmPrinter.cpp @@ -422,7 +422,7 @@ /// This class manages the state of SSA value names. class SSANameState { public: - /// A sentinal value used for values with names set. + /// A sentinel value used for values with names set. enum : unsigned { NameSentinel = ~0U }; SSANameState(Operation *op, diff --git a/mlir/lib/IR/StandardTypes.cpp b/mlir/lib/IR/StandardTypes.cpp --- a/mlir/lib/IR/StandardTypes.cpp +++ b/mlir/lib/IR/StandardTypes.cpp @@ -702,7 +702,7 @@ /// Return a version of `t` with identity layout if it can be determined /// statically that the layout is the canonical contiguous strided layout. /// Otherwise pass `t`'s layout into `simplifyAffineMap` and return a copy of -/// `t` with simplifed layout. +/// `t` with simplified layout. /// If `t` has multiple layout maps or a multi-result layout, just return `t`. MemRefType mlir::canonicalizeStridedLayout(MemRefType t) { auto affineMaps = t.getAffineMaps(); diff --git a/mlir/lib/IR/Visitors.cpp b/mlir/lib/IR/Visitors.cpp --- a/mlir/lib/IR/Visitors.cpp +++ b/mlir/lib/IR/Visitors.cpp @@ -1,4 +1,4 @@ -//===- Visitors.cpp - MLIR Visitor Utilties -------------------------------===// +//===- Visitors.cpp - MLIR Visitor Utilities ------------------------------===// // // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp --- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp @@ -66,7 +66,7 @@ llvm::ArrayType::get(elementType, shape.front()), nested); } -/// Returns the first non-sequential type netsed in sequential types. +/// Returns the first non-sequential type nested in sequential types. static llvm::Type *getInnermostElementType(llvm::Type *type) { while (isa(type)) type = type->getSequentialElementType(); diff --git a/mlir/lib/Transforms/LoopFusion.cpp b/mlir/lib/Transforms/LoopFusion.cpp --- a/mlir/lib/Transforms/LoopFusion.cpp +++ b/mlir/lib/Transforms/LoopFusion.cpp @@ -541,7 +541,7 @@ // on the value of 'createPrivateMemRef'. void updateEdges(unsigned srcId, unsigned dstId, Value oldMemRef, bool createPrivateMemRef) { - // For each edge in 'inEdges[srcId]': add new edge remaping to 'dstId'. + // For each edge in 'inEdges[srcId]': add new edge remapping to 'dstId'. if (inEdges.count(srcId) > 0) { SmallVector oldInEdges = inEdges[srcId]; for (auto &inEdge : oldInEdges) { diff --git a/mlir/test/Dialect/SPIRV/target-env.mlir b/mlir/test/Dialect/SPIRV/target-env.mlir --- a/mlir/test/Dialect/SPIRV/target-env.mlir +++ b/mlir/test/Dialect/SPIRV/target-env.mlir @@ -11,7 +11,7 @@ // whose value, if containing AtomicCounterMemory bit, additionally requires // AtomicStorage capability. -// spv.BitReverse is available in all SPIR-V versiosn under Shader capability. +// spv.BitReverse is available in all SPIR-V versions under Shader capability. // spv.GroupNonUniformBallot is available starting from SPIR-V 1.3 under // GroupNonUniform capability. diff --git a/mlir/test/lib/TestDialect/TestPatterns.cpp b/mlir/test/lib/TestDialect/TestPatterns.cpp --- a/mlir/test/lib/TestDialect/TestPatterns.cpp +++ b/mlir/test/lib/TestDialect/TestPatterns.cpp @@ -58,7 +58,7 @@ //===----------------------------------------------------------------------===// namespace { -// Generate ops for each instance where the type can be succesfully infered. +// Generate ops for each instance where the type can be successfully infered. template static void invokeCreateWithInferedReturnType(Operation *op) { auto *context = op->getContext(); diff --git a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp --- a/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp +++ b/mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp @@ -47,7 +47,7 @@ name = record.getName(); assert(name.startswith("int_") && - "LLVM intinsic names are expected to start with 'int_'"); + "LLVM intrinsic names are expected to start with 'int_'"); name = name.drop_front(4); llvm::SmallVector chunks; name.split(chunks, '_'); @@ -58,7 +58,7 @@ llvm::StringRef getProperRecordName() const { llvm::StringRef name = record.getName(); assert(name.startswith("int_") && - "LLVM intinsic names are expected to start with 'int_'"); + "LLVM intrinsic names are expected to start with 'int_'"); return name.drop_front(4); } @@ -109,7 +109,7 @@ } private: - /// Names of the fileds in the Intrinsic LLVM Tablegen class. + /// Names of the fields in the Intrinsic LLVM Tablegen class. const char *fieldName = "LLVMName"; const char *fieldOperands = "ParamTypes"; const char *fieldResults = "RetTypes"; diff --git a/mlir/tools/mlir-tblgen/RewriterGen.cpp b/mlir/tools/mlir-tblgen/RewriterGen.cpp --- a/mlir/tools/mlir-tblgen/RewriterGen.cpp +++ b/mlir/tools/mlir-tblgen/RewriterGen.cpp @@ -790,7 +790,7 @@ // values and replacement values, ops in nested patterns, auxiliary ops), we // still need to supply the result types when building the op. But because // we don't generate a builder automatically with ODS for them, it's the - // developer's responsiblity to make sure such a builder (with result type + // developer's responsibility to make sure such a builder (with result type // deduction ability) exists. We go through the separate-parameter builder // here given that it's easier for developers to write compared to // aggregate-parameter builders. diff --git a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp --- a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp +++ b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp @@ -1326,7 +1326,7 @@ static mlir::GenRegistration genCapabilityImplication("gen-spirv-capability-implication", - "Generate utilty function to return implied " + "Generate utility function to return implied " "capabilities for a given capability", [](const RecordKeeper &records, raw_ostream &os) { return emitCapabilityImplication(records, os);