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Change more of the guts of CodeGenRegister's RegUnit tracking to be based on bit vectors.
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Authored by resistor on Jan 30 2015, 10:58 AM.

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chandlerc
Summary

This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case.

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rL LLVM

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resistor updated this revision to Diff 19048.Jan 30 2015, 10:58 AM
resistor retitled this revision from to Change more of the guts of CodeGenRegister's RegUnit tracking to be based on bit vectors..
resistor updated this object.
resistor edited the test plan for this revision. (Show Details)
resistor added a reviewer: chandlerc.
resistor set the repository for this revision to rL LLVM.
resistor added a subscriber: Unknown Object (MLST).
chandlerc edited edge metadata.Jan 30 2015, 11:21 AM

Will look at the code shortly, but can you benchmark a more typical
target's tablegen runs as well just to make sure we're not making a bad
tradeoff here? Similarly, how does it do in debug+asserts builds which are
frustratingly common?

Generally looks fine. Feel free to submit whenever. Minor comments and a question below.

utils/TableGen/CodeGenRegisters.cpp
202

s/changed/Changed

522

range based loop?

utils/TableGen/RegisterInfoEmitter.cpp
576

Why pass by value here? Should this be a const reference?

chandlerc accepted this revision.Jan 30 2015, 9:40 PM
chandlerc edited edge metadata.
This revision is now accepted and ready to land.Jan 30 2015, 9:40 PM