diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -876,7 +876,7 @@ /// /// \return The newly created instruction. MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op, - Optional FLags = None); + Optional Flags = None); /// Build and insert \p Res = G_TRUNC \p Op /// @@ -1377,8 +1377,9 @@ /// Build and insert \p Res = G_FSUB \p Op0, \p Op1 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, - const SrcOp &Src1) { - return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}); + const SrcOp &Src1, + Optional Flags = None) { + return buildInstr(TargetOpcode::G_FSUB, {Dst}, {Src0, Src1}, Flags); } /// Build and insert \p Res = G_FMA \p Op0, \p Op1, \p Op2 diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -316,7 +316,7 @@ Flags = MachineInstr::copyFlagsFromInstruction(I); } // Negate the last operand of the FSUB - MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags); + MIRBuilder.buildFNeg(Res, Op1, Flags); return true; } return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder); @@ -330,7 +330,7 @@ const Instruction &I = cast(U); Flags = MachineInstr::copyFlagsFromInstruction(I); } - MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags); + MIRBuilder.buildFNeg(Res, Op0, Flags); return true; } @@ -353,8 +353,8 @@ Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType()))); else { assert(CI && "Instruction should be CmpInst"); - MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1}, - MachineInstr::copyFlagsFromInstruction(*CI)); + MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, + MachineInstr::copyFlagsFromInstruction(*CI)); } return true; @@ -631,8 +631,7 @@ if (CB.TrueBB == CB.ThisBB->getNextNode()) { std::swap(CB.TrueBB, CB.FalseBB); auto True = MIB.buildConstant(i1Ty, 1); - Cond = MIB.buildInstr(TargetOpcode::G_XOR, {i1Ty}, {Cond, True}, None) - .getReg(0); + Cond = MIB.buildXor(i1Ty, Cond, True).getReg(0); } MIB.buildBrCond(Cond, *CB.TrueBB); @@ -1016,8 +1015,7 @@ Flags = MachineInstr::copyFlagsFromInstruction(*Cmp); for (unsigned i = 0; i < ResRegs.size(); ++i) { - MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]}, - {Tst, Op0Regs[i], Op1Regs[i]}, Flags); + MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); } return true; @@ -1171,8 +1169,8 @@ MachineIRBuilder &MIRBuilder) { const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF)); - auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD); - MIB.addDef(DstReg); + auto MIB = + MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {}); auto &TLI = *MF->getSubtarget().getTargetLowering(); Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent()); @@ -1191,11 +1189,9 @@ bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op, MachineIRBuilder &MIRBuilder) { ArrayRef ResRegs = getOrCreateVRegs(CI); - MIRBuilder.buildInstr(Op) - .addDef(ResRegs[0]) - .addDef(ResRegs[1]) - .addUse(getOrCreateVReg(*CI.getOperand(0))) - .addUse(getOrCreateVReg(*CI.getOperand(1))); + MIRBuilder.buildInstr( + Op, {ResRegs[0], ResRegs[1]}, + {getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))}); return true; } @@ -1369,8 +1365,7 @@ unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8; // FIXME: Get alignment - MIRBuilder.buildInstr(TargetOpcode::G_VASTART) - .addUse(getOrCreateVReg(*Ptr)) + MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)}) .addMemOperand(MF->getMachineMemOperand( MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 1)); return true; @@ -1423,14 +1418,14 @@ TLI.getValueType(*DL, CI.getType()))) { // TODO: Revisit this to see if we should move this part of the // lowering to the combiner. - MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2}, - MachineInstr::copyFlagsFromInstruction(CI)); + MIRBuilder.buildFMA(Dst, Op0, Op1, Op2, + MachineInstr::copyFlagsFromInstruction(CI)); } else { LLT Ty = getLLTForType(*CI.getType(), *DL); - auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1}, - MachineInstr::copyFlagsFromInstruction(CI)); - MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2}, - MachineInstr::copyFlagsFromInstruction(CI)); + auto FMul = MIRBuilder.buildFMul( + Ty, Op0, Op1, MachineInstr::copyFlagsFromInstruction(CI)); + MIRBuilder.buildFAdd(Dst, FMul, Op2, + MachineInstr::copyFlagsFromInstruction(CI)); } return true; } @@ -1508,9 +1503,8 @@ : TargetOpcode::G_CTTZ_ZERO_UNDEF : Cst->isZero() ? TargetOpcode::G_CTLZ : TargetOpcode::G_CTLZ_ZERO_UNDEF; - MIRBuilder.buildInstr(Opcode) - .addDef(getOrCreateVReg(CI)) - .addUse(getOrCreateVReg(*CI.getArgOperand(0))); + MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)}, + {getOrCreateVReg(*CI.getArgOperand(0))}); return true; } case Intrinsic::invariant_start: { @@ -1528,9 +1522,9 @@ return true; case Intrinsic::read_register: { Value *Arg = CI.getArgOperand(0); - MIRBuilder.buildInstr(TargetOpcode::G_READ_REGISTER) - .addDef(getOrCreateVReg(CI)) - .addMetadata(cast(cast(Arg)->getMetadata())); + MIRBuilder + .buildInstr(TargetOpcode::G_READ_REGISTER, {getOrCreateVReg(CI)}, {}) + .addMetadata(cast(cast(Arg)->getMetadata())); return true; } } @@ -1863,10 +1857,9 @@ // we're completely discarding the i64/double distinction here (amongst // others). Fortunately the ABIs I know of where that matters don't use va_arg // anyway but that's not guaranteed. - MIRBuilder.buildInstr(TargetOpcode::G_VAARG) - .addDef(getOrCreateVReg(U)) - .addUse(getOrCreateVReg(*U.getOperand(0))) - .addImm(DL->getABITypeAlignment(U.getType())); + MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)}, + {getOrCreateVReg(*U.getOperand(0)), + uint64_t(DL->getABITypeAlignment(U.getType()))}); return true; } @@ -1936,10 +1929,10 @@ SmallVector Mask; ShuffleVectorInst::getShuffleMask(cast(U.getOperand(2)), Mask); ArrayRef MaskAlloc = MF->allocateShuffleMask(Mask); - MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR) - .addDef(getOrCreateVReg(U)) - .addUse(getOrCreateVReg(*U.getOperand(0))) - .addUse(getOrCreateVReg(*U.getOperand(1))) + MIRBuilder + .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)}, + {getOrCreateVReg(*U.getOperand(0)), + getOrCreateVReg(*U.getOperand(1))}) .addShuffleMask(MaskAlloc); return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -810,12 +810,7 @@ if (MMO.getSizeInBits() == NarrowSize) { MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); } else { - unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD - : TargetOpcode::G_SEXTLOAD; - MIRBuilder.buildInstr(ExtLoad) - .addDef(TmpReg) - .addUse(PtrReg) - .addMemOperand(&MMO); + MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); } if (ZExt) @@ -995,7 +990,7 @@ MachineOperand &MO2 = MI.getOperand(0); Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); - MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt}); + MIRBuilder.buildSExt(MO2.getReg(), DstExt); MO2.setReg(DstExt); Observer.changedInstr(MI); return Legalized; @@ -1042,11 +1037,10 @@ DstRegs.push_back(FullExtensionReg); continue; } - DstRegs.push_back(MIRBuilder - .buildInstr(TargetOpcode::G_ASHR, {NarrowTy}, - {PartialExtensionReg, AshrCstReg}) - ->getOperand(0) - .getReg()); + DstRegs.push_back( + MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) + ->getOperand(0) + .getReg()); FullExtensionReg = DstRegs.back(); } else { DstRegs.push_back( @@ -1101,8 +1095,7 @@ void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx) { MachineOperand &MO = MI.getOperand(OpIdx); - auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy}, - {MO.getReg()}); + auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO.getReg()); MO.setReg(ExtB->getOperand(0).getReg()); } @@ -1435,10 +1428,8 @@ case TargetOpcode::G_USUBO: { if (TypeIdx == 1) return UnableToLegalize; // TODO - auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy}, - {MI.getOperand(2).getReg()}); - auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy}, - {MI.getOperand(3).getReg()}); + auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2).getReg()); + auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3).getReg()); unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO ? TargetOpcode::G_ADD : TargetOpcode::G_SUB; @@ -1446,9 +1437,8 @@ auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext}); LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits()); - auto AndOp = MIRBuilder.buildInstr( - TargetOpcode::G_AND, {WideTy}, - {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())}); + auto AndOp = MIRBuilder.buildAnd( + WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())); // There is no overflow if the AndOp is the same as NewOp. MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp, AndOp); @@ -1491,9 +1481,8 @@ MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { // The correct result is NewOp - (Difference in widety and current ty). unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); - MIBNewOp = MIRBuilder.buildInstr( - TargetOpcode::G_SUB, {WideTy}, - {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)}); + MIBNewOp = MIRBuilder.buildSub( + WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); } MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); @@ -1516,10 +1505,7 @@ LLT Ty = MRI.getType(DstReg); unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); - MIRBuilder.buildInstr(TargetOpcode::G_LSHR) - .addDef(ShrReg) - .addUse(DstExt) - .addUse(ShiftAmtReg); + MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); MIRBuilder.buildTrunc(DstReg, ShrReg); Observer.changedInstr(MI); @@ -1972,10 +1958,9 @@ case TargetOpcode::G_SREM: case TargetOpcode::G_UREM: { Register QuotReg = MRI.createGenericVirtualRegister(Ty); - MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV) - .addDef(QuotReg) - .addUse(MI.getOperand(1).getReg()) - .addUse(MI.getOperand(2).getReg()); + MIRBuilder.buildInstr( + MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg}, + {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()}); Register ProdReg = MRI.createGenericVirtualRegister(Ty); MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg()); @@ -2057,8 +2042,7 @@ auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation); Register SubByReg = MI.getOperand(1).getReg(); Register ZeroReg = Zero->getOperand(0).getReg(); - MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg}, - MI.getFlags()); + MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags()); MI.eraseFromParent(); return Legalized; } @@ -2072,8 +2056,8 @@ Register LHS = MI.getOperand(1).getReg(); Register RHS = MI.getOperand(2).getReg(); Register Neg = MRI.createGenericVirtualRegister(Ty); - MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS); - MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags()); + MIRBuilder.buildFNeg(Neg, RHS); + MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); MI.eraseFromParent(); return Legalized; } @@ -2326,8 +2310,8 @@ Register TmpRes = MRI.createGenericVirtualRegister(DstTy); auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); - MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()}); - MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()}); + MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0).getReg()); + MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0).getReg()); MI.eraseFromParent(); return Legalized; } @@ -2597,9 +2581,8 @@ for (unsigned I = 0; I < NumParts; ++I) { Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); - MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode()) - .addDef(DstReg) - .addUse(SrcRegs[I]); + MachineInstr *NewInst = + MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); NewInst->setFlags(MI.getFlags()); DstRegs.push_back(DstReg); @@ -3769,8 +3752,7 @@ unsigned Len = Ty.getSizeInBits(); if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) { // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. - auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF, - {Ty}, {SrcReg}); + auto MIBCtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(Ty, SrcReg); auto MIBZero = MIRBuilder.buildConstant(Ty, 0); auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), @@ -3795,15 +3777,13 @@ unsigned NewLen = PowerOf2Ceil(Len); for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i); - auto MIBOp = MIRBuilder.buildInstr( - TargetOpcode::G_OR, {Ty}, - {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty}, - {Op, MIBShiftAmt})}); + auto MIBOp = + MIRBuilder.buildOr(Ty, Op, MIRBuilder.buildLShr(Ty, Op, MIBShiftAmt)); Op = MIBOp->getOperand(0).getReg(); } - auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op}); - MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()}, - {MIRBuilder.buildConstant(Ty, Len), MIBPop}); + auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op); + MIRBuilder.buildSub(MI.getOperand(0).getReg(), + MIRBuilder.buildConstant(Ty, Len), MIBPop); MI.eraseFromParent(); return Legalized; } @@ -3820,8 +3800,7 @@ if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) { // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with // zero. - auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF, - {Ty}, {SrcReg}); + auto MIBCttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(Ty, SrcReg); auto MIBZero = MIRBuilder.buildConstant(Ty, 0); auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), @@ -3836,19 +3815,14 @@ // { return 32 - nlz(~x & (x-1)); } // Ref: "Hacker's Delight" by Henry Warren auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1); - auto MIBNot = - MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1}); - auto MIBTmp = MIRBuilder.buildInstr( - TargetOpcode::G_AND, {Ty}, - {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty}, - {SrcReg, MIBCstNeg1})}); + auto MIBNot = MIRBuilder.buildXor(Ty, SrcReg, MIBCstNeg1); + auto MIBTmp = MIRBuilder.buildAnd( + Ty, MIBNot, MIRBuilder.buildAdd(Ty, SrcReg, MIBCstNeg1)); if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) && isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) { auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len); - MIRBuilder.buildInstr( - TargetOpcode::G_SUB, {MI.getOperand(0).getReg()}, - {MIBCstLen, - MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})}); + MIRBuilder.buildSub(MI.getOperand(0).getReg(), MIBCstLen, + MIRBuilder.buildCTLZ(Ty, MIBTmp)); MI.eraseFromParent(); return Legalized; }