Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -909,6 +909,15 @@ } // hasSideEffects = 0 } // End FXU Operations. +def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; +def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>; +def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; +def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>; +def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; +def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>; + +def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>; +def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>; //===----------------------------------------------------------------------===// // Load/Store instructions. Index: llvm/test/CodeGen/PowerPC/bperm.ll =================================================================== --- llvm/test/CodeGen/PowerPC/bperm.ll +++ llvm/test/CodeGen/PowerPC/bperm.ll @@ -9,7 +9,7 @@ ret i32 %0 ; CHECK-LABEL: @bs4 -; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31 +; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23 ; CHECK: rlwimi [[REG1]], 3, 24, 0, 7 ; CHECK: mr 3, [[REG1]] Index: llvm/test/CodeGen/PowerPC/pr44183.ll =================================================================== --- llvm/test/CodeGen/PowerPC/pr44183.ll +++ llvm/test/CodeGen/PowerPC/pr44183.ll @@ -16,7 +16,7 @@ ; CHECK-NEXT: lwz r5, 36(r30) ; CHECK-NEXT: rldicl r4, r4, 60, 4 ; CHECK-NEXT: rlwinm r3, r4, 31, 0, 0 -; CHECK-NEXT: rlwinm r4, r5, 0, 31, 31 +; CHECK-NEXT: clrlwi r4, r5, 31 ; CHECK-NEXT: or r4, r4, r3 ; CHECK-NEXT: bl _ZN1llsE1d ; CHECK-NEXT: nop Index: llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll =================================================================== --- llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll +++ llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll @@ -15,7 +15,7 @@ ; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: lis r5, 21399 ; P9LE-NEXT: ori r5, r5, 33437 -; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 +; P9LE-NEXT: clrlwi r4, r3, 16 ; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: lis r5, 16727 ; P9LE-NEXT: ori r5, r5, 2287 @@ -25,7 +25,7 @@ ; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: vextuhrx r3, r3, v2 -; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 +; P9LE-NEXT: clrlwi r4, r3, 16 ; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: lis r5, 8456 ; P9LE-NEXT: ori r5, r5, 16913 @@ -136,9 +136,9 @@ ; P8LE-NEXT: rldicl r9, r4, 32, 48 ; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31 ; P8LE-NEXT: rldicl r10, r4, 16, 48 -; P8LE-NEXT: rlwinm r11, r9, 0, 16, 31 +; P8LE-NEXT: clrlwi r11, r9, 16 ; P8LE-NEXT: clrldi r7, r6, 32 -; P8LE-NEXT: rlwinm r12, r10, 0, 16, 31 +; P8LE-NEXT: clrlwi r12, r10, 16 ; P8LE-NEXT: mulld r3, r7, r3 ; P8LE-NEXT: lis r7, 16727 ; P8LE-NEXT: ori r7, r7, 2287 @@ -980,7 +980,7 @@ ; P9LE-NEXT: oris r5, r5, 51306 ; P9LE-NEXT: ori r6, r6, 17097 ; P9LE-NEXT: ori r5, r5, 30865 -; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 +; P9LE-NEXT: clrlwi r4, r3, 16 ; P9LE-NEXT: mulld r4, r4, r6 ; P9LE-NEXT: lis r6, 24749 ; P9LE-NEXT: ori r6, r6, 47143 @@ -990,7 +990,7 @@ ; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: vextuhrx r3, r3, v2 -; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 +; P9LE-NEXT: clrlwi r4, r3, 16 ; P9LE-NEXT: mulld r4, r4, r6 ; P9LE-NEXT: rldicl r4, r4, 21, 43 ; P9LE-NEXT: mulli r4, r4, 5423 @@ -1074,10 +1074,10 @@ ; P8LE-NEXT: mfvsrd r4, f0 ; P8LE-NEXT: rldicl r6, r4, 32, 48 ; P8LE-NEXT: rldicl r7, r4, 16, 48 -; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31 +; P8LE-NEXT: clrlwi r9, r6, 16 ; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: mulld r5, r9, r5 -; P8LE-NEXT: rlwinm r9, r7, 0, 16, 31 +; P8LE-NEXT: clrlwi r9, r7, 16 ; P8LE-NEXT: mulld r8, r9, r8 ; P8LE-NEXT: rlwinm r9, r4, 31, 17, 31 ; P8LE-NEXT: mulld r3, r9, r3