diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -1138,6 +1138,7 @@
   let Inst{8} = 0b0;
   let Inst{6} = 0b1;
   let Inst{4} = bit_4;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VMINMAX_m<string iname, bit bit_4, MVEVectorVTInfo VTI,
@@ -2298,6 +2299,7 @@
   let Inst{4} = 0b0;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+  let validForTailPredication = 1;
 }
 
 def MVE_VMAXAs8  : MVE_VMINMAXA<"vmaxa", "s8",  0b00, 0b0>;
diff --git a/llvm/unittests/Target/ARM/MachineInstrTest.cpp b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
--- a/llvm/unittests/Target/ARM/MachineInstrTest.cpp
+++ b/llvm/unittests/Target/ARM/MachineInstrTest.cpp
@@ -149,6 +149,24 @@
     case MVE_VFMA_qr_Sf32:
     case MVE_VFMA_qr_f16:
     case MVE_VFMA_qr_f32:
+    case MVE_VMAXAs16:
+    case MVE_VMAXAs32:
+    case MVE_VMAXAs8:
+    case MVE_VMAXs16:
+    case MVE_VMAXs32:
+    case MVE_VMAXs8:
+    case MVE_VMAXu16:
+    case MVE_VMAXu32:
+    case MVE_VMAXu8:
+    case MVE_VMINAs16:
+    case MVE_VMINAs32:
+    case MVE_VMINAs8:
+    case MVE_VMINs16:
+    case MVE_VMINs32:
+    case MVE_VMINs8:
+    case MVE_VMINu16:
+    case MVE_VMINu32:
+    case MVE_VMINu8:
     case MVE_VMLAS_qr_s16:
     case MVE_VMLAS_qr_s32:
     case MVE_VMLAS_qr_s8: