Index: llvm/include/llvm/IR/IntrinsicsAArch64.td =================================================================== --- llvm/include/llvm/IR/IntrinsicsAArch64.td +++ llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -1542,6 +1542,13 @@ def int_aarch64_sve_and_z : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_bic_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_brka : AdvSIMD_Merged1VectorArg_Intrinsic; +def int_aarch64_sve_brka_z : AdvSIMD_Pred1VectorArg_Intrinsic; +def int_aarch64_sve_brkb : AdvSIMD_Merged1VectorArg_Intrinsic; +def int_aarch64_sve_brkb_z : AdvSIMD_Pred1VectorArg_Intrinsic; +def int_aarch64_sve_brkn_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_brkpa_z : AdvSIMD_Pred2VectorArg_Intrinsic; +def int_aarch64_sve_brkpb_z : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_eor_z : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_nand_z : AdvSIMD_Pred2VectorArg_Intrinsic; def int_aarch64_sve_nor_z : AdvSIMD_Pred2VectorArg_Intrinsic; Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -287,20 +287,20 @@ def MOVPRFX_ZZ : sve_int_bin_cons_misc_0_c<0b00000001, "movprfx", ZPRAny>; defm FEXPA_ZZ : sve_int_bin_cons_misc_0_c_fexpa<"fexpa", int_aarch64_sve_fexpa_x>; - def BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa">; - def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">; - def BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb">; - def BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs">; - - def BRKN_PPzP : sve_int_brkn<0b0, "brkn">; - def BRKNS_PPzP : sve_int_brkn<0b1, "brkns">; - - defm BRKA_PPzP : sve_int_break_z<0b000, "brka">; - defm BRKA_PPmP : sve_int_break_m<0b001, "brka">; - defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">; - defm BRKB_PPzP : sve_int_break_z<0b100, "brkb">; - defm BRKB_PPmP : sve_int_break_m<0b101, "brkb">; - defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">; + defm BRKPA_PPzPP : sve_int_brkp<0b00, "brkpa", int_aarch64_sve_brkpa_z>; + defm BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas", null_frag>; + defm BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb", int_aarch64_sve_brkpb_z>; + defm BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs", null_frag>; + + defm BRKN_PPzP : sve_int_brkn<0b0, "brkn", int_aarch64_sve_brkn_z>; + defm BRKNS_PPzP : sve_int_brkn<0b1, "brkns", null_frag>; + + defm BRKA_PPzP : sve_int_break_z<0b000, "brka", int_aarch64_sve_brka_z>; + defm BRKA_PPmP : sve_int_break_m<0b001, "brka", int_aarch64_sve_brka>; + defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas", null_frag>; + defm BRKB_PPzP : sve_int_break_z<0b100, "brkb", int_aarch64_sve_brkb_z>; + defm BRKB_PPmP : sve_int_break_m<0b101, "brkb", int_aarch64_sve_brkb>; + defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs", null_frag>; def PTEST_PP : sve_int_ptest<0b010000, "ptest">; def PFALSE : sve_int_pfalse<0b000000, "pfalse">; Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -6571,6 +6571,12 @@ let Defs = !if(!eq (opc{1}, 1), [NZCV], []); } +multiclass sve_int_brkp opc, string asm, SDPatternOperator op> { + def NAME : sve_int_brkp; + + def : SVE_3_Op_Pat(NAME)>; +} + //===----------------------------------------------------------------------===// // SVE Partition Break Group @@ -6597,6 +6603,12 @@ let Defs = !if(!eq (S, 0b1), [NZCV], []); } +multiclass sve_int_brkn opc, string asm, SDPatternOperator op> { + def NAME : sve_int_brkn; + + def : SVE_3_Op_Pat(NAME)>; +} + class sve_int_break opc, string asm, string suffix, dag iops> : I<(outs PPR8:$Pd), iops, asm, "\t$Pd, $Pg"#suffix#", $Pn", @@ -6619,12 +6631,16 @@ } -multiclass sve_int_break_m opc, string asm> { +multiclass sve_int_break_m opc, string asm, SDPatternOperator op> { def NAME : sve_int_break; + + def : SVE_3_Op_Pat(NAME)>; } -multiclass sve_int_break_z opc, string asm> { +multiclass sve_int_break_z opc, string asm, SDPatternOperator op> { def NAME : sve_int_break; + + def : SVE_2_Op_Pat(NAME)>; } //===----------------------------------------------------------------------===// Index: llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll =================================================================== --- llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll +++ llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll @@ -1,6 +1,95 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s ; +; BRKA +; + +define @brka_m_b8( %inactive, %pg, %a) { +; CHECK-LABEL: brka_m_b8: +; CHECK: brka p0.b, p1/m, p2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brka.nxv16i1( %inactive, + %pg, + %a) + ret %out +} + +define @brka_z_b8( %pg, %a) { +; CHECK-LABEL: brka_z_b8: +; CHECK: brka p0.b, p0/z, p1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brka.z.nxv16i1( %pg, + %a) + ret %out +} + +; +; BRKB +; + +define @brkb_m_b8( %inactive, %pg, %a) { +; CHECK-LABEL: brkb_m_b8: +; CHECK: brkb p0.b, p1/m, p2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brkb.nxv16i1( %inactive, + %pg, + %a) + ret %out +} + +define @brkb_z_b8( %pg, %a) { +; CHECK-LABEL: brkb_z_b8: +; CHECK: brkb p0.b, p0/z, p1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brkb.z.nxv16i1( %pg, + %a) + ret %out +} + +; +; BRKN +; + +define @brkn_b8( %pg, %a, %b) { +; CHECK-LABEL: brkn_b8: +; CHECK: brkn p2.b, p0/z, p1.b, p2.b +; CHECK-NEXT: mov p0.b, p2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brkn.z.nxv16i1( %pg, + %a, + %b) + ret %out +} + +; +; BRKPA +; + +define @brkpa_b8( %pg, %a, %b) { +; CHECK-LABEL: brkpa_b8: +; CHECK: brkpa p0.b, p0/z, p1.b, p2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brkpa.z.nxv16i1( %pg, + %a, + %b) + ret %out +} + +; +; BRKPB +; + +define @brkpb_b8( %pg, %a, %b) { +; CHECK-LABEL: brkpb_b8: +; CHECK: brkpb p0.b, p0/z, p1.b, p2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.brkpb.z.nxv16i1( %pg, + %a, + %b) + ret %out +} + +; ; PFIRST ; @@ -114,6 +203,14 @@ ret %res } +declare @llvm.aarch64.sve.brka.nxv16i1(, , ) +declare @llvm.aarch64.sve.brka.z.nxv16i1(, ) +declare @llvm.aarch64.sve.brkb.nxv16i1(, , ) +declare @llvm.aarch64.sve.brkb.z.nxv16i1(, ) +declare @llvm.aarch64.sve.brkn.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.brkpa.z.nxv16i1(, , ) +declare @llvm.aarch64.sve.brkpb.z.nxv16i1(, , ) + declare @llvm.aarch64.sve.pfirst.nxv16i1(, ) declare @llvm.aarch64.sve.pnext.nxv16i1(, )