Index: llvm/test/CodeGen/PowerPC/vshasigmaw.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/vshasigmaw.ll
@@ -0,0 +1,96 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 %s -o - | \
+; RUN:   FileCheck --check-prefix=CHECK-P8 %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -ppc-asm-full-reg-names -mcpu=pwr7 %s -o - | \
+; RUN:   FileCheck --check-prefix=CHECK-P7 %s
+
+define dso_local <4 x i32> @Sigma(<4 x i32> %a) local_unnamed_addr {
+; CHECK-P8-LABEL: Sigma:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    vshasigmaw v2, v2, 1, 6
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P7-LABEL: Sigma:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    addis r3, r2, .LCPI0_1@toc@ha
+; CHECK-P7-NEXT:    addis r4, r2, .LCPI0_2@toc@ha
+; CHECK-P7-NEXT:    addi r3, r3, .LCPI0_1@toc@l
+; CHECK-P7-NEXT:    lvx v3, 0, r3
+; CHECK-P7-NEXT:    addi r3, r4, .LCPI0_2@toc@l
+; CHECK-P7-NEXT:    lvx v4, 0, r3
+; CHECK-P7-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-P7-NEXT:    addi r3, r3, .LCPI0_0@toc@l
+; CHECK-P7-NEXT:    vrlw v3, v2, v3
+; CHECK-P7-NEXT:    lvx v5, 0, r3
+; CHECK-P7-NEXT:    vrlw v4, v2, v4
+; CHECK-P7-NEXT:    vrlw v2, v2, v5
+; CHECK-P7-NEXT:    xxlxor vs0, vs36, vs35
+; CHECK-P7-NEXT:    xxlxor vs34, vs0, vs34
+; CHECK-P7-NEXT:    blr
+entry:
+  %0 = lshr <4 x i32> %a, <i32 2, i32 6, i32 6, i32 2>
+  %1 = shl <4 x i32> %a, <i32 30, i32 26, i32 26, i32 30>
+  %2 = or <4 x i32> %0, %1
+  %3 = lshr <4 x i32> %a, <i32 13, i32 11, i32 11, i32 13>
+  %4 = shl <4 x i32> %a, <i32 19, i32 21, i32 21, i32 19>
+  %5 = or <4 x i32> %3, %4
+  %6 = lshr <4 x i32> %a, <i32 22, i32 25, i32 25, i32 22>
+  %7 = shl <4 x i32> %a, <i32 10, i32 7, i32 7, i32 10>
+  %8 = or <4 x i32> %6, %7
+  %9 = xor <4 x i32> %8, %5
+  %10 = xor <4 x i32> %9, %2
+  ret <4 x i32> %10
+}
+
+define dso_local <4 x i32> @Gamma(<4 x i32> %a) local_unnamed_addr {
+; CHECK-P8-LABEL: Gamma:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-P8-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-P8-NEXT:    lvx v3, 0, r3
+; CHECK-P8-NEXT:    addi r3, r4, .LCPI1_1@toc@l
+; CHECK-P8-NEXT:    lvx v4, 0, r3
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI1_2@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI1_2@toc@l
+; CHECK-P8-NEXT:    vrlw v3, v2, v3
+; CHECK-P8-NEXT:    vrlw v4, v2, v4
+; CHECK-P8-NEXT:    lvx v5, 0, r3
+; CHECK-P8-NEXT:    vrlw v2, v2, v5
+; CHECK-P8-NEXT:    xxlxor vs0, vs35, vs36
+; CHECK-P8-NEXT:    xxlxor vs34, vs0, vs34
+; CHECK-P8-NEXT:    blr
+;
+; CHECK-P7-LABEL: Gamma:
+; CHECK-P7:       # %bb.0: # %entry
+; CHECK-P7-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
+; CHECK-P7-NEXT:    addis r4, r2, .LCPI1_1@toc@ha
+; CHECK-P7-NEXT:    addi r3, r3, .LCPI1_0@toc@l
+; CHECK-P7-NEXT:    lvx v3, 0, r3
+; CHECK-P7-NEXT:    addi r3, r4, .LCPI1_1@toc@l
+; CHECK-P7-NEXT:    lvx v4, 0, r3
+; CHECK-P7-NEXT:    addis r3, r2, .LCPI1_2@toc@ha
+; CHECK-P7-NEXT:    addi r3, r3, .LCPI1_2@toc@l
+; CHECK-P7-NEXT:    vrlw v3, v2, v3
+; CHECK-P7-NEXT:    vrlw v4, v2, v4
+; CHECK-P7-NEXT:    lvx v5, 0, r3
+; CHECK-P7-NEXT:    vrlw v2, v2, v5
+; CHECK-P7-NEXT:    xxlxor vs0, vs35, vs36
+; CHECK-P7-NEXT:    xxlxor vs34, vs0, vs34
+; CHECK-P7-NEXT:    blr
+entry:
+  %0 = lshr <4 x i32> %a, <i32 7, i32 18, i32 3, i32 17>
+  %1 = shl <4 x i32> %a, <i32 25, i32 14, i32 29, i32 15>
+  %2 = or <4 x i32> %0, %1
+  %3 = lshr <4 x i32> %a, <i32 3, i32 7, i32 18, i32 19>
+  %4 = shl <4 x i32> %a, <i32 29, i32 25, i32 14, i32 13>
+  %5 = or <4 x i32> %3, %4
+  %6 = lshr <4 x i32> %a, <i32 18, i32 3, i32 7, i32 10>
+  %7 = shl <4 x i32> %a, <i32 14, i32 29, i32 25, i32 22>
+  %8 = or <4 x i32> %6, %7
+  %9 = xor <4 x i32> %2, %5
+  %10 = xor <4 x i32> %9, %8
+  ret <4 x i32> %10
+}