diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td
--- a/llvm/lib/Target/BPF/BPF.td
+++ b/llvm/lib/Target/BPF/BPF.td
@@ -21,6 +21,7 @@
 def : Proc<"v1", []>;
 def : Proc<"v2", []>;
 def : Proc<"v3", []>;
+def : Proc<"v4", []>;
 def : Proc<"probe", []>;
 
 def DummyFeature : SubtargetFeature<"dummy", "isDummyMode",
diff --git a/llvm/lib/Target/BPF/BPFInstrFormats.td b/llvm/lib/Target/BPF/BPFInstrFormats.td
--- a/llvm/lib/Target/BPF/BPFInstrFormats.td
+++ b/llvm/lib/Target/BPF/BPFInstrFormats.td
@@ -86,7 +86,15 @@
 def BPF_ABS  : BPFModeModifer<0x1>;
 def BPF_IND  : BPFModeModifer<0x2>;
 def BPF_MEM  : BPFModeModifer<0x3>;
-def BPF_XADD : BPFModeModifer<0x6>;
+def BPF_XMEM : BPFModeModifer<0x6>;
+
+class BPFXMemOp<bits<8> val> {
+  bits<8> Value = val;
+}
+
+def BPF_XADD    : BPFXMemOp<0x0>;
+def BPF_XCHG    : BPFXMemOp<0x1>;
+def BPF_CMPXCHG : BPFXMemOp<0x2>;
 
 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
   : Instruction {
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td
--- a/llvm/lib/Target/BPF/BPFInstrInfo.td
+++ b/llvm/lib/Target/BPF/BPFInstrInfo.td
@@ -53,6 +53,7 @@
 def BPFIsBigEndian    : Predicate<"!CurDAG->getDataLayout().isLittleEndian()">;
 def BPFHasALU32 : Predicate<"Subtarget->getHasAlu32()">;
 def BPFNoALU32 : Predicate<"!Subtarget->getHasAlu32()">;
+def BPFHasAtomicExt : Predicate<"Subtarget->getHasAtomicExt()">;
 
 def brtarget : Operand<OtherVT> {
   let PrintMethod = "printBrTargetOperand";
@@ -617,9 +618,9 @@
   def : Pat<(i64 (extloadi32 ADDRri:$src)), (i64 (LDW ADDRri:$src))>;
 }
 
-// Atomics
+// Atomic XADD
 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
-    : TYPE_LD_ST<BPF_XADD.Value, SizeOp.Value,
+    : TYPE_LD_ST<BPF_XMEM.Value, SizeOp.Value,
                  (outs GPR:$dst),
                  (ins MEMri:$addr, GPR:$val),
                  "lock *("#OpcodeStr#" *)($addr) += $val",
@@ -630,11 +631,12 @@
   let Inst{51-48} = addr{19-16}; // base reg
   let Inst{55-52} = dst;
   let Inst{47-32} = addr{15-0}; // offset
+  let Inst{7-0} = BPF_XADD.Value;
   let BPFClass = BPF_STX;
 }
 
 class XADD32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
-    : TYPE_LD_ST<BPF_XADD.Value, SizeOp.Value,
+    : TYPE_LD_ST<BPF_XMEM.Value, SizeOp.Value,
                  (outs GPR32:$dst),
                  (ins MEMri:$addr, GPR32:$val),
                  "lock *("#OpcodeStr#" *)($addr) += $val",
@@ -645,6 +647,7 @@
   let Inst{51-48} = addr{19-16}; // base reg
   let Inst{55-52} = dst;
   let Inst{47-32} = addr{15-0}; // offset
+  let Inst{7-0} = BPF_XADD.Value;
   let BPFClass = BPF_STX;
 }
 
@@ -660,6 +663,108 @@
   def XADDD : XADD<BPF_DW, "u64", atomic_load_add_64>;
 }
 
+// Atomic Exchange
+class XCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
+    : TYPE_LD_ST<BPF_XMEM.Value, SizeOp.Value,
+                 (outs GPR:$dst),
+                 (ins MEMri:$addr, GPR:$val),
+                 "$dst = xchg_"#OpcodeStr#"($addr, $val)",
+                 [(set GPR:$dst, (OpNode ADDRri:$addr,GPR:$val))]> {
+  bits<4> dst;
+  bits<20> addr;
+
+  let Inst{51-48} = addr{19-16}; // base reg
+  let Inst{55-52} = dst;
+  let Inst{47-32} = addr{15-0}; // offset
+  let Inst{7-0} = BPF_XCHG.Value;
+  let BPFClass = BPF_STX;
+}
+
+class XCHG32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
+    : TYPE_LD_ST<BPF_XMEM.Value, SizeOp.Value,
+                 (outs GPR32:$dst),
+                 (ins MEMri:$addr, GPR32:$val),
+                 "$dst = xchg32_"#OpcodeStr#"($addr, $val)",
+                 [(set GPR32:$dst, (OpNode ADDRri:$addr,GPR32:$val))]> {
+  bits<4> dst;
+  bits<20> addr;
+
+  let Inst{51-48} = addr{19-16}; // base reg
+  let Inst{55-52} = dst;
+  let Inst{47-32} = addr{15-0}; // offset
+  let Inst{7-0} = BPF_XCHG.Value;
+  let BPFClass = BPF_STX;
+}
+
+let Predicates = [BPFHasAtomicExt], Constraints = "$dst = $val" in {
+    let Predicates = [BPFNoALU32] in {
+      def XCHGB : XCHG<BPF_B, "u8", atomic_swap_8>;
+      def XCHGH : XCHG<BPF_H, "u16", atomic_swap_16>;
+      def XCHGW : XCHG<BPF_W, "u32", atomic_swap_32>;
+    }
+
+    let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
+      def XCHGB32 : XCHG32<BPF_B, "u8", atomic_swap_8>;
+      def XCHGH32 : XCHG32<BPF_H, "u16", atomic_swap_16>;
+      def XCHGW32 : XCHG32<BPF_W, "u32", atomic_swap_32>;
+    }
+
+    def XCHGD : XCHG<BPF_DW, "xchg_u64", atomic_swap_64>;
+}
+
+// Compare-And-Exchange
+class CMPXCHG<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
+    : TYPE_LD_ST<BPF_XMEM.Value, SizeOp.Value,
+                 (outs GPR:$dst),
+                 (ins MEMri:$addr, GPR:$old, GPR:$new),
+                 "$dst = cmpxchg_"#OpcodeStr#"($addr, $old, $new)",
+                 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$old, GPR:$new))]> {
+  bits<4> dst;
+  bits<20> addr;
+  bits<4> new;
+
+  let Inst{51-48} = addr{19-16}; // base reg
+  let Inst{55-52} = dst;
+  let Inst{47-32} = addr{15-0}; // offset
+  let Inst{11-8} = new;
+  let Inst{7-0} = BPF_CMPXCHG.Value;
+  let BPFClass = BPF_STX;
+}
+
+class CMPXCHG32<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
+    : TYPE_LD_ST<BPF_XMEM.Value, SizeOp.Value,
+                 (outs GPR32:$dst),
+                 (ins MEMri:$addr, GPR32:$old, GPR32:$new),
+                 "$dst = cmpxchg32_"#OpcodeStr#"($addr, $old, $new)",
+                 [(set GPR32:$dst, (OpNode ADDRri:$addr, GPR32:$old, GPR32:$new))]> {
+  bits<4> dst;
+  bits<20> addr;
+  bits<4> new;
+
+  let Inst{51-48} = addr{19-16}; // base reg
+  let Inst{55-52} = dst;
+  let Inst{47-32} = addr{15-0}; // offset
+  let Inst{11-8} = new;
+  let Inst{7-0} = BPF_CMPXCHG.Value;
+  let BPFClass = BPF_STX;
+}
+
+let Predicates = [BPFHasAtomicExt], Constraints = "$dst = $old" in {
+    let Predicates = [BPFNoALU32] in {
+      def CMPXCHGB : CMPXCHG<BPF_B, "u8", atomic_cmp_swap_8>;
+      def CMPXCHGH : CMPXCHG<BPF_H, "u16", atomic_cmp_swap_16>;
+      def CMPXCHGW : CMPXCHG<BPF_W, "u32", atomic_cmp_swap_32>;
+    }
+
+    let Predicates = [BPFHasALU32], DecoderNamespace = "BPFALU32" in {
+      def CMPXCHGB32 : CMPXCHG32<BPF_B, "u8", atomic_cmp_swap_8>;
+      def CMPXCHGH32 : CMPXCHG32<BPF_H, "u16", atomic_cmp_swap_16>;
+      def CMPXCHGW32 : CMPXCHG32<BPF_W, "u32", atomic_cmp_swap_32>;
+    }
+
+    def CMPXCHGD : CMPXCHG<BPF_DW, "u64", atomic_cmp_swap_64>;
+}
+
 // bswap16, bswap32, bswap64
 class BSWAP<bits<32> SizeOp, string OpcodeStr, BPFSrcType SrcType, list<dag> Pattern>
     : TYPE_ALU_JMP<BPF_END.Value, SrcType.Value,
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.h b/llvm/lib/Target/BPF/BPFSubtarget.h
--- a/llvm/lib/Target/BPF/BPFSubtarget.h
+++ b/llvm/lib/Target/BPF/BPFSubtarget.h
@@ -57,6 +57,9 @@
   // whether we should enable MCAsmInfo DwarfUsesRelocationsAcrossSections
   bool UseDwarfRIS;
 
+  // whether the cpu supports extended atomic operations.
+  bool HasAtomicExt;
+
 public:
   // This constructor initializes the data members to match that
   // of the specified triple.
@@ -72,6 +75,7 @@
   bool getHasJmp32() const { return HasJmp32; }
   bool getHasAlu32() const { return HasAlu32; }
   bool getUseDwarfRIS() const { return UseDwarfRIS; }
+  bool getHasAtomicExt() const { return HasAtomicExt; }
 
   const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const BPFFrameLowering *getFrameLowering() const override {
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp
--- a/llvm/lib/Target/BPF/BPFSubtarget.cpp
+++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp
@@ -38,9 +38,14 @@
   HasJmp32 = false;
   HasAlu32 = false;
   UseDwarfRIS = false;
+  HasAtomicExt = false;
 }
 
 void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
+#if 1
+  // Set to support AtomicExt for development purpose
+  HasAtomicExt = true;
+#endif
   if (CPU == "probe")
     CPU = sys::detail::getHostCPUNameForBPF();
   if (CPU == "generic" || CPU == "v1")
@@ -55,6 +60,13 @@
     HasAlu32 = true;
     return;
   }
+  if (CPU == "v4") {
+    HasJmpExt = true;
+    HasJmp32 = true;
+    HasAlu32 = true;
+    HasAtomicExt = true;
+    return;
+  }
 }
 
 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
diff --git a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
--- a/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
+++ b/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp
@@ -58,7 +58,7 @@
     BPF_MEM = 0x3,
     BPF_LEN = 0x4,
     BPF_MSH = 0x5,
-    BPF_XADD = 0x6
+    BPF_XMEM = 0x6
   };
 
   BPFDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
@@ -175,7 +175,7 @@
   uint8_t InstMode = getInstMode(Insn);
   if ((InstClass == BPF_LDX || InstClass == BPF_STX) &&
       getInstSize(Insn) != BPF_DW &&
-      (InstMode == BPF_MEM || InstMode == BPF_XADD) &&
+      (InstMode == BPF_MEM || InstMode == BPF_XMEM) &&
       STI.getFeatureBits()[BPF::ALU32])
     Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address,
                                this, STI);