diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
@@ -127,7 +127,9 @@
   if (!MCAI->useIntegratedAssembler() &&
       !OutStreamer->isIntegratedAssemblerRequired()) {
     emitInlineAsmStart();
+    OutStreamer->emitRawComment(MAI->getInlineAsmStart());
     OutStreamer->EmitRawText(Str);
+    OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
     emitInlineAsmEnd(STI, nullptr);
     return;
   }
@@ -158,10 +160,22 @@
   if (Dialect == InlineAsm::AD_Intel)
     Parser->getLexer().setLexMasmIntegers(true);
 
+  // Emit target-specific directives before inline asm.
   emitInlineAsmStart();
+
+  // Emit the #APP start marker.  This has to happen even if verbose-asm isn't
+  // enabled, so we use emitRawComment.
+  OutStreamer->emitRawComment(MAI->getInlineAsmStart());
+
   // Don't implicitly switch to the text section before the asm.
   int Res = Parser->Run(/*NoInitialTextSection*/ true,
                         /*NoFinalize*/ true);
+
+  // Emit the #NOAPP end marker.  This has to happen even if verbose-asm isn't
+  // enabled, so we use emitRawComment.
+  OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
+
+  // Emit target-specific directives after inline asm.
   emitInlineAsmEnd(STI, &TAP->getSTI());
 
   if (Res && !DiagInfo->DiagHandler)
@@ -516,10 +530,6 @@
     return;
   }
 
-  // Emit the #APP start marker.  This has to happen even if verbose-asm isn't
-  // enabled, so we use emitRawComment.
-  OutStreamer->emitRawComment(MAI->getInlineAsmStart());
-
   // Get the !srcloc metadata node if we have it, and decode the loc cookie from
   // it.
   unsigned LocCookie = 0;
@@ -589,10 +599,6 @@
 
   EmitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
                 MI->getInlineAsmDialect());
-
-  // Emit the #NOAPP end marker.  This has to happen even if verbose-asm isn't
-  // enabled, so we use emitRawComment.
-  OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
 }
 
 
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -846,12 +846,10 @@
   TS.emitDirectiveSetAt();
   TS.emitDirectiveSetMacro();
   TS.emitDirectiveSetReorder();
-  OutStreamer->AddBlankLine();
 }
 
 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
                                       const MCSubtargetInfo *EndInfo) const {
-  OutStreamer->AddBlankLine();
   getTargetStreamer().emitDirectiveSetPop();
 }
 
diff --git a/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll b/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
--- a/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll
@@ -4,15 +4,15 @@
 ; after the inline assembly code.
 define void @f() nounwind {
 entry:
-; CHECK:      #APP
-; CHECK-NEXT: .set  push
+; CHECK: .set  push
 ; CHECK-NEXT: .set  at
 ; CHECK-NEXT: .set  macro
 ; CHECK-NEXT: .set  reorder
+; CHECK-NEXT:      #APP
 ; CHECK:      addi $9, ${{[2-9][0-9]?}}, 8
 ; CHECK:      ori ${{[2-9][0-9]?}}, $9, 6
-; CHECK:      .set  pop
-; CHECK-NEXT: #NO_APP
+; CHECK: #NO_APP
+; CHECK-NEXT:      .set  pop
   %a = alloca i32, align 4
   %b = alloca i32, align 4
   store i32 20, i32* %a, align 4
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll
@@ -7,46 +7,46 @@
 entry:
 
 ; r with char
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
-;CHECK: #NO_APP
+;CHECK:      #APP
+;CHECK-NEXT: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
+;CHECK-NEXT: #NO_APP
   tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind
 
 ; r with short
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
-;CHECK: #NO_APP
+;CHECK:      #APP
+;CHECK-NEXT: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
+;CHECK-NEXT: #NO_APP
   tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind
 
 ; r with int
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
-;CHECK: #NO_APP
+;CHECK:      #APP
+;CHECK-NEXT: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
+;CHECK-NEXT: #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind
 
 ; Now c with 1024: make sure register $25 is picked
-; CHECK: #APP
-; CHECK: addiu $25, ${{[0-9]+}}, 1024
-; CHECK: #NO_APP
+; CHECK:      #APP
+; CHECK-NEXT: addiu $25, ${{[0-9]+}}, 1024
+; CHECK-NEXT: #NO_APP
    tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind
 
 ; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
 ; after the inline expression for a mflo to pull the value out of lo.
 ; CHECK:       #APP
-; CHECK:       mtlo ${{[0-9]+}}
+; CHECK-NEXT:  mtlo ${{[0-9]+}}
 ; CHECK-NEXT:  madd ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK:       #NO_APP
-; CHECK-NEXT:  mflo ${{[0-9]+}}
+; CHECK-NEXT:  #NO_APP
+; CHECK:       mflo ${{[0-9]+}}
   %bosco = alloca i32, align 4
   call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
   store volatile i32 %4, i32* %bosco, align 4
  
 ; Check the 'l' constraint for 16-bit type.
 ; CHECK:       #APP
-; CHECK:       mtlo ${{[0-9]+}}
+; CHECK-NEXT:  mtlo ${{[0-9]+}}
 ; CHECK-NEXT:  madd ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK:       #NO_APP
-; CHECK-NEXT:  mflo ${{[0-9]+}}
+; CHECK-NEXT:  #NO_APP
+; CHECK:       mflo ${{[0-9]+}}
   %bosco16 = alloca i16, align 4
   call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
   store volatile i16 %5, i16* %bosco16, align 4
diff --git a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
--- a/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
+++ b/llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll
@@ -11,16 +11,14 @@
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    daddiu $1, $zero, 7
-; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    .set push
 ; CHECK-NEXT:    .set at
 ; CHECK-NEXT:    .set macro
 ; CHECK-NEXT:    .set reorder
-; CHECK-EMPTY:
+; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    addiu $1, $1, 3
-; CHECK-EMPTY:
-; CHECK-NEXT:    .set pop
 ; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    .set pop
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $2, $zero, 0
 entry:
diff --git a/llvm/test/CodeGen/Mips/shrink-wrapping.ll b/llvm/test/CodeGen/Mips/shrink-wrapping.ll
--- a/llvm/test/CodeGen/Mips/shrink-wrapping.ll
+++ b/llvm/test/CodeGen/Mips/shrink-wrapping.ll
@@ -216,7 +216,7 @@
 ; SHRINK-WRAP-STATIC-NEXT:    .cfi_def_cfa_offset 24
 ; SHRINK-WRAP-STATIC-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; SHRINK-WRAP-STATIC-NEXT:    .cfi_offset 31, -4
-; SHRINK-WRAP-STATIC-NEXT:    #APP
+; SHRINK-WRAP-STATIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-STATIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-STATIC:       # %bb.0:
@@ -231,7 +231,7 @@
 ; NO-SHRINK-WRAP-STATIC-NEXT:    j $BB1_3
 ; NO-SHRINK-WRAP-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-STATIC-NEXT:  $BB1_2: # %if.then
-; NO-SHRINK-WRAP-STATIC-NEXT:    #APP
+; NO-SHRINK-WRAP-STATIC-NEXT:    .set push
 ;
 ; SHRINK-WRAP-PIC-LABEL: foo2:
 ; SHRINK-WRAP-PIC:       # %bb.0:
@@ -256,7 +256,7 @@
 ; SHRINK-WRAP-PIC-NEXT:    .cfi_def_cfa_offset 24
 ; SHRINK-WRAP-PIC-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; SHRINK-WRAP-PIC-NEXT:    .cfi_offset 31, -4
-; SHRINK-WRAP-PIC-NEXT:    #APP
+; SHRINK-WRAP-PIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-PIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-PIC:       # %bb.0:
@@ -281,7 +281,7 @@
 ; NO-SHRINK-WRAP-PIC-NEXT:    jr $1
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, 8
 ; NO-SHRINK-WRAP-PIC-NEXT:  $BB1_3: # %if.then
-; NO-SHRINK-WRAP-PIC-NEXT:    #APP
+; NO-SHRINK-WRAP-PIC-NEXT:    .set push
 ;
 ; SHRINK-WRAP-64-STATIC-LABEL: foo2:
 ; SHRINK-WRAP-64-STATIC:       # %bb.0:
@@ -297,7 +297,7 @@
 ; SHRINK-WRAP-64-STATIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-STATIC-NEXT:    .cfi_offset 31, -8
 ; SHRINK-WRAP-64-STATIC-NEXT:    sll $4, $4, 0
-; SHRINK-WRAP-64-STATIC-NEXT:    #APP
+; SHRINK-WRAP-64-STATIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-64-STATIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-64-STATIC:       # %bb.0:
@@ -313,7 +313,7 @@
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:  .LBB1_2: # %if.then
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    sll $4, $4, 0
-; NO-SHRINK-WRAP-64-STATIC-NEXT:    #APP
+; NO-SHRINK-WRAP-64-STATIC-NEXT:    .set push
 ;
 ; SHRINK-WRAP-64-PIC-LABEL: foo2:
 ; SHRINK-WRAP-64-PIC:       # %bb.0:
@@ -343,7 +343,7 @@
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 28, -16
 ; SHRINK-WRAP-64-PIC-NEXT:    daddiu $gp, $2, %lo(%neg(%gp_rel(foo2)))
 ; SHRINK-WRAP-64-PIC-NEXT:    sll $4, $4, 0
-; SHRINK-WRAP-64-PIC-NEXT:    #APP
+; SHRINK-WRAP-64-PIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-64-PIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-64-PIC:       # %bb.0:
@@ -373,7 +373,7 @@
 ; NO-SHRINK-WRAP-64-PIC-NEXT:  .LBB1_3: # %if.then
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $gp, $2, %lo(%neg(%gp_rel(foo2)))
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    sll $4, $4, 0
-; NO-SHRINK-WRAP-64-PIC-NEXT:    #APP
+; NO-SHRINK-WRAP-64-PIC-NEXT:    .set push
   %1 = icmp ne i32 %a, 4
   br i1 %1, label %if.then, label %if.end