Move inline-asm setup/cleanup directives outside of the "#APP" "#NO_APP" comment.

[jyknight]

Summary

After this change, only the user-specified assembly goes inside the
"APP" comment markers, not the mode-change directives. This only
affects MIPS at the moment, but we may soon start doing a similar
mode-change on X86 as well.

llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

void AsmPrinter::EmitInlineAsm(StringRef Str, const MCSubtargetInfo &STI,
   // Otherwise parse the asm and emit it via MC support.
   // This is useful in case the asm parser doesn't handle something but the
   // system assembler does.
   const MCAsmInfo *MCAI = TM.getMCAsmInfo();
   assert(MCAI && "No MCAsmInfo");
   if (!MCAI->useIntegratedAssembler() &&
       !OutStreamer->isIntegratedAssemblerRequired()) {
     emitInlineAsmStart();
+    OutStreamer->emitRawComment(MAI->getInlineAsmStart());
     OutStreamer->EmitRawText(Str);
+    OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
     emitInlineAsmEnd(STI, nullptr);
     return;
   }
 
   unsigned BufNum = addInlineAsmDiagBuffer(Str, LocMDNode);
   DiagInfo->SrcMgr.setIncludeDirs(MCOptions.IASSearchPaths);
 
   std::unique_ptr<MCAsmParser> Parser(createMCAsmParser(
report_fatal_error("Inline asm not supported by this streamer because"
                        " we don't have an asm parser for this target\n");
   Parser->setAssemblerDialect(Dialect);
   Parser->setTargetParser(*TAP.get());
   // Enable lexing Masm binary and hex integer literals in intel inline
   // assembly.
   if (Dialect == InlineAsm::AD_Intel)
     Parser->getLexer().setLexMasmIntegers(true);
 
+  // Emit target-specific directives before inline asm.
   emitInlineAsmStart();
+
+  // Emit the #APP start marker.  This has to happen even if verbose-asm isn't
+  // enabled, so we use emitRawComment.
+  OutStreamer->emitRawComment(MAI->getInlineAsmStart());
+
   // Don't implicitly switch to the text section before the asm.
   int Res = Parser->Run(/*NoInitialTextSection*/ true,
                         /*NoFinalize*/ true);
+
+  // Emit the #NOAPP end marker.  This has to happen even if verbose-asm isn't
+  // enabled, so we use emitRawComment.
+  OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
+
+  // Emit target-specific directives after inline asm.
   emitInlineAsmEnd(STI, &TAP->getSTI());
 
   if (Res && !DiagInfo->DiagHandler)
     report_fatal_error("Error parsing inline asm\n");
 }
 
 static void EmitMSInlineAsmStr(const char *AsmStr, const MachineInstr *MI,
                                MachineModuleInfo *MMI, AsmPrinter *AP,
void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const {
   // If this asmstr is empty, just print the #APP/#NOAPP markers.
   // These are useful to see where empty asm's wound up.
   if (AsmStr[0] == 0) {
     OutStreamer->emitRawComment(MAI->getInlineAsmStart());
     OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
     return;
   }
 
-  // Emit the #APP start marker.  This has to happen even if verbose-asm isn't
-  // enabled, so we use emitRawComment.
-  OutStreamer->emitRawComment(MAI->getInlineAsmStart());
-
   // Get the !srcloc metadata node if we have it, and decode the loc cookie from
   // it.
   unsigned LocCookie = 0;
   const MDNode *LocMD = nullptr;
   for (unsigned i = MI->getNumOperands(); i != 0; --i) {
     if (MI->getOperand(i-1).isMetadata() &&
         (LocMD = MI->getOperand(i-1).getMetadata()) &&
         LocMD->getNumOperands() != 0) {
std::string Note = "Reserved registers on the clobber list may not be "
                 "preserved across the asm statement, and clobbering them may "
                 "lead to undefined behaviour.";
     SrcMgr.PrintMessage(Loc, SourceMgr::DK_Warning, Msg);
     SrcMgr.PrintMessage(Loc, SourceMgr::DK_Note, Note);
   }
 
   EmitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
                 MI->getInlineAsmDialect());
-
-  // Emit the #NOAPP end marker.  This has to happen even if verbose-asm isn't
-  // enabled, so we use emitRawComment.
-  OutStreamer->emitRawComment(MAI->getInlineAsmEnd());
 }
 
 
 /// PrintSpecial - Print information related to the specified machine instr
 /// that is independent of the operand, and may be independent of the instr
 /// itself.  This can be useful for portably encoding the comment character
 /// or other bits of target-specific knowledge into the asmstrings.  The
 /// syntax used is ${:comment}.  Targets can override this to add support

llvm/lib/Target/Mips/MipsAsmPrinter.cpp

void MipsAsmPrinter::emitInlineAsmStart() const {
   // 'nomacro' and 'noreorder').
   // In order to maintain compatibility with inline assembly code which depends
   // on GCC's assembler options being used, we have to switch to those options
   // for the duration of the inline assembly block and then switch back.
   TS.emitDirectiveSetPush();
   TS.emitDirectiveSetAt();
   TS.emitDirectiveSetMacro();
   TS.emitDirectiveSetReorder();
-  OutStreamer->AddBlankLine();
 }
 
 void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
                                       const MCSubtargetInfo *EndInfo) const {
-  OutStreamer->AddBlankLine();
   getTargetStreamer().emitDirectiveSetPop();
 }
 
 void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
   MCInst I;
   I.setOpcode(Mips::JAL);
   I.addOperand(
       MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext)));

llvm/test/CodeGen/Mips/inlineasm-assembler-directives.ll

 ; RUN: llc -march=mips < %s | FileCheck %s
 
 ; Check for the emission of appropriate assembler directives before and
 ; after the inline assembly code.
 define void @f() nounwind {
 entry:
-; CHECK:      #APP
-; CHECK-NEXT: .set  push
+; CHECK: .set  push
 ; CHECK-NEXT: .set  at
 ; CHECK-NEXT: .set  macro
 ; CHECK-NEXT: .set  reorder
+; CHECK-NEXT:      #APP
 ; CHECK:      addi $9, ${{[2-9][0-9]?}}, 8
 ; CHECK:      ori ${{[2-9][0-9]?}}, $9, 6
-; CHECK:      .set  pop
-; CHECK-NEXT: #NO_APP
+; CHECK: #NO_APP
+; CHECK-NEXT:      .set  pop
   %a = alloca i32, align 4
   %b = alloca i32, align 4
   store i32 20, i32* %a, align 4
   %0 = load i32, i32* %a, align 4
   %1 = call i32 asm sideeffect "addi $$9, $1, 8\0A\09ori $0, $$9, 6", "=r,r,~{$1}"(i32 %0)
   store i32 %1, i32* %b, align 4
   ret void
 }

llvm/test/CodeGen/Mips/inlineasm-constraint-reg.ll

 ; Positive test for inline register constraints
 ;
 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s
 ; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s
 
 define i32 @main() nounwind {
 entry:
 
 ; r with char
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
-;CHECK: #NO_APP
+;CHECK:      #APP
+;CHECK-NEXT: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23
+;CHECK-NEXT: #NO_APP
   tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind
 
 ; r with short
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
-;CHECK: #NO_APP
+;CHECK:      #APP
+;CHECK-NEXT: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13
+;CHECK-NEXT: #NO_APP
   tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind
 
 ; r with int
-;CHECK: #APP
-;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
-;CHECK: #NO_APP
+;CHECK:      #APP
+;CHECK-NEXT: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
+;CHECK-NEXT: #NO_APP
   tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind
 
 ; Now c with 1024: make sure register $25 is picked
-; CHECK: #APP
-; CHECK: addiu $25, ${{[0-9]+}}, 1024
-; CHECK: #NO_APP
+; CHECK:      #APP
+; CHECK-NEXT: addiu $25, ${{[0-9]+}}, 1024
+; CHECK-NEXT: #NO_APP
    tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind
 
 ; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
 ; after the inline expression for a mflo to pull the value out of lo.
 ; CHECK:       #APP
-; CHECK:       mtlo ${{[0-9]+}}
+; CHECK-NEXT:  mtlo ${{[0-9]+}}
 ; CHECK-NEXT:  madd ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK:       #NO_APP
-; CHECK-NEXT:  mflo ${{[0-9]+}}
+; CHECK-NEXT:  #NO_APP
+; CHECK:       mflo ${{[0-9]+}}
   %bosco = alloca i32, align 4
   call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
   store volatile i32 %4, i32* %bosco, align 4
  
 ; Check the 'l' constraint for 16-bit type.
 ; CHECK:       #APP
-; CHECK:       mtlo ${{[0-9]+}}
+; CHECK-NEXT:  mtlo ${{[0-9]+}}
 ; CHECK-NEXT:  madd ${{[0-9]+}}, ${{[0-9]+}}
-; CHECK:       #NO_APP
-; CHECK-NEXT:  mflo ${{[0-9]+}}
+; CHECK-NEXT:  #NO_APP
+; CHECK:       mflo ${{[0-9]+}}
   %bosco16 = alloca i16, align 4
   call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
   store volatile i16 %5, i16* %bosco16, align 4
 
   ret i32 0
 }

llvm/test/CodeGen/Mips/inlineasm-constraint-reg64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;
 ; Register constraint "r" shouldn't take long long unless
 ; The target is 64 bit.
 ;
 ;
 ; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s
 
 
 define i32 @main() nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    daddiu $1, $zero, 7
-; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    .set push
 ; CHECK-NEXT:    .set at
 ; CHECK-NEXT:    .set macro
 ; CHECK-NEXT:    .set reorder
-; CHECK-EMPTY:
+; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    addiu $1, $1, 3
-; CHECK-EMPTY:
-; CHECK-NEXT:    .set pop
 ; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    .set pop
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $2, $zero, 0
 entry:
 
 
 ; r with long long
   tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind
   ret i32 0
 }
 

llvm/test/CodeGen/Mips/shrink-wrapping.ll

 ; SHRINK-WRAP-STATIC-NEXT:  # %bb.1:
 ; SHRINK-WRAP-STATIC-NEXT:    j $BB1_3
 ; SHRINK-WRAP-STATIC-NEXT:    nop
 ; SHRINK-WRAP-STATIC-NEXT:  $BB1_2: # %if.then
 ; SHRINK-WRAP-STATIC-NEXT:    addiu $sp, $sp, -24
 ; SHRINK-WRAP-STATIC-NEXT:    .cfi_def_cfa_offset 24
 ; SHRINK-WRAP-STATIC-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; SHRINK-WRAP-STATIC-NEXT:    .cfi_offset 31, -4
-; SHRINK-WRAP-STATIC-NEXT:    #APP
+; SHRINK-WRAP-STATIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-STATIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-STATIC:       # %bb.0:
 ; NO-SHRINK-WRAP-STATIC-NEXT:    addiu $sp, $sp, -24
 ; NO-SHRINK-WRAP-STATIC-NEXT:    .cfi_def_cfa_offset 24
 ; NO-SHRINK-WRAP-STATIC-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; NO-SHRINK-WRAP-STATIC-NEXT:    .cfi_offset 31, -4
 ; NO-SHRINK-WRAP-STATIC-NEXT:    addiu $1, $zero, 4
 ; NO-SHRINK-WRAP-STATIC-NEXT:    bne $4, $1, $BB1_2
 ; NO-SHRINK-WRAP-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-STATIC-NEXT:  # %bb.1:
 ; NO-SHRINK-WRAP-STATIC-NEXT:    j $BB1_3
 ; NO-SHRINK-WRAP-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-STATIC-NEXT:  $BB1_2: # %if.then
-; NO-SHRINK-WRAP-STATIC-NEXT:    #APP
+; NO-SHRINK-WRAP-STATIC-NEXT:    .set push
 ;
 ; SHRINK-WRAP-PIC-LABEL: foo2:
 ; SHRINK-WRAP-PIC:       # %bb.0:
 ; SHRINK-WRAP-PIC-NEXT:    lui $2, %hi(_gp_disp)
 ; SHRINK-WRAP-PIC-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; SHRINK-WRAP-PIC-NEXT:    addiu $1, $zero, 4
 ; SHRINK-WRAP-PIC-NEXT:    bne $4, $1, $BB1_3
 ; SHRINK-WRAP-PIC-NEXT:    addu $gp, $2, $25
 ; SHRINK-WRAP-PIC-NEXT:  # %bb.1:
 ; SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, -8
 ; SHRINK-WRAP-PIC-NEXT:    sw $ra, 0($sp)
 ; SHRINK-WRAP-PIC-NEXT:    lui $1, %hi(($BB1_4)-($BB1_2))
 ; SHRINK-WRAP-PIC-NEXT:    bal $BB1_2
 ; SHRINK-WRAP-PIC-NEXT:    addiu $1, $1, %lo(($BB1_4)-($BB1_2))
 ; SHRINK-WRAP-PIC-NEXT:  $BB1_2:
 ; SHRINK-WRAP-PIC-NEXT:    addu $1, $ra, $1
 ; SHRINK-WRAP-PIC-NEXT:    lw $ra, 0($sp)
 ; SHRINK-WRAP-PIC-NEXT:    jr $1
 ; SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, 8
 ; SHRINK-WRAP-PIC-NEXT:  $BB1_3: # %if.then
 ; SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, -24
 ; SHRINK-WRAP-PIC-NEXT:    .cfi_def_cfa_offset 24
 ; SHRINK-WRAP-PIC-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; SHRINK-WRAP-PIC-NEXT:    .cfi_offset 31, -4
-; SHRINK-WRAP-PIC-NEXT:    #APP
+; SHRINK-WRAP-PIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-PIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-PIC:       # %bb.0:
 ; NO-SHRINK-WRAP-PIC-NEXT:    lui $2, %hi(_gp_disp)
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, -24
 ; NO-SHRINK-WRAP-PIC-NEXT:    .cfi_def_cfa_offset 24
 ; NO-SHRINK-WRAP-PIC-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
 ; NO-SHRINK-WRAP-PIC-NEXT:    .cfi_offset 31, -4
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $1, $zero, 4
 ; NO-SHRINK-WRAP-PIC-NEXT:    bne $4, $1, $BB1_3
 ; NO-SHRINK-WRAP-PIC-NEXT:    addu $gp, $2, $25
 ; NO-SHRINK-WRAP-PIC-NEXT:  # %bb.1:
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, -8
 ; NO-SHRINK-WRAP-PIC-NEXT:    sw $ra, 0($sp)
 ; NO-SHRINK-WRAP-PIC-NEXT:    lui $1, %hi(($BB1_4)-($BB1_2))
 ; NO-SHRINK-WRAP-PIC-NEXT:    bal $BB1_2
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $1, $1, %lo(($BB1_4)-($BB1_2))
 ; NO-SHRINK-WRAP-PIC-NEXT:  $BB1_2:
 ; NO-SHRINK-WRAP-PIC-NEXT:    addu $1, $ra, $1
 ; NO-SHRINK-WRAP-PIC-NEXT:    lw $ra, 0($sp)
 ; NO-SHRINK-WRAP-PIC-NEXT:    jr $1
 ; NO-SHRINK-WRAP-PIC-NEXT:    addiu $sp, $sp, 8
 ; NO-SHRINK-WRAP-PIC-NEXT:  $BB1_3: # %if.then
-; NO-SHRINK-WRAP-PIC-NEXT:    #APP
+; NO-SHRINK-WRAP-PIC-NEXT:    .set push
 ;
 ; SHRINK-WRAP-64-STATIC-LABEL: foo2:
 ; SHRINK-WRAP-64-STATIC:       # %bb.0:
 ; SHRINK-WRAP-64-STATIC-NEXT:    addiu $1, $zero, 4
 ; SHRINK-WRAP-64-STATIC-NEXT:    bne $4, $1, .LBB1_2
 ; SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; SHRINK-WRAP-64-STATIC-NEXT:  # %bb.1:
 ; SHRINK-WRAP-64-STATIC-NEXT:    j .LBB1_3
 ; SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; SHRINK-WRAP-64-STATIC-NEXT:  .LBB1_2: # %if.then
 ; SHRINK-WRAP-64-STATIC-NEXT:    daddiu $sp, $sp, -16
 ; SHRINK-WRAP-64-STATIC-NEXT:    .cfi_def_cfa_offset 16
 ; SHRINK-WRAP-64-STATIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-STATIC-NEXT:    .cfi_offset 31, -8
 ; SHRINK-WRAP-64-STATIC-NEXT:    sll $4, $4, 0
-; SHRINK-WRAP-64-STATIC-NEXT:    #APP
+; SHRINK-WRAP-64-STATIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-64-STATIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-64-STATIC:       # %bb.0:
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    daddiu $sp, $sp, -16
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    .cfi_def_cfa_offset 16
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    .cfi_offset 31, -8
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    addiu $1, $zero, 4
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    bne $4, $1, .LBB1_2
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:  # %bb.1:
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    j .LBB1_3
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    nop
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:  .LBB1_2: # %if.then
 ; NO-SHRINK-WRAP-64-STATIC-NEXT:    sll $4, $4, 0
-; NO-SHRINK-WRAP-64-STATIC-NEXT:    #APP
+; NO-SHRINK-WRAP-64-STATIC-NEXT:    .set push
 ;
 ; SHRINK-WRAP-64-PIC-LABEL: foo2:
 ; SHRINK-WRAP-64-PIC:       # %bb.0:
 ; SHRINK-WRAP-64-PIC-NEXT:    lui $1, %hi(%neg(%gp_rel(foo2)))
 ; SHRINK-WRAP-64-PIC-NEXT:    daddu $2, $1, $25
 ; SHRINK-WRAP-64-PIC-NEXT:    addiu $1, $zero, 4
 ; SHRINK-WRAP-64-PIC-NEXT:    bne $4, $1, .LBB1_3
 ; SHRINK-WRAP-64-PIC-NEXT:    nop

 ; SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, -16
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_def_cfa_offset 16
 ; SHRINK-WRAP-64-PIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-PIC-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 31, -8
 ; SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 28, -16
 ; SHRINK-WRAP-64-PIC-NEXT:    daddiu $gp, $2, %lo(%neg(%gp_rel(foo2)))
 ; SHRINK-WRAP-64-PIC-NEXT:    sll $4, $4, 0
-; SHRINK-WRAP-64-PIC-NEXT:    #APP
+; SHRINK-WRAP-64-PIC-NEXT:    .set push
 ;
 ; NO-SHRINK-WRAP-64-PIC-LABEL: foo2:
 ; NO-SHRINK-WRAP-64-PIC:       # %bb.0:
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, -16
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    .cfi_def_cfa_offset 16
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    sd $gp, 0($sp) # 8-byte Folded Spill
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    .cfi_offset 31, -8

 ; NO-SHRINK-WRAP-64-PIC-NEXT:  .LBB1_2:
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddu $1, $ra, $1
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    ld $ra, 0($sp)
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    jr $1
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $sp, $sp, 16
 ; NO-SHRINK-WRAP-64-PIC-NEXT:  .LBB1_3: # %if.then
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    daddiu $gp, $2, %lo(%neg(%gp_rel(foo2)))
 ; NO-SHRINK-WRAP-64-PIC-NEXT:    sll $4, $4, 0
-; NO-SHRINK-WRAP-64-PIC-NEXT:    #APP
+; NO-SHRINK-WRAP-64-PIC-NEXT:    .set push
   %1 = icmp ne i32 %a, 4
   br i1 %1, label %if.then, label %if.end
 
 if.then:
   call void asm sideeffect ".space 1048576", "~{$1}"()
   call void @f(i32 signext %a)
   br label %if.end
 
 if.end:
   ret i32 0
 }