diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h --- a/llvm/lib/Target/PowerPC/PPC.h +++ b/llvm/lib/Target/PowerPC/PPC.h @@ -99,15 +99,6 @@ /// the function's picbase, e.g. lo16(symbol-picbase). MO_PIC_FLAG = 2, - /// MO_NLP_FLAG - If this bit is set, the symbol reference is actually to - /// the non_lazy_ptr for the global, e.g. lo16(symbol$non_lazy_ptr-picbase). - MO_NLP_FLAG = 4, - - /// MO_NLP_HIDDEN_FLAG - If this bit is set, the symbol reference is to a - /// symbol with hidden visibility. This causes a different kind of - /// non-lazy-pointer to be generated. - MO_NLP_HIDDEN_FLAG = 8, - /// The next are not flags but distinct values. MO_ACCESS_MASK = 0xf0, diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -176,23 +176,7 @@ raw_ostream &O) { // Computing the address of a global symbol, not calling it. const GlobalValue *GV = MO.getGlobal(); - MCSymbol *SymToPrint; - - // External or weakly linked global variables need non-lazily-resolved stubs - if (Subtarget->hasLazyResolverStub(GV)) { - SymToPrint = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr"); - MachineModuleInfoImpl::StubValueTy &StubSym = - MMI->getObjFileInfo().getGVStubEntry( - SymToPrint); - if (!StubSym.getPointer()) - StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), - !GV->hasInternalLinkage()); - } else { - SymToPrint = getSymbol(GV); - } - - SymToPrint->print(O, MAI); - + getSymbol(GV)->print(O, MAI); printOffset(MO.getOffset(), O); } @@ -208,9 +192,7 @@ // Linux assembler (Others?) does not take register mnemonics. // FIXME - What about special registers used in mfspr/mtspr? - if (!Subtarget->isDarwin()) - RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); - O << RegName; + O << PPCRegisterInfo::stripRegisterPrefix(RegName); return; } case MachineOperand::MO_Immediate: @@ -300,10 +282,7 @@ default: return true; // Unknown modifier. case 'y': // A memory reference for an X-form instruction { - const char *RegName = "r0"; - if (!Subtarget->isDarwin()) - RegName = PPCRegisterInfo::stripRegisterPrefix(RegName); - O << RegName << ", "; + O << "0, "; printOperand(MI, OpNo, O); return false; } diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -47,7 +47,7 @@ }; static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) { - if (STI.isDarwinABI() || STI.isAIXABI()) + if (STI.isAIXABI()) return STI.isPPC64() ? 16 : 8; // SVR4 ABI: return STI.isPPC64() ? 16 : 4; @@ -60,20 +60,12 @@ } static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) { - // For the Darwin ABI: - // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area - // for saving the frame pointer (if needed.) While the published ABI has - // not used this slot since at least MacOSX 10.2, there is older code - // around that does use it, and that needs to continue to work. - if (STI.isDarwinABI()) - return STI.isPPC64() ? -8U : -4U; - // SVR4 ABI: First slot in the general register save area. return STI.isPPC64() ? -8U : -4U; } static unsigned computeLinkageSize(const PPCSubtarget &STI) { - if ((STI.isDarwinABI() || STI.isAIXABI()) || STI.isPPC64()) + if (STI.isAIXABI() || STI.isPPC64()) return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4); // 32-bit SVR4 ABI: @@ -81,9 +73,6 @@ } static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) { - if (STI.isDarwinABI()) - return STI.isPPC64() ? -16U : -8U; - // SVR4 ABI: First slot in the general register save area. return STI.isPPC64() ? -16U @@ -108,17 +97,6 @@ // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots( unsigned &NumEntries) const { - if (Subtarget.isDarwinABI()) { - NumEntries = 1; - if (Subtarget.isPPC64()) { - static const SpillSlot darwin64Offsets = {PPC::X31, -8}; - return &darwin64Offsets; - } else { - static const SpillSlot darwinOffsets = {PPC::R31, -4}; - return &darwinOffsets; - } - } - // Early exit if not using the SVR4 ABI. if (!Subtarget.isSVR4ABI()) { NumEntries = 0; @@ -790,8 +768,7 @@ bool isSVR4ABI = Subtarget.isSVR4ABI(); bool isAIXABI = Subtarget.isAIXABI(); bool isELFv2ABI = Subtarget.isELFv2ABI(); - assert((Subtarget.isDarwinABI() || isSVR4ABI || isAIXABI) && - "Unsupported PPC ABI."); + assert((isSVR4ABI || isAIXABI) && "Unsupported PPC ABI."); // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, // process it. @@ -1776,7 +1753,6 @@ // Save R31 if necessary int FPSI = FI->getFramePointerSaveIndex(); const bool isPPC64 = Subtarget.isPPC64(); - const bool IsDarwinABI = Subtarget.isDarwinABI(); MachineFrameInfo &MFI = MF.getFrameInfo(); // If the frame pointer save index hasn't been defined yet. @@ -1825,9 +1801,8 @@ // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the // function uses CR 2, 3, or 4. - if (!isPPC64 && !IsDarwinABI && - (SavedRegs.test(PPC::CR2) || - SavedRegs.test(PPC::CR3) || + if (Subtarget.is32BitELFABI() && + (SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) || SavedRegs.test(PPC::CR4))) { int FrameIdx = MFI.CreateFixedObject((uint64_t)4, (int64_t)-4, true); FI->setCRSpillFrameIndex(FrameIdx); @@ -2201,10 +2176,8 @@ for (unsigned i = 0, e = CSI.size(); i != e; ++i) { unsigned Reg = CSI[i].getReg(); - // Only Darwin actually uses the VRSAVE register, but it can still appear - // here if, for example, @llvm.eh.unwind.init() is used. If we're not on - // Darwin, ignore it. - if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) + // VRSAVE can appear here if, for example, @llvm.eh.unwind.init() is used. + if (Reg == PPC::VRSAVE) continue; // CR2 through CR4 are the nonvolatile CR fields. @@ -2374,10 +2347,8 @@ for (unsigned i = 0, e = CSI.size(); i != e; ++i) { unsigned Reg = CSI[i].getReg(); - // Only Darwin actually uses the VRSAVE register, but it can still appear - // here if, for example, @llvm.eh.unwind.init() is used. If we're not on - // Darwin, ignore it. - if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI()) + // VRSAVE can appear here if, for example, @llvm.eh.unwind.init() is used. + if (Reg == PPC::VRSAVE) continue; if ((Reg == PPC::X2 || Reg == PPC::R2) && MustSaveTOC) diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -5126,8 +5126,6 @@ const bool isELFABI = PPCSubTarget->isSVR4ABI(); const bool isAIXABI = PPCSubTarget->isAIXABI(); - assert(!PPCSubTarget->isDarwin() && "TOC is an ELF/XCOFF construct"); - // PowerPC only support small, medium and large code model. const CodeModel::Model CModel = TM.getCodeModel(); assert(!(CModel == CodeModel::Tiny || CModel == CodeModel::Kernel) && @@ -6428,10 +6426,6 @@ } void PPCDAGToDAGISel::PeepholePPC64() { - // These optimizations are currently supported only for 64-bit SVR4. - if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64()) - return; - SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end(); while (Position != CurDAG->allnodes_begin()) { diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1190,20 +1190,6 @@ setTargetDAGCombine(ISD::VSELECT); } - // Darwin long double math library functions have $LDBL128 appended. - if (Subtarget.isDarwin()) { - setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128"); - setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128"); - setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128"); - setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128"); - setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128"); - setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128"); - setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128"); - setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128"); - setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128"); - setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128"); - } - if (EnableQuadPrecision) { setLibcallName(RTLIB::LOG_F128, "logf128"); setLibcallName(RTLIB::LOG2_F128, "log2f128"); @@ -1227,8 +1213,6 @@ } setMinFunctionAlignment(Align(4)); - if (Subtarget.isDarwin()) - setPrefFunctionAlignment(Align(16)); switch (Subtarget.getCPUDirective()) { default: break; @@ -1314,10 +1298,6 @@ /// function arguments in the caller parameter area. unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty, const DataLayout &DL) const { - // Darwin passes everything on 4 byte boundary. - if (Subtarget.isDarwin()) - return 4; - // 16byte and wider vectors are passed on 16byte boundary. // The rest is 8 on PPC64 and 4 on PPC32 boundary. unsigned Align = Subtarget.isPPC64() ? 8 : 4; @@ -2687,18 +2667,6 @@ HiOpFlags |= PPCII::MO_PIC_FLAG; LoOpFlags |= PPCII::MO_PIC_FLAG; } - - // If this is a reference to a global value that requires a non-lazy-ptr, make - // sure that instruction lowering adds it. - if (GV && Subtarget.hasLazyResolverStub(GV)) { - HiOpFlags |= PPCII::MO_NLP_FLAG; - LoOpFlags |= PPCII::MO_NLP_FLAG; - - if (GV->hasHiddenVisibility()) { - HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; - LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG; - } - } } static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, @@ -3007,13 +2975,7 @@ SDValue GALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); - SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG); - - // If the global reference is actually to a non-lazy-pointer, we have to do an - // extra load to get the address of the global. - if (MOHiFlag & PPCII::MO_NLP_FLAG) - Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo()); - return Ptr; + return LowerLabelRef(GAHi, GALo, IsPIC, DAG); } SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { @@ -3234,7 +3196,7 @@ SDLoc dl(Op); - if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { + if (Subtarget.isPPC64()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); @@ -4858,18 +4820,6 @@ SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, MachinePointerInfo::getFixedStack(MF, NewRetAddr)); - - // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack - // slot as the FP is never overwritten. - if (Subtarget.isDarwinABI()) { - int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset(); - int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc, - true); - SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); - Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx, - MachinePointerInfo::getFixedStack( - DAG.getMachineFunction(), NewFPIdx)); - } } return Chain; } @@ -4904,14 +4854,6 @@ LROpOut = getReturnAddrFrameIndex(DAG); LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo()); Chain = SDValue(LROpOut.getNode(), 1); - - // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack - // slot as the FP is never overwritten. - if (Subtarget.isDarwinABI()) { - FPOpOut = getFramePointerFrameIndex(DAG); - FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo()); - Chain = SDValue(FPOpOut.getNode(), 1); - } } return Chain; } @@ -14858,7 +14800,6 @@ Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const { bool isPPC64 = Subtarget.isPPC64(); - bool IsDarwinABI = Subtarget.isDarwinABI(); bool is64Bit = isPPC64 && VT == LLT::scalar(64); if (!is64Bit && VT != LLT::scalar(32)) @@ -14866,9 +14807,8 @@ Register Reg = StringSwitch(RegName) .Case("r1", is64Bit ? PPC::X1 : PPC::R1) - .Case("r2", (IsDarwinABI || isPPC64) ? Register() : PPC::R2) - .Case("r13", (!isPPC64 && IsDarwinABI) ? Register() : - (is64Bit ? PPC::X13 : PPC::R13)) + .Case("r2", isPPC64 ? Register() : PPC::R2) + .Case("r13", (is64Bit ? PPC::X13 : PPC::R13)) .Default(Register()); if (Reg) @@ -15303,7 +15243,6 @@ } void PPCTargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const { - if (Subtarget.isDarwinABI()) return; if (!Subtarget.isPPC64()) return; // Update IsSplitCSR in PPCFunctionInfo diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2034,10 +2034,7 @@ PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { using namespace PPCII; static const std::pair TargetFlags[] = { - {MO_PLT, "ppc-plt"}, - {MO_PIC_FLAG, "ppc-pic"}, - {MO_NLP_FLAG, "ppc-nlp"}, - {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}}; + {MO_PLT, "ppc-plt"}, {MO_PIC_FLAG, "ppc-pic"}}; return makeArrayRef(TargetFlags); } diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp --- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp +++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp @@ -29,10 +29,6 @@ #include "llvm/Target/TargetLoweringObjectFile.h" using namespace llvm; -static MachineModuleInfoMachO &getMachOMMI(AsmPrinter &AP) { - return AP.MMI->getObjFileInfo(); -} - static MCSymbol *GetSymbolFromOperand(const MachineOperand &MO, AsmPrinter &AP) { const TargetMachine &TM = AP.TM; @@ -41,13 +37,6 @@ MCContext &Ctx = AP.OutContext; SmallString<128> Name; - StringRef Suffix; - if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG) - Suffix = "$non_lazy_ptr"; - - if (!Suffix.empty()) - Name += DL.getPrivateGlobalPrefix(); - if (!MO.isGlobal()) { assert(MO.isSymbol() && "Isn't a symbol reference"); Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL); @@ -56,25 +45,8 @@ TM.getNameWithPrefix(Name, GV, Mang); } - Name += Suffix; MCSymbol *Sym = Ctx.getOrCreateSymbol(Name); - // If the symbol reference is actually to a non_lazy_ptr, not to the symbol, - // then add the suffix. - if (MO.getTargetFlags() & PPCII::MO_NLP_FLAG) { - MachineModuleInfoMachO &MachO = getMachOMMI(AP); - - MachineModuleInfoImpl::StubValueTy &StubSym = MachO.getGVStubEntry(Sym); - - if (!StubSym.getPointer()) { - assert(MO.isGlobal() && "Extern symbol not handled yet"); - StubSym = MachineModuleInfoImpl:: - StubValueTy(AP.getSymbol(MO.getGlobal()), - !MO.getGlobal()->hasInternalLinkage()); - } - return Sym; - } - return Sym; } diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -149,13 +149,6 @@ return CSR_64_AllRegs_SaveList; } - if (Subtarget.isDarwinABI()) - return TM.isPPC64() - ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList - : CSR_Darwin64_SaveList) - : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList - : CSR_Darwin32_SaveList); - if (TM.isPPC64() && MF->getInfo()->isSplitCSR()) return CSR_SRV464_TLS_PE_SaveList; @@ -198,8 +191,6 @@ PPCRegisterInfo::getCalleeSavedRegsViaCopy(const MachineFunction *MF) const { assert(MF && "Invalid MachineFunction pointer."); const PPCSubtarget &Subtarget = MF->getSubtarget(); - if (Subtarget.isDarwinABI()) - return nullptr; if (!TM.isPPC64()) return nullptr; if (MF->getFunction().getCallingConv() != CallingConv::CXX_FAST_TLS) @@ -231,11 +222,6 @@ return CSR_64_AllRegs_RegMask; } - if (Subtarget.isDarwinABI()) - return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask - : CSR_Darwin64_RegMask) - : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask - : CSR_Darwin32_RegMask); if (Subtarget.isAIXABI()) { assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet."); return TM.isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask; @@ -295,8 +281,7 @@ markSuperRegs(Reserved, PPC::LR8); markSuperRegs(Reserved, PPC::RM); - if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) - markSuperRegs(Reserved, PPC::VRSAVE); + markSuperRegs(Reserved, PPC::VRSAVE); // The SVR4 ABI reserves r2 and r13 if (Subtarget.isSVR4ABI()) { diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -126,7 +126,6 @@ bool FeatureMFTB; bool AllowsUnalignedFPAccess; bool DeprecatedDST; - bool HasLazyResolverStubs; bool IsLittleEndian; bool HasICBT; bool HasInvariantFunctionDescriptors; @@ -230,11 +229,6 @@ /// the individual condition register bits. bool useCRBits() const { return UseCRBits; } - /// hasLazyResolverStub - Return true if accesses to the specified global have - /// to go through a dyld lazy resolution stub. This means that an extra load - /// is required to get the address of the global. - bool hasLazyResolverStub(const GlobalValue *GV) const; - // isLittleEndian - True if generating little-endian code bool isLittleEndian() const { return IsLittleEndian; } @@ -294,10 +288,9 @@ return Align(16); } - // DarwinABI has a 224-byte red zone. PPC32 SVR4ABI(Non-DarwinABI) has no - // red zone and PPC64 SVR4ABI has a 288-byte red zone. + // PPC32 SVR4ABI has no red zone and PPC64 SVR4ABI has a 288-byte red zone. unsigned getRedZoneSize() const { - return isDarwinABI() ? 224 : (isPPC64() ? 288 : 0); + return isPPC64() ? 288 : 0; } bool hasHTM() const { return HasHTM; } @@ -312,8 +305,6 @@ const Triple &getTargetTriple() const { return TargetTriple; } - /// isDarwin - True if this is any darwin platform. - bool isDarwin() const { return TargetTriple.isMacOSX(); } /// isBGQ - True if this is a BG/Q platform. bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; } @@ -321,9 +312,8 @@ bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } bool isTargetLinux() const { return TargetTriple.isOSLinux(); } - bool isDarwinABI() const { return isTargetMachO() || isDarwin(); } bool isAIXABI() const { return TargetTriple.isOSAIX(); } - bool isSVR4ABI() const { return !isDarwinABI() && !isAIXABI(); } + bool isSVR4ABI() const { return !isAIXABI(); } bool isELFv2ABI() const; bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); } diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -102,7 +102,6 @@ FeatureMFTB = false; AllowsUnalignedFPAccess = false; DeprecatedDST = false; - HasLazyResolverStubs = false; HasICBT = false; HasInvariantFunctionDescriptors = false; HasPartwordAtomics = false; @@ -142,10 +141,6 @@ if (IsPPC64 && has64BitSupport()) Use64BitRegs = true; - // Set up darwin-specific properties. - if (isDarwin()) - HasLazyResolverStubs = true; - if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) || TargetTriple.isOSNetBSD() || TargetTriple.isOSOpenBSD() || TargetTriple.isMusl()) @@ -175,22 +170,6 @@ IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); } -/// Return true if accesses to the specified global have to go through a dyld -/// lazy resolution stub. This means that an extra load is required to get the -/// address of the global. -bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const { - if (!HasLazyResolverStubs) - return false; - if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) - return true; - // 32 bit macho has no relocation for a-b if a is undefined, even if b is in - // the section that is being relocated. This means we have to use o load even - // for GVs that are known to be local to the dso. - if (GV->isDeclarationForLinker() || GV->hasCommonLinkage()) - return true; - return false; -} - bool PPCSubtarget::enableMachineScheduler() const { return true; } bool PPCSubtarget::enableMachinePipeliner() const { diff --git a/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll deleted file mode 100644 --- a/llvm/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: llc -verify-machineinstrs < %s -; PR2988 -target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" -target triple = "powerpc-unknown-linux-gnu" -@a = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; [#uses=2] -@b = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; [#uses=2] -@c = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; [#uses=3] -@d = common global ppc_fp128 0xM00000000000000000000000000000000, align 16 ; [#uses=2] - -define void @foo() nounwind { -entry: - %0 = load ppc_fp128, ppc_fp128* @a, align 16 ; [#uses=1] - %1 = call ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128 %0) ; [#uses=1] - store ppc_fp128 %1, ppc_fp128* @a, align 16 - %2 = load ppc_fp128, ppc_fp128* @b, align 16 ; [#uses=1] - %3 = call ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128 %2) nounwind readonly ; [#uses=1] - store ppc_fp128 %3, ppc_fp128* @b, align 16 - %4 = load ppc_fp128, ppc_fp128* @c, align 16 ; [#uses=1] - %5 = call ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128 %4) nounwind readonly ; [#uses=1] - store ppc_fp128 %5, ppc_fp128* @c, align 16 - %6 = load ppc_fp128, ppc_fp128* @d, align 16 ; [#uses=1] - %7 = load ppc_fp128, ppc_fp128* @c, align 16 ; [#uses=1] - %8 = call ppc_fp128 @llvm.pow.ppcf128(ppc_fp128 %6, ppc_fp128 %7) ; [#uses=1] - store ppc_fp128 %8, ppc_fp128* @d, align 16 - br label %return - -return: ; preds = %entry - ret void -} - -declare ppc_fp128 @llvm.sqrt.ppcf128(ppc_fp128) nounwind readonly - -declare ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128) nounwind readonly - -declare ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128) nounwind readonly - -declare ppc_fp128 @llvm.pow.ppcf128(ppc_fp128, ppc_fp128) nounwind readonly - -declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) - -define ppc_fp128 @cs(ppc_fp128 %from, ppc_fp128 %to) { - %tmp = call ppc_fp128 @copysignl(ppc_fp128 %from, ppc_fp128 %to) - ret ppc_fp128 %tmp -}