[GlobalISel][RFC] Importing patterns with PtrValueType and nullptr

[Petar.Avramovic]

Summary

This is WIP on iseling icmp, select and branch patterns that involve pointers.

Pointers in GlobalISel have pointer type, unlike SDAG where they have integer type.
Thus GlobalISel selectImpl cannot select pointer instructions from SDAG td files since there are no patterns for pointers there.

It is already possible to write td file for GlobalIsel that will allow selection of pointer patterns.
For that reason I am adding a new td file with additional patterns for pointers, everything from SDAG td files is also included.

Introducing new ValueType, NullPtrValue. It allows to specify nullpointer integer value in td file that will be matched with:

%0:gprb(scalar) = G_CONSTANT intvalue
%1:gprb(p_addrspace) = G_INTTOPTR %0(scalar)

since that is how globalisel translates llvm-ir null. For MIPS intvalue is 0.

Added a few pointer patterns example tests for MIPS in new td file.

Similar thing could be possible for x86, this pattern for example:

def : Pat<(X86cmp GR32:$src1, 0),
          (TEST32rr GR32:$src1, GR32:$src1)>;

also works for pointers in SDAG, but for globalisel it would require custom legalize that generates GINodeEquiv of X86cmp and new pattern with PtrValueType and NullPtrValue instead of 0.

TODO: If NullPtrValue idea works, split to smaller patches and add detailed tests for source patterns with two or more instructions.

[arsenm]

G_CONSTANT can already directly have a pointer type, so I don't see a reason that the extra G_INTTOPTR needs to be involved. I would also like to avoid that for non-integral address spaces, which may still have a sentinel pointer value / null value. This is also going to create a lot of spurious instructions. It's not just the selection patterns that will need to consider this, but any pattern matching before that.

Are you trying to specifically select pointer differently from integers? I thought you could already get this to work without distinguishing them with PtrValueType. My main frustration with pointers today in legalization and selection patterns is treating most address spaces as "other". i.e. I have a whitelist of address spaces to handle specially, but anything else should be treated as if it were address space 1. This seems to commit to defining more address space specific machinery (although I suppose I can fixup all of these cases in legalization)

llvm/lib/Target/Mips/MipsGISel.td

1

The indentation in this file is all over the place

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir

19

I don't think you need the IR section in this test at all

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select_patterns.mir

3

Shouldn't need the IR section

[Petar.Avramovic]

G_CONSTANT can already directly have a pointer type, so I don't see a reason that the extra G_INTTOPTR needs to be involved.

When I started this patch I thought the same. nullptr was translated like that some time ago, D44762 changed it to what we have now. NullPtrValue was meant to match IRTranslator's translation of llvm-ir null

Are you trying to specifically select pointer differently from integers?

I am trying to select pointers/nullptr exectly like integers i.e. use gpr32/0.
Sdag td files already have Int_Src -> Int_Dst patterns.
I am trying to add Pointer_Src -> Int_Dst that will be used by GlobalISel only since it has pointers in intermediate representation.
It looks like this:

def : MipsPat<(seteq GPR32:$lhs, GPR32:$rhs),
              (SLTiu (XOR GPR32:$lhs, GPR32:$rhs), 1)>;

def : MipsPat<(seteq p0:$lhs, p0:$rhs),
              (SLTiu (XOR GPR32:$lhs, GPR32:$rhs), 1)>;

There should be fewer pointer patterns then integer patterns.

I thought you could already get this to work without distinguishing them with PtrValueType.

If you think of changing pointer type to scalar before isel, I also think that could work (it works in sdag).
I asked about it in http://lists.llvm.org/pipermail/llvm-dev/2019-November/137041.html.

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir

19

I see. I will take a look at other mir tests and fix them all together.

[Petar.Avramovic]

Ping.

[arsenm]

In D72034#1829684, @Petar.Avramovic wrote:

Ping.

I'm going to have to disagree with the change in D44762, and think it should be reverted. null in the IR has the original pointer type, and is not a cast from an integer constant. This presents a problem for non integral address spaces for example, where you are allowed to have a literal null/0 value, but the inttoptr is not allowed. I would prefer if the IR defined a more proper nullptr in the IR that wasn't just a 0 constant, but that's not the current state of the world.

llvm/include/llvm/CodeGen/ValueTypes.td

 /// derived from this class.  The scalar argument should be an
 /// integer type with the same bit size as the ponter.
 /// e.g. def p0 : PtrValueType <i64, 0>;
 
 class PtrValueType <ValueType scalar, int addrspace> :
     ValueType<scalar.Size, scalar.Value> {
   int AddrSpace = addrspace;
 }
+
+/// This class represents nullptr value. First two arguments are same as for
+/// PtrValueType, third is actual integer value that represents nullptr in
+/// addrspace. Targets must define their own null pointers derived from this
+/// class. GlobalISel Emmiter matches NullPtrValue leaf with:
+///    %0:gprb(scalar) = G_CONSTANT intvalue
+///    %1:gprb(p_addrspace) = G_INTTOPTR %0(scalar)
+class NullPtrValue <ValueType scalar, int addrspace, int intvalue> :
+    PtrValueType<scalar, addrspace> {
+  int IntValue = intvalue;
+}

llvm/lib/Target/Mips/CMakeLists.txt

+set(LLVM_TARGET_DEFINITIONS MipsGISel.td)
+
+tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
+tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
+
 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
 tablegen(LLVM MipsGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM MipsGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel)
-tablegen(LLVM MipsGenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM MipsGenMCPseudoLowering.inc -gen-pseudo-lowering)
-tablegen(LLVM MipsGenRegisterBank.inc -gen-register-bank)
 tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM MipsGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM MipsGenExegesis.inc -gen-exegesis)
 
 add_public_tablegen_target(MipsCommonTableGen)
 
 add_llvm_target(MipsCodeGen
   Mips16FrameLowering.cpp

llvm/lib/Target/Mips/MipsGISel.td

+include "Mips.td"
+
+def p0 : PtrValueType<i32, 0>;
+
+  // Pointer compare
+  def : MipsPat<(seteq p0:$lhs, p0:$rhs),
+                (SLTiu (XOR GPR32:$lhs, GPR32:$rhs), 1)>, ISA_MIPS1;
+  def : MipsPat<(setne p0:$lhs, p0:$rhs),
+                (SLTu ZERO, (XOR GPR32:$lhs, GPR32:$rhs))>, ISA_MIPS1;
+  def : MipsPat<(setult p0:$lhs, p0:$rhs),
+                (SLTu GPR32:$rhs, GPR32:$lhs)>, ISA_MIPS1;
+  def : MipsPat<(setule p0:$lhs, p0:$rhs),
+                (XORi (SLTu GPR32:$rhs, GPR32:$lhs), 1)>, ISA_MIPS1;
+  def : MipsPat<(setugt p0:$lhs, p0:$rhs),
+                (SLTu GPR32:$rhs, GPR32:$lhs)>, ISA_MIPS1;
+  def : MipsPat<(setuge p0:$lhs, p0:$rhs),
+                (XORi (SLTu GPR32:$lhs, GPR32:$rhs), 1)>, ISA_MIPS1;
+
+  // Pointer select
+  def : MipsPat<(select GPR32:$cond, p0:$T, p0:$F),
+                (MOVN_I_I GPR32:$T, GPR32:$cond, GPR32:$F)>,
+                INSN_MIPS4_32_NOT_32R6_64R6;
+
+def p0Nullptr : NullPtrValue<i32, 0, 0>;
+
+  // nullptr compare
+  def : MipsPat<(seteq p0:$lhs, p0Nullptr),
+                (SLTiu GPR32:$lhs, 1)>, ISA_MIPS1;
+
+  // 'Select with nullptr compare' pattern
+  def : MipsPat<(select (i32 (setne p0:$lhs, p0Nullptr)),p0:$T, p0:$F),
+                (MOVN_I_I GPR32:$T, GPR32:$lhs, GPR32:$F)>,
+                INSN_MIPS4_32_NOT_32R6_64R6;

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

PseudoMove = BuildMI(MBB, I, I.getDebugLoc(),
                      .addDef(I.getOperand(0).getReg())
                      .addUse(HILOReg);
     if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI))
       return false;
 
     I.eraseFromParent();
     return true;
   }
-  case G_SELECT: {
-    // Handle operands with pointer type.
-    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
-             .add(I.getOperand(0))
-             .add(I.getOperand(2))
-             .add(I.getOperand(1))
-             .add(I.getOperand(3));
-    break;
-  }
   case G_IMPLICIT_DEF: {
     Register Dst = I.getOperand(0).getReg();
     MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
              .addDef(Dst);
 
     // Set class based on register bank, there can be fpr and gpr implicit def.
     MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI));
     break;
case G_JUMP_TABLE: {
     } else {
       MI =
           BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
               .addDef(I.getOperand(0).getReg())
               .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI);
     }
     break;
   }
-  case G_ICMP: {
-    struct Instr {
-      unsigned Opcode;
-      Register Def, LHS, RHS;
-      Instr(unsigned Opcode, Register Def, Register LHS, Register RHS)
-          : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
-
-      bool hasImm() const {
-        if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
-          return true;
-        return false;
-      }
-    };
-
-    SmallVector<struct Instr, 2> Instructions;
-    Register ICMPReg = I.getOperand(0).getReg();
-    Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
-    Register LHS = I.getOperand(2).getReg();
-    Register RHS = I.getOperand(3).getReg();
-    CmpInst::Predicate Cond =
-        static_cast<CmpInst::Predicate>(I.getOperand(1).getPredicate());
-
-    switch (Cond) {
-    case CmpInst::ICMP_EQ: // LHS == RHS -> (LHS ^ RHS) < 1
-      Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
-      Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
-      break;
-    case CmpInst::ICMP_NE: // LHS != RHS -> 0 < (LHS ^ RHS)
-      Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
-      Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
-      break;
-    case CmpInst::ICMP_UGT: // LHS >  RHS -> RHS < LHS
-      Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
-      break;
-    case CmpInst::ICMP_UGE: // LHS >= RHS -> !(LHS < RHS)
-      Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
-      Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
-      break;
-    case CmpInst::ICMP_ULT: // LHS <  RHS -> LHS < RHS
-      Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
-      break;
-    case CmpInst::ICMP_ULE: // LHS <= RHS -> !(RHS < LHS)
-      Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);
-      Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
-      break;
-    case CmpInst::ICMP_SGT: // LHS >  RHS -> RHS < LHS
-      Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
-      break;
-    case CmpInst::ICMP_SGE: // LHS >= RHS -> !(LHS < RHS)
-      Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
-      Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
-      break;
-    case CmpInst::ICMP_SLT: // LHS <  RHS -> LHS < RHS
-      Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
-      break;
-    case CmpInst::ICMP_SLE: // LHS <= RHS -> !(RHS < LHS)
-      Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);
-      Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
-      break;
-    default:
-      return false;
-    }
-
-    MachineIRBuilder B(I);
-    for (const struct Instr &Instruction : Instructions) {
-      MachineInstrBuilder MIB = B.buildInstr(
-          Instruction.Opcode, {Instruction.Def}, {Instruction.LHS});
-
-      if (Instruction.hasImm())
-        MIB.addImm(Instruction.RHS);
-      else
-        MIB.addUse(Instruction.RHS);
-
-      if (!MIB.constrainAllUses(TII, TRI, RBI))
-        return false;
-    }
-
-    I.eraseFromParent();
-    return true;
-  }
   case G_FCMP: {
     unsigned MipsFCMPCondCode;
     bool isLogicallyNegated;
     switch (CmpInst::Predicate Cond = static_cast<CmpInst::Predicate>(
                 I.getOperand(1).getPredicate())) {
     case CmpInst::FCMP_UNO: // Unordered
     case CmpInst::FCMP_ORD: // Ordered (OR)
       MipsFCMPCondCode = Mips::FCOND_UN;

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
 --- |
 
   define void @eq_i32() {entry: ret void}
   define void @ne_i32() {entry: ret void}
   define void @sgt_i32() {entry: ret void}
   define void @sge_i32() {entry: ret void}
   define void @slt_i32() {entry: ret void}
   define void @sle_i32() {entry: ret void}
   define void @ugt_i32() {entry: ret void}
   define void @uge_i32() {entry: ret void}
   define void @ult_i32() {entry: ret void}
   define void @ule_i32() {entry: ret void}
   define void @eq_ptr() {entry: ret void}
+  define void @ne_ptr() {entry: ret void}
+  define void @ugt_ptr() {entry: ret void}
+  define void @uge_ptr() {entry: ret void}
+  define void @ult_ptr() {entry: ret void}
+  define void @ule_ptr() {entry: ret void}
 
 
 ...
 ---
 name:            eq_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
bb.1.entry:
     %0:gprb(p0) = COPY $a0
     %1:gprb(p0) = COPY $a1
     %4:gprb(s32) = G_ICMP intpred(eq), %0(p0), %1
     %3:gprb(s32) = COPY %4(s32)
     $v0 = COPY %3(s32)
     RetRA implicit $v0
 
 ...
+---
+name:            ne_ptr
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ne_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[COPY]], [[COPY1]]
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(ne), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ugt_ptr
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ugt_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(ugt), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            uge_ptr
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: uge_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY]], [[COPY1]]
+    ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
+    ; MIPS32: $v0 = COPY [[XORi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(uge), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ult_ptr
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ult_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
+    ; MIPS32: $v0 = COPY [[SLTu]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(ult), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            ule_ptr
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1
+
+    ; MIPS32-LABEL: name: ule_ptr
+    ; MIPS32: liveins: $a0, $a1
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[COPY1]], [[COPY]]
+    ; MIPS32: [[XORi:%[0-9]+]]:gpr32 = XORi [[SLTu]], 1
+    ; MIPS32: $v0 = COPY [[XORi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %4:gprb(s32) = G_ICMP intpred(ule), %0(p0), %1
+    %3:gprb(s32) = COPY %4(s32)
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/icmp_nullptr.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+  define zeroext i1 @_Z10eq_nullptrPi(i32* %a) {
+  entry:
+    %cmp = icmp eq i32* %a, null
+    ret i1 %cmp
+  }
+
+  define zeroext i1 @_Z7eq_zeroi(i32 %a) {
+  entry:
+    %cmp = icmp eq i32 %a, 0
+    ret i1 %cmp
+  }
+
+...
+---
+name:            _Z10eq_nullptrPi
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: _Z10eq_nullptrPi
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[COPY]], 1
+    ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTiu]], 1
+    ; MIPS32: $v0 = COPY [[ANDi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %2:gprb(s32) = G_CONSTANT i32 0
+    %1:gprb(p0) = G_INTTOPTR %2(s32)
+    %5:gprb(s32) = G_ICMP intpred(eq), %0(p0), %1
+    %6:gprb(s32) = G_CONSTANT i32 1
+    %7:gprb(s32) = COPY %5(s32)
+    %4:gprb(s32) = G_AND %7, %6
+    $v0 = COPY %4(s32)
+    RetRA implicit $v0
+
+...
+---
+name:            _Z7eq_zeroi
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0
+
+    ; MIPS32-LABEL: name: _Z7eq_zeroi
+    ; MIPS32: liveins: $a0
+    ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32: [[SLTiu:%[0-9]+]]:gpr32 = SLTiu [[COPY]], 1
+    ; MIPS32: [[ANDi:%[0-9]+]]:gpr32 = ANDi [[SLTiu]], 1
+    ; MIPS32: $v0 = COPY [[ANDi]]
+    ; MIPS32: RetRA implicit $v0
+    %0:gprb(s32) = COPY $a0
+    %1:gprb(s32) = G_CONSTANT i32 0
+    %4:gprb(s32) = G_ICMP intpred(eq), %0(s32), %1
+    %5:gprb(s32) = G_CONSTANT i32 1
+    %6:gprb(s32) = COPY %4(s32)
+    %3:gprb(s32) = G_AND %6, %5
+    $v0 = COPY %3(s32)
+    RetRA implicit $v0
+
+...

llvm/test/CodeGen/Mips/GlobalISel/instruction-select/select_patterns.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32FP32
+--- |
+  define i32* @select(i32* %Test, i32* %T, i32* %F) {
+  entry:
+    %cmp = icmp ne i32* %Test, null
+    %cond = select i1 %cmp, i32* %F, i32* %T
+    ret i32* %cond
+  }
+
+...
+---
+name:            select
+alignment:       4
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $a0, $a1, $a2
+
+    ; MIPS32FP32-LABEL: name: select
+    ; MIPS32FP32: liveins: $a0, $a1, $a2
+    ; MIPS32FP32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+    ; MIPS32FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY $a1
+    ; MIPS32FP32: [[COPY2:%[0-9]+]]:gpr32 = COPY $a2
+    ; MIPS32FP32: [[MOVN_I_I:%[0-9]+]]:gpr32 = MOVN_I_I [[COPY2]], [[COPY]], [[COPY1]]
+    ; MIPS32FP32: $v0 = COPY [[MOVN_I_I]]
+    ; MIPS32FP32: RetRA implicit $v0
+    %0:gprb(p0) = COPY $a0
+    %1:gprb(p0) = COPY $a1
+    %2:gprb(p0) = COPY $a2
+    %4:gprb(s32) = G_CONSTANT i32 0
+    %3:gprb(p0) = G_INTTOPTR %4(s32)
+    %8:gprb(s32) = G_ICMP intpred(ne), %0(p0), %3
+    %6:gprb(p0) = G_SELECT %8(s32), %2, %1
+    $v0 = COPY %6(p0)
+    RetRA implicit $v0
+
+...

llvm/test/CodeGen/Mips/GlobalISel/irtranslator/icmp_nullptr.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+
+define zeroext i1 @_Z10eq_nullptrPi(i32* %a) {
+  ; MIPS32-LABEL: name: _Z10eq_nullptrPi
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(p0) = COPY $a0
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; MIPS32:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s32)
+  ; MIPS32:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](p0), [[INTTOPTR]]
+  ; MIPS32:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+  ; MIPS32:   $v0 = COPY [[ZEXT]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %cmp = icmp eq i32* %a, null
+  ret i1 %cmp
+}
+
+define zeroext i1 @_Z7eq_zeroi(i32 %a) {
+  ; MIPS32-LABEL: name: _Z7eq_zeroi
+  ; MIPS32: bb.1.entry:
+  ; MIPS32:   liveins: $a0
+  ; MIPS32:   [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+  ; MIPS32:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+  ; MIPS32:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
+  ; MIPS32:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
+  ; MIPS32:   $v0 = COPY [[ZEXT]](s32)
+  ; MIPS32:   RetRA implicit $v0
+entry:
+  %cmp = icmp eq i32 %a, 0
+  ret i1 %cmp
+}

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll

 ; MIPS32-NEXT:    sltiu $2, $1, 1
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop
 entry:
   %cmp = icmp eq i32* %a, %b
   ret i1 %cmp
 }
 
+define i1 @ne_ptr(i32* %a, i32* %b) {
+; MIPS32-LABEL: ne_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    xor $1, $4, $5
+; MIPS32-NEXT:    sltu $2, $zero, $1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ne i32* %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ugt_ptr(i32* %a, i32* %b) {
+; MIPS32-LABEL: ugt_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $2, $5, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ugt i32* %a, %b
+  ret i1 %cmp
+}
+
+define i1 @uge_ptr(i32* %a, i32* %b) {
+; MIPS32-LABEL: uge_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $4, $5
+; MIPS32-NEXT:    xori $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp uge i32* %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ult_ptr(i32* %a, i32* %b) {
+; MIPS32-LABEL: ult_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $2, $5, $4
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ult i32* %a, %b
+  ret i1 %cmp
+}
+
+define i1 @ule_ptr(i32* %a, i32* %b) {
+; MIPS32-LABEL: ule_ptr:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltu $1, $5, $4
+; MIPS32-NEXT:    xori $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp ule i32* %a, %b
+  ret i1 %cmp
+}
+
 define i1 @ult_i8(i8 %a, i8 %b) {
 ; MIPS32-LABEL: ult_i8:
 ; MIPS32:       # %bb.0: # %entry
 ; MIPS32-NEXT:    andi $1, $4, 255
 ; MIPS32-NEXT:    andi $2, $5, 255
 ; MIPS32-NEXT:    sltu $2, $1, $2
 ; MIPS32-NEXT:    jr $ra
 ; MIPS32-NEXT:    nop

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp_nullptr.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc  -O0 -mtriple=mipsel-linux-gnu -global-isel  -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+
+define zeroext i1 @_Z10eq_nullptrPi(i32* %a) {
+; MIPS32-LABEL: _Z10eq_nullptrPi:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltiu $1, $4, 1
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp eq i32* %a, null
+  ret i1 %cmp
+}
+define zeroext i1 @_Z7eq_zeroi(i32 %a) {
+; MIPS32-LABEL: _Z7eq_zeroi:
+; MIPS32:       # %bb.0: # %entry
+; MIPS32-NEXT:    sltiu $1, $4, 1
+; MIPS32-NEXT:    andi $2, $1, 1
+; MIPS32-NEXT:    jr $ra
+; MIPS32-NEXT:    nop
+entry:
+  %cmp = icmp eq i32 %a, 0
+  ret i1 %cmp
+}

llvm/test/TableGen/Common/GlobalISelEmitterCommon.td

 // Common target boilerplate for GlobalISelEmitter tests.
 def MyTargetISA : InstrInfo;
 def MyTarget : Target { let InstructionSet = MyTargetISA; }
 
 def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
 def GPR32Op : RegisterOperand<GPR32>;
 def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
 def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
 def FPR32Op : RegisterOperand<FPR32>;
 def p0 : PtrValueType <i32, 0>;
+def p0Nullptr : NullPtrValue <i32, 0, 123>;
 
 class I<dag OOps, dag IOps, list<dag> Pat>
   : Instruction {
   let Namespace = "MyTarget";
   let OutOperandList = OOps;
   let InOperandList = IOps;
   let Pattern = Pat;
 }

llvm/test/TableGen/GlobalISelEmitter.td

 // NOOPT-NEXT:    // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2))  =>  (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MULADD,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
-// NOOPT-NEXT:    // GIR_Coverage, 26,
+// NOOPT-NEXT:    // GIR_Coverage, 27,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
                [(set GPR32:$dst,
                      (mul (add GPR32:$src1, GPR32:$src2), GPR32:$src3))]>,
              Requires<[HasA]>;
 

 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // NOOPT-NEXT:    // GIR_Coverage, 12,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
                  [(set GPR32:$dst, (sextloadi16 GPR32:$src1))]>;
 
+//===- Test a simple pattern with explicit nullptr operand. ---------------===//
+
+// NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
+// NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
+// NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ICMP,
+// NOOPT-NEXT:    // MIs[0] scr
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
+// NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
+// NOOPT-NEXT:    // MIs[0] Operand 1
+// NOOPT-NEXT:    GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
+// NOOPT-NEXT:    // MIs[0] lhs
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_p0s32,
+// NOOPT-NEXT:    // MIs[0] Operand 3
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_p0s32,
+// NOOPT-NEXT:    GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
+// NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/1, /*Expected*/2,
+// NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTTOPTR,
+// NOOPT-NEXT:    // MIs[1] Operand 0
+// NOOPT-NEXT:    GIM_CheckPointerToAny, /*MI*/1, /*Op*/0, /*SizeInBits*/32,
+// NOOPT-NEXT:    // MIs[1] Operand 1
+// NOOPT-NEXT:    GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
+// NOOPT-NEXT:    GIM_CheckConstantInt, /*MI*/1, /*Op*/1, 123,
+// NOOPT-NEXT:    GIM_CheckIsSafeToFold, /*InsnID*/1,
+// NOOPT-NEXT:    // (setcc:{ *:[i32] } p0:{ *:[i32] }:$lhs, p0Nullptr:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
+// NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN5,
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // scr
+// NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // lhs
+// NOOPT-NEXT:    GIR_AddImm, /*InsnID*/0, /*Imm*/1,
+// NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
+// NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// NOOPT-NEXT:    // GIR_Coverage, 24,
+// NOOPT-NEXT:    GIR_Done,
+// NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
+
+def INSN5 : I<(outs GPR32:$scr), (ins GPR32:$src3, i32imm:$src5a), []>;
+def : Pat<(seteq p0:$lhs, p0Nullptr),
+          (INSN5 GPR32:$lhs, 1)>;
+
 //===- Test a simple pattern with regclass operands. ----------------------===//
 //
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
 // NOOPT-NEXT:    // MIs[0] dst
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,

 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    // MIs[0] src2
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::ADD,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
-// NOOPT-NEXT:    // GIR_Coverage, 24,
+// NOOPT-NEXT:    // GIR_Coverage, 25,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def : Pat<(add i32:$src1, i32:$src2),
           (ADD i32:$src1, i32:$src2)>;
 
 //===- Test another simple pattern with regclass operands. ----------------===//
 //

 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] src1
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::FPR32RegClassID,
 // NOOPT-NEXT:    // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] })
 // NOOPT-NEXT:    GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/TargetOpcode::COPY,
 // NOOPT-NEXT:    GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, /*RC GPR32*/1,
-// NOOPT-NEXT:    // GIR_Coverage, 25,
+// NOOPT-NEXT:    // GIR_Coverage, 26,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def : Pat<(i32 (bitconvert FPR32:$src1)),
           (COPY_TO_REGCLASS FPR32:$src1, GPR32)>;
 
 //===- Test a simple pattern with just a leaf immediate. ------------------===//
 //

llvm/utils/TableGen/CodeGenDAGPatterns.cpp

if (R->isSubClassOf("Register")) {
     return TypeSetByHwMode(T.getRegisterVTs(R));
   }
 
   if (R->isSubClassOf("SubRegIndex")) {
     assert(ResNo == 0 && "SubRegisterIndices only produce one result!");
     return TypeSetByHwMode(MVT::i32);
   }
 
+  if (R->isSubClassOf("NullPtrValue")) {
+    assert (Unnamed && "Named NullPtrValue");
+    const CodeGenHwModes &CGH = CDP.getTargetInfo().getHwModes();
+    return TypeSetByHwMode(getValueTypeByHwMode(R, CGH));
+  }
+
   if (R->isSubClassOf("ValueType")) {
     assert(ResNo == 0 && "This node only has one result!");
     // An unnamed VTSDNode represents itself as an MVT::Other immediate.
     //
     //   (sext_inreg GPR:$src, i16)
     //                         ~~~
     if (Unnamed)
       return TypeSetByHwMode(MVT::Other);

llvm/utils/TableGen/GlobalISelEmitter.cpp

if (ChildRec->isSubClassOf("Register")) {
         return failedImport(
           "Could not determine physical register class of pattern source");
       }
 
       OM.addPredicate<RegisterBankOperandMatcher>(*RC);
       return Error::success();
     }
 
+    // Check for nullptr ValueType.
+    if (ChildRec->isSubClassOf("NullPtrValue")) {
+      auto IntToPtrDefOM = OM.addPredicate<InstructionOperandMatcher>(
+          InsnMatcher.getRuleMatcher(), "");
+      InstructionMatcher &IntToPtrInsnMatcher =
+          (*IntToPtrDefOM)->getInsnMatcher();
+      IntToPtrInsnMatcher.addPredicate<InstructionOpcodeMatcher>(
+          &Target.getInstruction(RK.getDef("G_INTTOPTR")));
+
+      OperandMatcher &OM0 = IntToPtrInsnMatcher.addOperand(0, "", TempOpIdx);
+      if (auto Error = OM0.addTypeCheckPredicate(ChildTypes.front(), true))
+        return failedImport(toString(std::move(Error)) +
+                            " for result of Src pattern operator");
+
+      OperandMatcher &OM1 = IntToPtrInsnMatcher.addOperand(1, "", TempOpIdx);
+      TypeSetByHwMode IntPtrTy(
+          (MVT::SimpleValueType)ChildRec->getValueAsInt("Value"));
+      if (auto Error = OM1.addTypeCheckPredicate(IntPtrTy, false))
+        return failedImport(toString(std::move(Error)) +
+                            " for result of Src pattern operator");
+      OM1.addPredicate<ConstantIntOperandMatcher>(
+          ChildRec->getValueAsInt("IntValue"));
+      return Error::success();
+    }
+
     // Check for ValueType.
     if (ChildRec->isSubClassOf("ValueType")) {
       // We already added a type check as standard practice so this doesn't need
       // to do anything.
       return Error::success();
     }
 
     // Check for ComplexPattern's.