Index: llvm/lib/Target/ARM/ARM.td
===================================================================
--- llvm/lib/Target/ARM/ARM.td
+++ llvm/lib/Target/ARM/ARM.td
@@ -407,6 +407,11 @@
                                              "equivalent when the immediate does "
                                              "not fit in the encoding.">;
 
+def FeatureIgnoreRestrictIT : SubtargetFeature<"unrestricted-it-blocks",
+                                               "IgnoreRestrictIT", "true",
+                                               "Don't restrict V8 IT blocks to a "
+                                               "single instruction.">;
+
 // Use the MachineScheduler for instruction scheduling for the subtarget.
 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
                                         "Use the MachineScheduler">;
@@ -1147,7 +1152,8 @@
 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
-                                                         FeatureDotProd]>;
+                                                         FeatureDotProd,
+                                                         FeatureIgnoreRestrictIT]>;
 
 def : ProcNoItin<"cortex-a76",                          [ARMv82a, ProcA76,
                                                          FeatureHWDivThumb,
@@ -1155,7 +1161,8 @@
                                                          FeatureCrypto,
                                                          FeatureCRC,
                                                          FeatureFullFP16,
-                                                         FeatureDotProd]>;
+                                                         FeatureDotProd,
+                                                         FeatureIgnoreRestrictIT]>;
 
 def : ProcNoItin<"cortex-a76ae",                        [ARMv82a, ProcA76,
                                                          FeatureHWDivThumb,
@@ -1163,14 +1170,16 @@
                                                          FeatureCrypto,
                                                          FeatureCRC,
                                                          FeatureFullFP16,
-                                                         FeatureDotProd]>;
+                                                         FeatureDotProd,
+                                                         FeatureIgnoreRestrictIT]>;
 
 def : ProcNoItin<"neoverse-n1",                         [ARMv82a,
                                                          FeatureHWDivThumb,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC,
-                                                         FeatureDotProd]>;
+                                                         FeatureDotProd,
+                                                         FeatureIgnoreRestrictIT]>;
 
 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
                                                          FeatureHasRetAddrStack,
Index: llvm/lib/Target/ARM/ARMSubtarget.h
===================================================================
--- llvm/lib/Target/ARM/ARMSubtarget.h
+++ llvm/lib/Target/ARM/ARMSubtarget.h
@@ -418,6 +418,10 @@
   ///  blocks to conform to ARMv8 rule.
   bool RestrictIT = false;
 
+  /// IgnoreRestrictIT - If true, ignore the armv8 limitation of a single
+  /// instruction within an IT block.
+  bool IgnoreRestrictIT = false;
+
   /// HasDSP - If true, the subtarget supports the DSP (saturating arith
   /// and such) instructions.
   bool HasDSP = false;
@@ -789,7 +793,7 @@
 
   bool allowsUnalignedMem() const { return !StrictAlign; }
 
-  bool restrictIT() const { return RestrictIT; }
+  bool restrictIT() const { return RestrictIT && !IgnoreRestrictIT; }
 
   const std::string & getCPUString() const { return CPUString; }
 
Index: llvm/lib/Target/ARM/ARMSubtarget.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -241,6 +241,7 @@
     break;
   case RestrictedIT:
     RestrictIT = true;
+    IgnoreRestrictIT = false;
     break;
   case NoRestrictedIT:
     RestrictIT = false;
Index: llvm/test/CodeGen/Thumb2/v8_deprecate_IT.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/v8_deprecate_IT.ll
+++ llvm/test/CodeGen/Thumb2/v8_deprecate_IT.ll
@@ -2,6 +2,11 @@
 ; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it -o - | llvm-mc -triple thumbv7 --show-encoding 2>&1 | FileCheck %s --check-prefix=V7_RESTRICT_IT
 ; RUN: llc < %s -mtriple=thumbv8 -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8
 ; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8_NO_RESTRICT_IT
+; RUN: llc < %s -mtriple=thumbv8 -mcpu=cortex-a75 -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8_NO_RESTRICT_IT
+; RUN: llc < %s -mtriple=thumbv8 -mcpu=cortex-a76 -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8_NO_RESTRICT_IT
+; RUN: llc < %s -mtriple=thumbv8 -mcpu=cortex-a76ae -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8_NO_RESTRICT_IT
+; RUN: llc < %s -mtriple=thumbv8 -mcpu=neoverse-n1 -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8_NO_RESTRICT_IT
+; RUN: llc < %s -mtriple=thumbv8 -mcpu=cortex-a76 -arm-restrict-it -o - | llvm-mc -triple thumbv8 --show-encoding 2>&1 | FileCheck %s --check-prefix=V8
 
 
 ; V7-NOT: warning