Index: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -901,6 +901,11 @@
           LLVM_DEBUG(MI.dump());
 
           if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) {
+            if (MRI->hasOneNonDBGUse(FoldingReg)) {
+              ToErase = SrcMI;
+              LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
+              LLVM_DEBUG(SrcMI->dump());
+            }
             // Replace MI with "LI 0"
             MI.RemoveOperand(4);
             MI.RemoveOperand(3);
@@ -919,8 +924,12 @@
 
           LLVM_DEBUG(dbgs() << "With: ");
           LLVM_DEBUG(MI.dump());
-        } else if (isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB,
-                               NewME) || SrcMaskFull) {
+        } else if ((MBSrc < MESrc && 
+                    isRunOfOnes((unsigned)(FinalMask.getZExtValue()),
+                                NewMB, NewME)) || SrcMaskFull) {
+          // If MBSrc >= MESrc which is a wrapping mask, give up as we need the 
+          // MI to clear the bits [0, 31].
+
           // If FoldingReg has only one use and it it not RLWINMo and
           // RLWINM8o, safe to delete its def SrcMI. Otherwise keep it.
           if (MRI->hasOneNonDBGUse(FoldingReg) &&
Index: llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+++ llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -11,7 +11,7 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 31
-    ; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 5, 31
+    ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
     ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
     BLR8 implicit $lr8, implicit $rm
@@ -26,7 +26,7 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 0, 31
-    ; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 0, 31
+    ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 0, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
     ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
     BLR8 implicit $lr8, implicit $rm
@@ -41,7 +41,7 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 10, 9 
-    ; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 10, 9
+    ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 10, 9
     %3:gprc = RLWINM %2:gprc, 19, 10, 1
     ; CHECK: %3:gprc = RLWINM %1, 14, 10, 1
     BLR8 implicit $lr8, implicit $rm
@@ -56,9 +56,9 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 30, 10
-    ; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 30 ,10 
+    ; CHECK: %2:gprc = RLWINM %1, 27, 30, 10 
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 11, 12
+    ; CHECK: %3:gprc = RLWINM %2, 19, 0, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
@@ -71,7 +71,7 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 10, 5, 31
-    ; CHECKT: %2:gprc = RLWINM %1:gprc, 10, 5, 31
+    ; CHECK: %2:gprc = RLWINM %1, 10, 5, 31
     %3:gprc = RLWINM %2:gprc, 10, 30, 5
     ; CHECK: %3:gprc = RLWINM %2, 10, 30, 5
     BLR8 implicit $lr8, implicit $rm
@@ -103,7 +103,7 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 10
-    ; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 5, 10
+    ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 5, 10
     %3:gprc = RLWINM %2:gprc, 8, 5, 10
     ; CHECK: %3:gprc = LI 0
     BLR8 implicit $lr8, implicit $rm
@@ -118,7 +118,7 @@
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 10
-    ; CHECK-NOT: %2:gprc = RLWINM %1:gprc, 27, 5, 10
+    ; CHECK: %2:gprc = RLWINM %1, 27, 5, 10
     %3:gprc = RLWINMo %2:gprc, 8, 5, 10, implicit-def $cr0
     ; CHECK: %3:gprc = ANDIo %2, 0, implicit-def $cr0
     BLR8 implicit $lr8, implicit $rm