diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
@@ -36,13 +36,16 @@
   MCOperand &getValueFor(const Operand &Op);
   const MCOperand &getValueFor(const Operand &Op) const;
   bool hasImmediateVariables() const;
+  const Instruction &getInstr() const { return *Instr; }
+  ArrayRef<MCOperand> getVariableValues() const { return VariableValues; }
 
   // Builds an MCInst from this InstructionTemplate setting its operands
   // to the corresponding variable values. Precondition: All VariableValues must
   // be set.
   MCInst build() const;
 
-  Instruction Instr;
+private:
+  const Instruction *Instr;
   SmallVector<MCOperand, 4> VariableValues;
 };
 
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
@@ -16,7 +16,7 @@
 CodeTemplate &CodeTemplate::operator=(CodeTemplate &&) = default;
 
 InstructionTemplate::InstructionTemplate(const Instruction &Instr)
-    : Instr(Instr), VariableValues(Instr.Variables.size()) {}
+    : Instr(&Instr), VariableValues(Instr.Variables.size()) {}
 
 InstructionTemplate::InstructionTemplate(InstructionTemplate &&) = default;
 
@@ -29,7 +29,7 @@
 operator=(const InstructionTemplate &) = default;
 
 unsigned InstructionTemplate::getOpcode() const {
-  return Instr.Description->getOpcode();
+  return Instr->Description.getOpcode();
 }
 
 MCOperand &InstructionTemplate::getValueFor(const Variable &Var) {
@@ -41,23 +41,23 @@
 }
 
 MCOperand &InstructionTemplate::getValueFor(const Operand &Op) {
-  return getValueFor(Instr.Variables[Op.getVariableIndex()]);
+  return getValueFor(Instr->Variables[Op.getVariableIndex()]);
 }
 
 const MCOperand &InstructionTemplate::getValueFor(const Operand &Op) const {
-  return getValueFor(Instr.Variables[Op.getVariableIndex()]);
+  return getValueFor(Instr->Variables[Op.getVariableIndex()]);
 }
 
 bool InstructionTemplate::hasImmediateVariables() const {
-  return any_of(Instr.Variables, [this](const Variable &Var) {
-    return Instr.getPrimaryOperand(Var).isImmediate();
+  return any_of(Instr->Variables, [this](const Variable &Var) {
+    return Instr->getPrimaryOperand(Var).isImmediate();
   });
 }
 
 MCInst InstructionTemplate::build() const {
   MCInst Result;
-  Result.setOpcode(Instr.Description->Opcode);
-  for (const auto &Op : Instr.Operands)
+  Result.setOpcode(Instr->Description.Opcode);
+  for (const auto &Op : Instr->Operands)
     if (Op.isExplicit())
       Result.addOperand(getValueFor(Op));
   return Result;
diff --git a/llvm/tools/llvm-exegesis/lib/Latency.cpp b/llvm/tools/llvm-exegesis/lib/Latency.cpp
--- a/llvm/tools/llvm-exegesis/lib/Latency.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Latency.cpp
@@ -37,7 +37,7 @@
 
 static constexpr size_t kMaxAliasingInstructions = 10;
 
-static std::vector<Instruction>
+static std::vector<std::reference_wrapper<const Instruction>>
 computeAliasingInstructions(const LLVMState &State, const Instruction &Instr,
                             size_t MaxAliasingInstructions,
                             const BitVector &ForbiddenRegisters) {
@@ -47,9 +47,9 @@
   std::iota(Opcodes.begin(), Opcodes.end(), 0U);
   std::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator());
 
-  std::vector<Instruction> AliasingInstructions;
+  std::vector<std::reference_wrapper<const Instruction>> AliasingInstructions;
   for (const unsigned OtherOpcode : Opcodes) {
-    if (OtherOpcode == Instr.Description->getOpcode())
+    if (OtherOpcode == Instr.Description.getOpcode())
       continue;
     const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
     if (OtherInstr.hasMemoryOperands())
@@ -125,7 +125,7 @@
   }
   case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: {
     // Select back-to-back non-memory instruction.
-    for (const auto OtherInstr : computeAliasingInstructions(
+    for (const auto &OtherInstr : computeAliasingInstructions(
              State, Instr, kMaxAliasingInstructions, ForbiddenRegisters)) {
       const AliasingConfigurations Forward(Instr, OtherInstr);
       const AliasingConfigurations Back(OtherInstr, Instr);
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
@@ -48,7 +48,7 @@
 
   // The index of this Variable in Instruction.Variables and its associated
   // Value in InstructionBuilder.VariableValues.
-  int Index = -1;
+  Optional<uint8_t> Index;
 };
 
 // MCOperandInfo can only represents Explicit operands. This object gives a
@@ -81,20 +81,43 @@
   const MCOperandInfo &getExplicitOperandInfo() const;
 
   // Please use the accessors above and not the following fields.
-  int Index = -1;
+  Optional<uint8_t> Index;
   bool IsDef = false;
   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
   const MCOperandInfo *Info = nullptr;              // Set for Explicit Op.
-  int TiedToIndex = -1;                             // Set for Reg&Explicit Op.
+  Optional<uint8_t> TiedToIndex;                    // Set for Reg&Explicit Op.
   const MCPhysReg *ImplicitReg = nullptr;           // Set for Implicit Op.
-  int VariableIndex = -1;                           // Set for Explicit Op.
+  Optional<uint8_t> VariableIndex;                  // Set for Explicit Op.
+};
+
+/// A cache of BitVector to reuse between Instructions.
+/// The cache will only be exercised during Instruction initialization.
+/// For X86, this is ~160 unique vectors for all of the ~15K Instructions.
+struct UniqueBitVector {
+  const BitVector *get(BitVector &&) const;
+
+private:
+  mutable SmallVector<std::unique_ptr<BitVector>, 0> Cache;
 };
 
 // A view over an MCInstrDesc offering a convenient interface to compute
 // Register aliasing.
 struct Instruction {
-  Instruction(const MCInstrInfo &InstrInfo,
-              const RegisterAliasingTrackerCache &RATC, unsigned Opcode);
+  Instruction(const MCInstrDesc *Description, StringRef Name,
+              SmallVector<Operand, 8> Operands,
+              SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
+              const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
+              const BitVector *AllUseRegs);
+  // Prevent copy or move, instructions are allocated once and cached.
+  Instruction(const Instruction &) = delete;
+  Instruction(Instruction &&) = delete;
+  Instruction &operator=(const Instruction &) = delete;
+  Instruction &operator=(Instruction &&) = delete;
+
+  // Create an instruction for a particular Opcode.
+  static std::unique_ptr<Instruction>
+  create(const MCInstrInfo &InstrInfo, const RegisterAliasingTrackerCache &RATC,
+         const UniqueBitVector &UBV, unsigned Opcode);
 
   // Returns the Operand linked to this Variable.
   // In case the Variable is tied, the primary (i.e. Def) Operand is returned.
@@ -133,14 +156,14 @@
             const RegisterAliasingTrackerCache &RATC,
             raw_ostream &Stream) const;
 
-  const MCInstrDesc *Description; // Never nullptr.
-  StringRef Name;                 // The name of this instruction.
-  SmallVector<Operand, 8> Operands;
-  SmallVector<Variable, 4> Variables;
-  BitVector ImplDefRegs; // The set of aliased implicit def registers.
-  BitVector ImplUseRegs; // The set of aliased implicit use registers.
-  BitVector AllDefRegs;  // The set of all aliased def registers.
-  BitVector AllUseRegs;  // The set of all aliased use registers.
+  const MCInstrDesc &Description;
+  const StringRef Name; // The name of this instruction.
+  const SmallVector<Operand, 8> Operands;
+  const SmallVector<Variable, 4> Variables;
+  const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
+  const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
+  const BitVector &AllDefRegs;  // The set of all aliased def registers.
+  const BitVector &AllUseRegs;  // The set of all aliased use registers.
 };
 
 // Instructions are expensive to instantiate. This class provides a cache of
@@ -157,6 +180,7 @@
   const RegisterAliasingTrackerCache &RATC;
   mutable std::unordered_map<unsigned, std::unique_ptr<Instruction>>
       Instructions;
+  const UniqueBitVector UBV;
 };
 
 // Represents the assignment of a Register to an Operand.
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -17,10 +17,7 @@
 namespace llvm {
 namespace exegesis {
 
-unsigned Variable::getIndex() const {
-  assert(Index >= 0 && "Index must be set");
-  return Index;
-}
+unsigned Variable::getIndex() const { return *Index; }
 
 unsigned Variable::getPrimaryOperandIndex() const {
   assert(!TiedOperands.empty());
@@ -36,10 +33,7 @@
   return TiedOperands.size() > 1;
 }
 
-unsigned Operand::getIndex() const {
-  assert(Index >= 0 && "Index must be set");
-  return Index;
-}
+unsigned Operand::getIndex() const { return *Index; }
 
 bool Operand::isExplicit() const { return Info; }
 
@@ -53,9 +47,9 @@
 
 bool Operand::isReg() const { return Tracker; }
 
-bool Operand::isTied() const { return TiedToIndex >= 0; }
+bool Operand::isTied() const { return TiedToIndex.hasValue(); }
 
-bool Operand::isVariable() const { return VariableIndex >= 0; }
+bool Operand::isVariable() const { return VariableIndex.hasValue(); }
 
 bool Operand::isMemory() const {
   return isExplicit() &&
@@ -67,17 +61,9 @@
          getExplicitOperandInfo().OperandType == MCOI::OPERAND_IMMEDIATE;
 }
 
-unsigned Operand::getTiedToIndex() const {
-  assert(isTied() && "Operand must be tied to get the tied index");
-  assert(TiedToIndex >= 0 && "TiedToIndex must be set");
-  return TiedToIndex;
-}
+unsigned Operand::getTiedToIndex() const { return *TiedToIndex; }
 
-unsigned Operand::getVariableIndex() const {
-  assert(isVariable() && "Operand must be variable to get the Variable index");
-  assert(VariableIndex >= 0 && "VariableIndex must be set");
-  return VariableIndex;
-}
+unsigned Operand::getVariableIndex() const { return *VariableIndex; }
 
 unsigned Operand::getImplicitReg() const {
   assert(ImplicitReg);
@@ -93,12 +79,35 @@
   assert(Info);
   return *Info;
 }
+const BitVector *UniqueBitVector::get(BitVector &&BV) const {
+  for (const auto &Entry : Cache)
+    if (*Entry == BV)
+      return Entry.get();
+  auto &Entry = Cache.emplace_back(new BitVector());
+  Entry->swap(BV);
+  return Entry.get();
+}
 
-Instruction::Instruction(const MCInstrInfo &InstrInfo,
-                         const RegisterAliasingTrackerCache &RATC,
-                         unsigned Opcode)
-    : Description(&InstrInfo.get(Opcode)), Name(InstrInfo.getName(Opcode)) {
+Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
+                         SmallVector<Operand, 8> Operands,
+                         SmallVector<Variable, 4> Variables,
+                         const BitVector *ImplDefRegs,
+                         const BitVector *ImplUseRegs,
+                         const BitVector *AllDefRegs,
+                         const BitVector *AllUseRegs)
+    : Description(*Description), Name(Name), Operands(std::move(Operands)),
+      Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
+      ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
+      AllUseRegs(*AllUseRegs) {}
+
+std::unique_ptr<Instruction>
+Instruction::create(const MCInstrInfo &InstrInfo,
+                    const RegisterAliasingTrackerCache &RATC,
+                    const UniqueBitVector &UBV, unsigned Opcode) {
+  const llvm::MCInstrDesc *const Description = &InstrInfo.get(Opcode);
   unsigned OpIndex = 0;
+  SmallVector<Operand, 8> Operands;
+  SmallVector<Variable, 4> Variables;
   for (; OpIndex < Description->getNumOperands(); ++OpIndex) {
     const auto &OpInfo = Description->opInfo_begin()[OpIndex];
     Operand Operand;
@@ -107,8 +116,11 @@
     // TODO(gchatelet): Handle isLookupPtrRegClass.
     if (OpInfo.RegClass >= 0)
       Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
-    Operand.TiedToIndex =
-        Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
+    int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
+    assert(TiedToIndex == -1 ||
+           TiedToIndex < std::numeric_limits<uint8_t>::max());
+    if (TiedToIndex >= 0)
+      Operand.TiedToIndex = TiedToIndex;
     Operand.Info = &OpInfo;
     Operands.push_back(Operand);
   }
@@ -130,28 +142,29 @@
     Operand.ImplicitReg = MCPhysReg;
     Operands.push_back(Operand);
   }
-  // Assigning Variables to non tied explicit operands.
   Variables.reserve(Operands.size()); // Variables.size() <= Operands.size()
+  // Assigning Variables to non tied explicit operands.
   for (auto &Op : Operands)
     if (Op.isExplicit() && !Op.isTied()) {
       const size_t VariableIndex = Variables.size();
+      assert(VariableIndex < std::numeric_limits<uint8_t>::max());
       Op.VariableIndex = VariableIndex;
       Variables.emplace_back();
       Variables.back().Index = VariableIndex;
     }
   // Assigning Variables to tied operands.
   for (auto &Op : Operands)
-    if (Op.isTied())
+    if (Op.isExplicit() && Op.isTied())
       Op.VariableIndex = Operands[Op.getTiedToIndex()].getVariableIndex();
   // Assigning Operands to Variables.
   for (auto &Op : Operands)
     if (Op.isVariable())
       Variables[Op.getVariableIndex()].TiedOperands.push_back(Op.getIndex());
   // Processing Aliasing.
-  ImplDefRegs = RATC.emptyRegisters();
-  ImplUseRegs = RATC.emptyRegisters();
-  AllDefRegs = RATC.emptyRegisters();
-  AllUseRegs = RATC.emptyRegisters();
+  BitVector ImplDefRegs = RATC.emptyRegisters();
+  BitVector ImplUseRegs = RATC.emptyRegisters();
+  BitVector AllDefRegs = RATC.emptyRegisters();
+  BitVector AllUseRegs = RATC.emptyRegisters();
   for (const auto &Op : Operands) {
     if (Op.isReg()) {
       const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
@@ -165,6 +178,11 @@
         ImplUseRegs |= AliasingBits;
     }
   }
+  return std::make_unique<Instruction>(
+      Description, InstrInfo.getName(Opcode), std::move(Operands),
+      std::move(Variables), UBV.get(std::move(ImplDefRegs)),
+      UBV.get(std::move(ImplUseRegs)), UBV.get(std::move(AllDefRegs)),
+      UBV.get(std::move(AllUseRegs)));
 }
 
 const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
@@ -284,7 +302,7 @@
 const Instruction &InstructionsCache::getInstr(unsigned Opcode) const {
   auto &Found = Instructions[Opcode];
   if (!Found)
-    Found.reset(new Instruction(InstrInfo, RATC, Opcode));
+    Found = Instruction::create(InstrInfo, RATC, UBV, Opcode);
   return *Found;
 }
 
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -112,7 +112,7 @@
       return 0;
     };
     // Collect used registers that have never been def'ed.
-    for (const Operand &Op : IT.Instr.Operands) {
+    for (const Operand &Op : IT.getInstr().Operands) {
       if (Op.isUse()) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0 && !DefinedRegs.test(Reg)) {
@@ -122,7 +122,7 @@
       }
     }
     // Mark defs as having been def'ed.
-    for (const Operand &Op : IT.Instr.Operands) {
+    for (const Operand &Op : IT.getInstr().Operands) {
       if (Op.isDef()) {
         const unsigned Reg = GetOpReg(Op);
         if (Reg > 0)
@@ -218,10 +218,11 @@
 void randomizeUnsetVariables(const ExegesisTarget &Target,
                              const BitVector &ForbiddenRegs,
                              InstructionTemplate &IT) {
-  for (const Variable &Var : IT.Instr.Variables) {
+  for (const Variable &Var : IT.getInstr().Variables) {
     MCOperand &AssignedValue = IT.getValueFor(Var);
     if (!AssignedValue.isValid())
-      Target.randomizeMCOperand(IT.Instr, Var, AssignedValue, ForbiddenRegs);
+      Target.randomizeMCOperand(IT.getInstr(), Var, AssignedValue,
+                                ForbiddenRegs);
   }
 }
 
diff --git a/llvm/tools/llvm-exegesis/lib/Uops.cpp b/llvm/tools/llvm-exegesis/lib/Uops.cpp
--- a/llvm/tools/llvm-exegesis/lib/Uops.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Uops.cpp
@@ -127,7 +127,7 @@
   std::vector<BitVector> PossibleRegsForVar;
   for (const Variable *Var : TiedVariables) {
     assert(Var);
-    const Operand &Op = IT.Instr.getPrimaryOperand(*Var);
+    const Operand &Op = IT.getInstr().getPrimaryOperand(*Var);
     assert(Op.isReg());
     BitVector PossibleRegs = Op.getRegisterAliasing().sourceBits();
     remove(PossibleRegs, ForbiddenRegisters);
diff --git a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
--- a/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/X86/Target.cpp
@@ -25,7 +25,7 @@
 // Returns an error if we cannot handle the memory references in this
 // instruction.
 static Error isInvalidMemoryInstr(const Instruction &Instr) {
-  switch (Instr.Description->TSFlags & X86II::FormMask) {
+  switch (Instr.Description.TSFlags & X86II::FormMask) {
   default:
     llvm_unreachable("Unknown FormMask value");
   // These have no memory access.
@@ -114,10 +114,10 @@
   case X86II::RawFrmImm8:
     return Error::success();
   case X86II::AddRegFrm:
-    return (Instr.Description->Opcode == X86::POP16r ||
-            Instr.Description->Opcode == X86::POP32r ||
-            Instr.Description->Opcode == X86::PUSH16r ||
-            Instr.Description->Opcode == X86::PUSH32r)
+    return (Instr.Description.Opcode == X86::POP16r ||
+            Instr.Description.Opcode == X86::POP32r ||
+            Instr.Description.Opcode == X86::PUSH16r ||
+            Instr.Description.Opcode == X86::PUSH32r)
                ? make_error<Failure>(
                      "unsupported opcode: unsupported memory access")
                : Error::success();
@@ -150,7 +150,7 @@
 
 static Error IsInvalidOpcode(const Instruction &Instr) {
   const auto OpcodeName = Instr.Name;
-  if ((Instr.Description->TSFlags & X86II::FormMask) == X86II::Pseudo)
+  if ((Instr.Description.TSFlags & X86II::FormMask) == X86II::Pseudo)
     return make_error<Failure>("unsupported opcode: pseudo instruction");
   if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
       OpcodeName.startswith("ADJCALLSTACK"))
@@ -172,13 +172,13 @@
 }
 
 static unsigned getX86FPFlags(const Instruction &Instr) {
-  return Instr.Description->TSFlags & X86II::FPTypeMask;
+  return Instr.Description.TSFlags & X86II::FPTypeMask;
 }
 
 // Helper to fill a memory operand with a value.
 static void setMemOp(InstructionTemplate &IT, int OpIdx,
                      const MCOperand &OpVal) {
-  const auto Op = IT.Instr.Operands[OpIdx];
+  const auto Op = IT.getInstr().Operands[OpIdx];
   assert(Op.isExplicit() && "invalid memory pattern");
   IT.getValueFor(Op) = OpVal;
 }
@@ -190,7 +190,7 @@
     const LLVMState &State, const SnippetGenerator::Options &Opts,
     std::function<unsigned(unsigned, unsigned)> GetDestReg) {
   assert(Instr.Operands.size() == 6 && "invalid LEA");
-  assert(X86II::getMemoryOperandNo(Instr.Description->TSFlags) == 1 &&
+  assert(X86II::getMemoryOperandNo(Instr.Description.TSFlags) == 1 &&
          "invalid LEA");
 
   constexpr const int kDestOp = 0;
@@ -259,7 +259,7 @@
     return std::move(E);
 
   // LEA gets special attention.
-  const auto Opcode = Instr.Description->getOpcode();
+  const auto Opcode = Instr.Description.getOpcode();
   if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
     return generateLEATemplatesCommon(Instr, ForbiddenRegisters, State, Opts,
                                       [](unsigned BaseReg, unsigned IndexReg) {
@@ -310,7 +310,7 @@
     return std::move(E);
 
   // LEA gets special attention.
-  const auto Opcode = Instr.Description->getOpcode();
+  const auto Opcode = Instr.Description.getOpcode();
   if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r) {
     // Any destination register that is not used for adddressing is fine.
     auto PossibleDestRegs =
@@ -648,13 +648,13 @@
 void ExegesisX86Target::fillMemoryOperands(InstructionTemplate &IT,
                                            unsigned Reg,
                                            unsigned Offset) const {
-  assert(!isInvalidMemoryInstr(IT.Instr) &&
+  assert(!isInvalidMemoryInstr(IT.getInstr()) &&
          "fillMemoryOperands requires a valid memory instruction");
-  int MemOpIdx = X86II::getMemoryOperandNo(IT.Instr.Description->TSFlags);
+  int MemOpIdx = X86II::getMemoryOperandNo(IT.getInstr().Description.TSFlags);
   assert(MemOpIdx >= 0 && "invalid memory operand index");
   // getMemoryOperandNo() ignores tied operands, so we have to add them back.
   for (unsigned I = 0; I <= static_cast<unsigned>(MemOpIdx); ++I) {
-    const auto &Op = IT.Instr.Operands[I];
+    const auto &Op = IT.getInstr().Operands[I];
     if (Op.isTied() && Op.getTiedToIndex() < I) {
       ++MemOpIdx;
     }
diff --git a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
--- a/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
+++ b/llvm/tools/llvm-exegesis/llvm-exegesis.cpp
@@ -208,7 +208,7 @@
 generateSnippets(const LLVMState &State, unsigned Opcode,
                  const BitVector &ForbiddenRegs) {
   const Instruction &Instr = State.getIC().getInstr(Opcode);
-  const MCInstrDesc &InstrDesc = *Instr.Description;
+  const MCInstrDesc &InstrDesc = Instr.Description;
   // Ignore instructions that we cannot run.
   if (InstrDesc.isPseudo())
     return make_error<Failure>("Unsupported opcode: isPseudo");
diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
--- a/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp
@@ -81,8 +81,8 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(3));
-  EXPECT_THAT(IT.VariableValues,
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -86,8 +86,8 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(1)); // Imm.
-  EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Immediate is not set";
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
+  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
@@ -109,9 +109,9 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(2));
-  EXPECT_THAT(IT.VariableValues[0], IsInvalid()) << "Operand 1 is not set";
-  EXPECT_THAT(IT.VariableValues[1], IsInvalid()) << "Operand 2 is not set";
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
+  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
 }
 
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
@@ -131,8 +131,8 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(3));
-  EXPECT_THAT(IT.VariableValues,
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
@@ -173,9 +173,10 @@
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
-    ASSERT_THAT(IT.VariableValues, SizeIs(2));
-    EXPECT_THAT(IT.VariableValues, AnyOf(ElementsAre(IsReg(), IsInvalid()),
-                                         ElementsAre(IsInvalid(), IsReg())));
+    ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+    EXPECT_THAT(IT.getVariableValues(),
+                AnyOf(ElementsAre(IsReg(), IsInvalid()),
+                      ElementsAre(IsInvalid(), IsReg())));
     EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
     // TODO: check that the two instructions alias each other.
   }
@@ -193,7 +194,7 @@
     ASSERT_THAT(CT.Instructions, SizeIs(2));
     const InstructionTemplate &IT = CT.Instructions[0];
     EXPECT_THAT(IT.getOpcode(), Opcode);
-    ASSERT_THAT(IT.VariableValues, SizeIs(0));
+    ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
   }
 }
 
@@ -212,9 +213,9 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(2));
-  EXPECT_THAT(IT.VariableValues[0], IsInvalid());
-  EXPECT_THAT(IT.VariableValues[1], IsInvalid());
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
+  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid());
+  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, SerialInstruction) {
@@ -233,7 +234,7 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(0));
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
 }
 
 TEST_F(UopsSnippetGeneratorTest, StaticRenaming) {
@@ -260,8 +261,8 @@
   ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
   std::unordered_set<unsigned> AllDefRegisters;
   for (const auto &IT : CT.Instructions) {
-    ASSERT_THAT(IT.VariableValues, SizeIs(3));
-    AllDefRegisters.insert(IT.VariableValues[0].getReg());
+    ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+    AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
   }
   EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
       << "Each instruction writes to a different register";
@@ -291,12 +292,14 @@
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(4));
-  EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[1].getReg()))
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
+  EXPECT_THAT(IT.getVariableValues()[0].getReg(),
+              Not(IT.getVariableValues()[1].getReg()))
       << "Def is different from first Use";
-  EXPECT_THAT(IT.VariableValues[0].getReg(), Not(IT.VariableValues[2].getReg()))
+  EXPECT_THAT(IT.getVariableValues()[0].getReg(),
+              Not(IT.getVariableValues()[2].getReg()))
       << "Def is different from second Use";
-  EXPECT_THAT(IT.VariableValues[3], IsInvalid());
+  EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
 }
 
 TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
@@ -326,11 +329,11 @@
               SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
-  ASSERT_THAT(IT.VariableValues, SizeIs(6));
-  EXPECT_EQ(IT.VariableValues[2].getImm(), 1);
-  EXPECT_EQ(IT.VariableValues[3].getReg(), 0u);
-  EXPECT_EQ(IT.VariableValues[4].getImm(), 0);
-  EXPECT_EQ(IT.VariableValues[5].getReg(), 0u);
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
+  EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
+  EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
+  EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
+  EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
 }
 
 class FakeSnippetGenerator : public SnippetGenerator {
@@ -338,7 +341,7 @@
   FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
       : SnippetGenerator(State, Opts) {}
 
-  Instruction createInstruction(unsigned Opcode) {
+  const Instruction &createInstruction(unsigned Opcode) {
     return State.getIC().getInstr(Opcode);
   }
 
@@ -390,7 +393,7 @@
   // explicit use 2       : imm
   // implicit def         : EFLAGS
   InstructionTemplate IT(Generator.createInstruction(X86::ADD16ri));
-  IT.getValueFor(IT.Instr.Variables[0]) = MCOperand::createReg(X86::AX);
+  IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
   std::vector<InstructionTemplate> Snippet;
   Snippet.push_back(std::move(IT));
   const auto RIV = Generator.computeRegisterInitialValues(Snippet);
@@ -405,14 +408,17 @@
   std::vector<InstructionTemplate> Snippet;
   {
     InstructionTemplate Mov(Generator.createInstruction(X86::MOV64ri));
-    Mov.getValueFor(Mov.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
-    Mov.getValueFor(Mov.Instr.Variables[1]) = MCOperand::createImm(42);
+    Mov.getValueFor(Mov.getInstr().Variables[0]) =
+        MCOperand::createReg(X86::RAX);
+    Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
     Snippet.push_back(std::move(Mov));
   }
   {
     InstructionTemplate Add(Generator.createInstruction(X86::ADD64rr));
-    Add.getValueFor(Add.Instr.Variables[0]) = MCOperand::createReg(X86::RAX);
-    Add.getValueFor(Add.Instr.Variables[1]) = MCOperand::createReg(X86::RBX);
+    Add.getValueFor(Add.getInstr().Variables[0]) =
+        MCOperand::createReg(X86::RAX);
+    Add.getValueFor(Add.getInstr().Variables[1]) =
+        MCOperand::createReg(X86::RBX);
     Snippet.push_back(std::move(Add));
   }
 
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
--- a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp
@@ -119,6 +119,10 @@
                                               Value);
   }
 
+  const Instruction &getInstr(unsigned OpCode) {
+    return State.getIC().getInstr(OpCode);
+  }
+
   LLVMState State;
 };
 
@@ -355,7 +359,7 @@
 }
 
 TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
-  Instruction I(State.getInstrInfo(), State.getRATC(), X86::ADD64rm);
+  const Instruction &I = getInstr(X86::ADD64rm);
   InstructionTemplate IT(I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
@@ -368,7 +372,7 @@
 }
 
 TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
-  Instruction I(State.getInstrInfo(), State.getRATC(), X86::VGATHERDPSZ128rm);
+  const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
   InstructionTemplate IT(I);
   constexpr const int kOffset = 42;
   State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);