Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -410,6 +410,7 @@ def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; +let hasSideEffects = 0 in { let Defs = [LR8] in { def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), "mtlr $rS", IIC_SprMTSPR>, @@ -421,6 +422,7 @@ PPC970_DGroup_First, PPC970_Unit_FXU; } } // Interpretation64Bit +} //===----------------------------------------------------------------------===// // Fixed point instructions. Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -2703,6 +2703,7 @@ PPC970_DGroup_First, PPC970_Unit_FXU; } +let hasSideEffects = 0 in { let Defs = [LR] in { def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), "mtlr $rS", IIC_SprMTSPR>, @@ -2713,6 +2714,7 @@ "mflr $rT", IIC_SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } +} let isCodeGenOnly = 1 in { // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed Index: llvm/test/CodeGen/PowerPC/CSR-fit.ll =================================================================== --- llvm/test/CodeGen/PowerPC/CSR-fit.ll +++ llvm/test/CodeGen/PowerPC/CSR-fit.ll @@ -27,9 +27,9 @@ ; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: ld r0, 16(r1) -; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: blr ; ; CHECK-PWR9-LABEL: caller1: @@ -51,9 +51,9 @@ ; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr entry: %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b) @@ -81,9 +81,9 @@ ; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: ld r0, 16(r1) -; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload +; CHECK-PWR8-NEXT: mtlr r0 ; CHECK-PWR8-NEXT: blr ; ; CHECK-PWR9-LABEL: caller2: @@ -105,9 +105,9 @@ ; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr entry: %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b) Index: llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll =================================================================== --- llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll +++ llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll @@ -42,8 +42,8 @@ ; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: addi 1, 1, 48 ; CHECK-NEXT: ld 0, 16(1) -; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: blr entry: %foo = getelementptr inbounds %class.CC, %class.CC* %this, i64 0, i32 0, i32 0 Index: llvm/test/CodeGen/PowerPC/csr-split.ll =================================================================== --- llvm/test/CodeGen/PowerPC/csr-split.ll +++ llvm/test/CodeGen/PowerPC/csr-split.ll @@ -34,8 +34,8 @@ ; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr ; ; CHECK-LABEL: test1: @@ -116,8 +116,8 @@ ; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr ; ; CHECK-LABEL: test2: @@ -199,9 +199,9 @@ ; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: addi r1, r1, 64 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr ; ; CHECK-LABEL: test3: Index: llvm/test/CodeGen/PowerPC/machine-pre.ll =================================================================== --- llvm/test/CodeGen/PowerPC/machine-pre.ll +++ llvm/test/CodeGen/PowerPC/machine-pre.ll @@ -134,10 +134,10 @@ ; CHECK-P9-NEXT: .LBB1_10: # %cleanup20 ; CHECK-P9-NEXT: addi r1, r1, 80 ; CHECK-P9-NEXT: ld r0, 16(r1) -; CHECK-P9-NEXT: mtlr r0 ; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; CHECK-P9-NEXT: mtlr r0 ; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: blr entry: Index: llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll =================================================================== --- llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll +++ llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll @@ -61,10 +61,10 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: addi r1, r1, 192 ; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload Index: llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll =================================================================== --- llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll +++ llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll @@ -1375,12 +1375,12 @@ ; PC64LE-NEXT: stfd 1, -16(30) ; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload -; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: test_constrained_libcall_multichain: @@ -1426,12 +1426,12 @@ ; PC64LE9-NEXT: stfd 1, -16(30) ; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 +; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr ; ; PC64-LABEL: test_constrained_libcall_multichain: Index: llvm/test/CodeGen/PowerPC/pr43527.ll =================================================================== --- llvm/test/CodeGen/PowerPC/pr43527.ll +++ llvm/test/CodeGen/PowerPC/pr43527.ll @@ -34,9 +34,9 @@ ; CHECK-NEXT: stb r3, 0(r3) ; CHECK-NEXT: addi r1, r1, 64 ; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr ; CHECK-NEXT: .LBB0_5: # %bb2 ; CHECK-NEXT: .LBB0_6: # %bb14 Index: llvm/test/CodeGen/PowerPC/pr44183.ll =================================================================== --- llvm/test/CodeGen/PowerPC/pr44183.ll +++ llvm/test/CodeGen/PowerPC/pr44183.ll @@ -31,8 +31,8 @@ ; CHECK-NEXT: nop ; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr entry: %bc = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, i64 0, i32 2 Index: llvm/test/CodeGen/PowerPC/sjlj.ll =================================================================== --- llvm/test/CodeGen/PowerPC/sjlj.ll +++ llvm/test/CodeGen/PowerPC/sjlj.ll @@ -81,8 +81,8 @@ ; CHECK: # %bb.1: ; CHECK: .LBB1_3: -; CHECK: mflr [[REGL:[0-9]+]] ; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload +; CHECK: mflr [[REGL:[0-9]+]] ; CHECK: std [[REGL]], 8([[REG2]]) ; CHECK: li 3, 0 Index: llvm/test/CodeGen/PowerPC/sms-phi-1.ll =================================================================== --- llvm/test/CodeGen/PowerPC/sms-phi-1.ll +++ llvm/test/CodeGen/PowerPC/sms-phi-1.ll @@ -36,8 +36,8 @@ ; CHECK-NEXT: stwu 4, 4(3) ; CHECK-NEXT: addi 1, 1, 48 ; CHECK-NEXT: ld 0, 16(1) -; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: blr %1 = tail call i64 @strtol() %2 = trunc i64 %1 to i32 Index: llvm/test/CodeGen/PowerPC/sms-phi-3.ll =================================================================== --- llvm/test/CodeGen/PowerPC/sms-phi-3.ll +++ llvm/test/CodeGen/PowerPC/sms-phi-3.ll @@ -54,9 +54,9 @@ ; CHECK-NEXT: stdu 3, 8(4) ; CHECK-NEXT: addi 1, 1, 64 ; CHECK-NEXT: ld 0, 16(1) -; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: blr %2 = tail call noalias i8* @malloc() %3 = bitcast i8* %2 to %0** Index: llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll =================================================================== --- llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll +++ llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll @@ -43,10 +43,10 @@ ; CHECK-NEXT: ld 2, 24(r1) ; CHECK-NEXT: addi r1, r1, 64 ; CHECK-NEXT: ld r0, 16(r1) -; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload +; CHECK-NEXT: mtlr r0 ; CHECK-NEXT: blr entry: %cmp7 = icmp sgt i32 %Len, 0 Index: llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll =================================================================== --- llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll +++ llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll @@ -293,8 +293,8 @@ ; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_frem_v2f64: @@ -322,8 +322,8 @@ ; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64( @@ -375,10 +375,10 @@ ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_frem_v3f32: @@ -421,9 +421,9 @@ ; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr entry: @@ -1542,8 +1542,8 @@ ; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_pow_v2f64: @@ -1571,8 +1571,8 @@ ; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %pow = call <2 x double> @llvm.experimental.constrained.pow.v2f64( @@ -1624,10 +1624,10 @@ ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_pow_v3f32: @@ -1670,9 +1670,9 @@ ; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr entry: @@ -2032,9 +2032,9 @@ ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_powi_v3f32: @@ -2074,9 +2074,9 @@ ; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32( @@ -2405,9 +2405,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_sin_v3f32: @@ -2444,9 +2444,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32( @@ -2758,9 +2758,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_cos_v3f32: @@ -2797,9 +2797,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32( @@ -3111,9 +3111,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_exp_v3f32: @@ -3150,9 +3150,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32( @@ -3464,9 +3464,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_exp2_v3f32: @@ -3503,9 +3503,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32( @@ -3817,9 +3817,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_log_v3f32: @@ -3856,9 +3856,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %log = call <3 x float> @llvm.experimental.constrained.log.v3f32( @@ -4170,9 +4170,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_log10_v3f32: @@ -4209,9 +4209,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32( @@ -4523,9 +4523,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_log2_v3f32: @@ -4562,9 +4562,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32( @@ -4876,9 +4876,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_rint_v3f32: @@ -4915,9 +4915,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32( @@ -5229,9 +5229,9 @@ ; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32: @@ -5268,9 +5268,9 @@ ; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: blr entry: %nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32( @@ -5600,10 +5600,10 @@ ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_maxnum_v3f32: @@ -5647,9 +5647,9 @@ ; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr entry: @@ -6009,10 +6009,10 @@ ; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: ld 0, 16(1) -; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload +; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: blr ; ; PC64LE9-LABEL: constrained_vector_minnum_v3f32: @@ -6056,9 +6056,9 @@ ; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) -; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload +; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: blr entry: