diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -24,7 +24,7 @@
 // RISC-V Target
 class RISCVTargetInfo : public TargetInfo {
 protected:
-  std::string ABI;
+  std::string ABI, CPU;
   bool HasM;
   bool HasA;
   bool HasF;
@@ -43,6 +43,11 @@
     WIntType = UnsignedInt;
   }
 
+  bool setCPU(const std::string &Name) override {
+    CPU = Name;
+    return isValidCPUName(Name);
+  }
+
   StringRef getABI() const override { return ABI; }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
@@ -94,6 +99,7 @@
     return false;
   }
 
+  bool isValidCPUName(StringRef Name) const override;
   void setMaxAtomicWidth() override {
     MaxAtomicPromoteWidth = 128;
 
@@ -118,6 +124,7 @@
     return false;
   }
 
+  bool isValidCPUName(StringRef Name) const override;
   void setMaxAtomicWidth() override {
     MaxAtomicPromoteWidth = 128;
 
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -160,3 +160,17 @@
 
   return true;
 }
+
+static constexpr llvm::StringLiteral ValidRV32CPUNames[] = {{"generic-rv32"},
+                                                            {"rocket-rv32"}};
+
+bool RISCV32TargetInfo::isValidCPUName(StringRef Name) const {
+  return llvm::find(ValidRV32CPUNames, Name) != std::end(ValidRV32CPUNames);
+}
+
+static constexpr llvm::StringLiteral ValidRV64CPUNames[] = {{"generic-rv64"},
+                                                            {"rocket-rv64"}};
+
+bool RISCV64TargetInfo::isValidCPUName(StringRef Name) const {
+  return llvm::find(ValidRV64CPUNames, Name) != std::end(ValidRV64CPUNames);
+}
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -304,6 +304,11 @@
     }
     return TargetCPUName;
   }
+  case llvm::Triple::riscv32:
+  case llvm::Triple::riscv64:
+    if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
+      return A->getValue();
+    return "";
 
   case llvm::Triple::bpfel:
   case llvm::Triple::bpfeb:
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
new file mode 100644
--- /dev/null
+++ b/clang/test/Driver/riscv-cpus.c
@@ -0,0 +1,8 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=ROCKETCHIP32 %s
+// ROCKETCHIP32: "-fuse-init-array" "-target-cpu" "rocket-rv32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=ROCKETCHIP64 %s
+// ROCKETCHIP64: "-fuse-init-array" "-target-cpu" "rocket-rv64"
+