Index: llvm/lib/Target/PowerPC/PPCInstrAltivec.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -261,6 +261,11 @@
   return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr;
 }], VSPLTISW_get_imm>;
 
+def immEQOneV : PatLeaf<(build_vector), [{
+  if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode())
+    return C->isOne();
+  return false;
+}]>;
 //===----------------------------------------------------------------------===//
 // Helpers for defining instructions that directly correspond to intrinsics.
 
@@ -1092,6 +1097,20 @@
 def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)),
           (VSEL $vC, $vB, $vA)>;
 
+// Vector Integer Average Instructions
+def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)),
+          (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>;
+def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>;
+def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>;
+def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)),
+          (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>;
+def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>;
+def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))),
+          (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>;
+
 } // end HasAltivec
 
 def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
Index: llvm/test/CodeGen/PowerPC/vavg.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vavg.ll
+++ llvm/test/CodeGen/PowerPC/vavg.ll
@@ -5,26 +5,17 @@
 define <8 x i16> @test_v8i16(<8 x i16> %m, <8 x i16> %n) {
 ; CHECK-P9-LABEL: test_v8i16:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltish 4, 1
-; CHECK-P9-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P9-NEXT:    vsrh 2, 2, 4
+; CHECK-P9-NEXT:    vavguh 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v8i16:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltish 4, 1
-; CHECK-P8-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P8-NEXT:    vsrh 2, 2, 4
+; CHECK-P8-NEXT:    vavguh 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v8i16:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltish 4, 1
-; CHECK-P7-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P7-NEXT:    vsrh 2, 2, 4
+; CHECK-P7-NEXT:    vavguh 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -36,26 +27,17 @@
 define <8 x i16> @test_v8i16_sign(<8 x i16> %m, <8 x i16> %n) {
 ; CHECK-P9-LABEL: test_v8i16_sign:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltish 4, 1
-; CHECK-P9-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P9-NEXT:    vsrah 2, 2, 4
+; CHECK-P9-NEXT:    vavgsh 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v8i16_sign:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltish 4, 1
-; CHECK-P8-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P8-NEXT:    vsrah 2, 2, 4
+; CHECK-P8-NEXT:    vavgsh 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v8i16_sign:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltish 4, 1
-; CHECK-P7-NEXT:    vsubuhm 2, 3, 2
-; CHECK-P7-NEXT:    vsrah 2, 2, 4
+; CHECK-P7-NEXT:    vavgsh 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <8 x i16> %m, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
@@ -67,26 +49,17 @@
 define <4 x i32> @test_v4i32(<4 x i32> %m, <4 x i32> %n) {
 ; CHECK-P9-LABEL: test_v4i32:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltisw 4, 1
-; CHECK-P9-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P9-NEXT:    vsrw 2, 2, 4
+; CHECK-P9-NEXT:    vavguw 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v4i32:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisw 4, 1
-; CHECK-P8-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P8-NEXT:    vsrw 2, 2, 4
+; CHECK-P8-NEXT:    vavguw 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v4i32:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisw 4, 1
-; CHECK-P7-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P7-NEXT:    vsrw 2, 2, 4
+; CHECK-P7-NEXT:    vavguw 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
@@ -98,26 +71,17 @@
 define <4 x i32> @test_v4i32_sign(<4 x i32> %m, <4 x i32> %n) {
 ; CHECK-P9-LABEL: test_v4i32_sign:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    vspltisw 4, 1
-; CHECK-P9-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P9-NEXT:    vsraw 2, 2, 4
+; CHECK-P9-NEXT:    vavgsw 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v4i32_sign:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisw 4, 1
-; CHECK-P8-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P8-NEXT:    vsraw 2, 2, 4
+; CHECK-P8-NEXT:    vavgsw 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v4i32_sign:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisw 4, 1
-; CHECK-P7-NEXT:    vsubuwm 2, 3, 2
-; CHECK-P7-NEXT:    vsraw 2, 2, 4
+; CHECK-P7-NEXT:    vavgsw 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <4 x i32> %m, <i32 1, i32 1, i32 1, i32 1>
@@ -129,26 +93,17 @@
 define <16 x i8> @test_v16i8(<16 x i8> %m, <16 x i8> %n) {
 ; CHECK-P9-LABEL: test_v16i8:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    xxspltib 36, 1
-; CHECK-P9-NEXT:    vsububm 2, 3, 2
-; CHECK-P9-NEXT:    vsrb 2, 2, 4
+; CHECK-P9-NEXT:    vavgub 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v16i8:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisb 4, 1
-; CHECK-P8-NEXT:    vsububm 2, 3, 2
-; CHECK-P8-NEXT:    vsrb 2, 2, 4
+; CHECK-P8-NEXT:    vavgub 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v16i8:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisb 4, 1
-; CHECK-P7-NEXT:    vsububm 2, 3, 2
-; CHECK-P7-NEXT:    vsrb 2, 2, 4
+; CHECK-P7-NEXT:    vavgub 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
@@ -160,26 +115,17 @@
 define <16 x i8> @test_v16i8_sign(<16 x i8> %m, <16 x i8> %n) {
 ; CHECK-P9-LABEL: test_v16i8_sign:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    xxlnor 34, 34, 34
-; CHECK-P9-NEXT:    xxspltib 36, 1
-; CHECK-P9-NEXT:    vsububm 2, 3, 2
-; CHECK-P9-NEXT:    vsrab 2, 2, 4
+; CHECK-P9-NEXT:    vavgsb 2, 3, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_v16i8_sign:
 ; CHECK-P8:       # %bb.0: # %entry
-; CHECK-P8-NEXT:    xxlnor 34, 34, 34
-; CHECK-P8-NEXT:    vspltisb 4, 1
-; CHECK-P8-NEXT:    vsububm 2, 3, 2
-; CHECK-P8-NEXT:    vsrab 2, 2, 4
+; CHECK-P8-NEXT:    vavgsb 2, 3, 2
 ; CHECK-P8-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: test_v16i8_sign:
 ; CHECK-P7:       # %bb.0: # %entry
-; CHECK-P7-NEXT:    xxlnor 34, 34, 34
-; CHECK-P7-NEXT:    vspltisb 4, 1
-; CHECK-P7-NEXT:    vsububm 2, 3, 2
-; CHECK-P7-NEXT:    vsrab 2, 2, 4
+; CHECK-P7-NEXT:    vavgsb 2, 3, 2
 ; CHECK-P7-NEXT:    blr
 entry:
   %add = add <16 x i8> %m, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>