Index: llvm/lib/Target/X86/X86MacroFusion.cpp
===================================================================
--- llvm/lib/Target/X86/X86MacroFusion.cpp
+++ llvm/lib/Target/X86/X86MacroFusion.cpp
@@ -21,17 +21,30 @@
 namespace {
 
 // The classification for the first instruction.
-enum class FirstInstrKind { Test, Cmp, And, ALU, IncDec, Invalid };
+enum class FirstInstrKind {
+  // TEST
+  Test,
+  // CMP
+  Cmp,
+  // AND
+  And,
+  // ADD, SUB
+  AddSub,
+  // INC, DEC
+  IncDec,
+  // Not valid as a first macro fusion instruction
+  Invalid
+};
 
 // The classification for the second instruction (jump).
 enum class JumpKind {
-  // JE, JL, JG and variants.
-  ELG,
   // JA, JB and variants.
   AB,
+  // JE, JL, JG and variants.
+  ELG,
   // JS, JP, JO and variants.
   SPO,
-  // Not a fusable jump.
+  // Not a fusible jump.
   Invalid,
 };
 
@@ -41,103 +54,135 @@
   switch (MI.getOpcode()) {
   default:
     return FirstInstrKind::Invalid;
-  case X86::TEST8rr:
+  // Test
+  case X86::TEST16i16:
+  case X86::TEST16ri:
   case X86::TEST16rr:
+  case X86::TEST32i32:
+  case X86::TEST32ri:
   case X86::TEST32rr:
+  case X86::TEST64i32:
+  case X86::TEST64ri32:
   case X86::TEST64rr:
+  case X86::TEST8i8:
   case X86::TEST8ri:
-  case X86::TEST16ri:
-  case X86::TEST32ri:
-  case X86::TEST64ri32:
-  case X86::TEST8mr:
-  case X86::TEST16mr:
-  case X86::TEST32mr:
-  case X86::TEST64mr:
+  case X86::TEST8rr:
     return FirstInstrKind::Test;
+    // AND
+  case X86::AND16i16:
   case X86::AND16ri:
   case X86::AND16ri8:
   case X86::AND16rm:
   case X86::AND16rr:
+  case X86::AND16rr_REV:
+  case X86::AND32i32:
   case X86::AND32ri:
   case X86::AND32ri8:
   case X86::AND32rm:
   case X86::AND32rr:
+  case X86::AND32rr_REV:
+  case X86::AND64i32:
   case X86::AND64ri32:
   case X86::AND64ri8:
   case X86::AND64rm:
   case X86::AND64rr:
+  case X86::AND64rr_REV:
+  case X86::AND8i8:
   case X86::AND8ri:
+  case X86::AND8ri8:
   case X86::AND8rm:
   case X86::AND8rr:
+  case X86::AND8rr_REV:
     return FirstInstrKind::And;
+  // CMP
+  case X86::CMP16i16:
   case X86::CMP16ri:
   case X86::CMP16ri8:
   case X86::CMP16rm:
   case X86::CMP16rr:
-  case X86::CMP16mr:
+  case X86::CMP16rr_REV:
+  case X86::CMP32i32:
   case X86::CMP32ri:
   case X86::CMP32ri8:
   case X86::CMP32rm:
   case X86::CMP32rr:
-  case X86::CMP32mr:
+  case X86::CMP32rr_REV:
+  case X86::CMP64i32:
   case X86::CMP64ri32:
   case X86::CMP64ri8:
   case X86::CMP64rm:
   case X86::CMP64rr:
-  case X86::CMP64mr:
+  case X86::CMP64rr_REV:
+  case X86::CMP8i8:
   case X86::CMP8ri:
+  case X86::CMP8ri8:
   case X86::CMP8rm:
   case X86::CMP8rr:
-  case X86::CMP8mr:
+  case X86::CMP8rr_REV:
     return FirstInstrKind::Cmp;
+    // ADD
+  case X86::ADD16i16:
   case X86::ADD16ri:
   case X86::ADD16ri8:
-  case X86::ADD16ri8_DB:
-  case X86::ADD16ri_DB:
   case X86::ADD16rm:
   case X86::ADD16rr:
-  case X86::ADD16rr_DB:
+  case X86::ADD16rr_REV:
+  case X86::ADD32i32:
   case X86::ADD32ri:
   case X86::ADD32ri8:
-  case X86::ADD32ri8_DB:
-  case X86::ADD32ri_DB:
   case X86::ADD32rm:
   case X86::ADD32rr:
-  case X86::ADD32rr_DB:
+  case X86::ADD32rr_REV:
+  case X86::ADD64i32:
   case X86::ADD64ri32:
-  case X86::ADD64ri32_DB:
   case X86::ADD64ri8:
-  case X86::ADD64ri8_DB:
   case X86::ADD64rm:
   case X86::ADD64rr:
-  case X86::ADD64rr_DB:
+  case X86::ADD64rr_REV:
+  case X86::ADD8i8:
   case X86::ADD8ri:
-  case X86::ADD8ri_DB:
+  case X86::ADD8ri8:
   case X86::ADD8rm:
   case X86::ADD8rr:
-  case X86::ADD8rr_DB:
+  case X86::ADD8rr_REV:
+  // SUB
+  case X86::SUB16i16:
   case X86::SUB16ri:
   case X86::SUB16ri8:
   case X86::SUB16rm:
   case X86::SUB16rr:
+  case X86::SUB16rr_REV:
+  case X86::SUB32i32:
   case X86::SUB32ri:
   case X86::SUB32ri8:
   case X86::SUB32rm:
   case X86::SUB32rr:
+  case X86::SUB32rr_REV:
+  case X86::SUB64i32:
   case X86::SUB64ri32:
   case X86::SUB64ri8:
   case X86::SUB64rm:
   case X86::SUB64rr:
+  case X86::SUB64rr_REV:
+  case X86::SUB8i8:
   case X86::SUB8ri:
+  case X86::SUB8ri8:
   case X86::SUB8rm:
   case X86::SUB8rr:
-    return FirstInstrKind::ALU;
+  case X86::SUB8rr_REV:
+    return FirstInstrKind::AddSub;
+  // INC
   case X86::INC16r:
+  case X86::INC16r_alt:
   case X86::INC32r:
+  case X86::INC32r_alt:
   case X86::INC64r:
   case X86::INC8r:
+  // DEC
   case X86::DEC16r:
+  case X86::DEC16r_alt:
   case X86::DEC32r:
+  case X86::DEC32r_alt:
   case X86::DEC64r:
   case X86::DEC8r:
     return FirstInstrKind::IncDec;
@@ -211,7 +256,7 @@
     case FirstInstrKind::And:
       return true;
     case FirstInstrKind::Cmp:
-    case FirstInstrKind::ALU:
+    case FirstInstrKind::AddSub:
       return BranchKind == JumpKind::ELG || BranchKind == JumpKind::AB;
     case FirstInstrKind::IncDec:
       return BranchKind == JumpKind::ELG;