diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2134,7 +2134,7 @@ return N->hasOneUse(); }]>; -let Predicates = [HasAVX512] in { +let Predicates = [HasAVX512], Uses = [MXCSR], mayRaiseFPException = 1 in { let ExeDomain = SSEPackedSingle in defm VCMPSSZ : avx512_cmp_scalar, - AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W, SIMD_EXC; defm VCMPPS : avx512_vcmp, - AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>, SIMD_EXC; // Patterns to select fp compares with load as first operand. let Predicates = [HasAVX512] in { @@ -5392,17 +5392,17 @@ XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; } defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86fadds, X86faddRnds, - SchedWriteFAddSizes, 1>; + SchedWriteFAddSizes, 1>, SIMD_EXC; defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmuls, X86fmulRnds, - SchedWriteFMulSizes, 1>; + SchedWriteFMulSizes, 1>, SIMD_EXC; defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubs, X86fsubRnds, - SchedWriteFAddSizes, 0>; + SchedWriteFAddSizes, 0>, SIMD_EXC; defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivs, X86fdivRnds, - SchedWriteFDivSizes, 0>; + SchedWriteFDivSizes, 0>, SIMD_EXC; defm VMIN : avx512_binop_s_sae<0x5D, "vmin", X86fmin, X86fmins, X86fminSAEs, - SchedWriteFCmpSizes, 0>; + SchedWriteFCmpSizes, 0>, SIMD_EXC; defm VMAX : avx512_binop_s_sae<0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxSAEs, - SchedWriteFCmpSizes, 0>; + SchedWriteFCmpSizes, 0>, SIMD_EXC; // MIN/MAX nodes are commutable under "unsafe-fp-math". In this case we use // X86fminc and X86fmaxc instead of X86fmin and X86fmax @@ -5429,21 +5429,21 @@ } defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc, SchedWriteFCmp.Scl, "VMINCSS">, XS, - EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; + EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>, SIMD_EXC; defm VMINCSDZ : avx512_comutable_binop_s<0x5D, "vminsd", f64x_info, X86fminc, SchedWriteFCmp.Scl, "VMINCSD">, XD, VEX_W, EVEX_4V, VEX_LIG, - EVEX_CD8<64, CD8VT1>; + EVEX_CD8<64, CD8VT1>, SIMD_EXC; defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc, SchedWriteFCmp.Scl, "VMAXCSS">, XS, - EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>; + EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>, SIMD_EXC; defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc, SchedWriteFCmp.Scl, "VMAXCSD">, XD, VEX_W, EVEX_4V, VEX_LIG, - EVEX_CD8<64, CD8VT1>; + EVEX_CD8<64, CD8VT1>, SIMD_EXC; multiclass avx512_fp_packed opc, string OpcodeStr, SDPatternOperator OpNode, X86VectorVTInfo _, X86FoldableSchedWrite sched, @@ -5476,7 +5476,7 @@ multiclass avx512_fp_round_packed opc, string OpcodeStr, SDPatternOperator OpNodeRnd, X86FoldableSchedWrite sched, X86VectorVTInfo _> { - let ExeDomain = _.ExeDomain in + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in defm rrb: AVX512_maskable opc, string OpcodeStr, SDPatternOperator OpNodeSAE, X86FoldableSchedWrite sched, X86VectorVTInfo _> { - let ExeDomain = _.ExeDomain in + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in defm rrb: AVX512_maskable, - avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd, SchedWriteFAddSizes>; + avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd, SchedWriteFAddSizes>, SIMD_EXC; defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512, SchedWriteFMulSizes, 1>, - avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd, SchedWriteFMulSizes>; + avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd, SchedWriteFMulSizes>, SIMD_EXC; defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub, HasAVX512, SchedWriteFAddSizes>, - avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SchedWriteFAddSizes>; + avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SchedWriteFAddSizes>, SIMD_EXC; defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv, HasAVX512, SchedWriteFDivSizes>, - avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SchedWriteFDivSizes>; + avx512_fp_binop_p_round<0x5E, "vdiv", X86fdivRnd, SchedWriteFDivSizes>, SIMD_EXC; defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, HasAVX512, SchedWriteFCmpSizes, 0>, - avx512_fp_binop_p_sae<0x5D, "vmin", X86fminSAE, SchedWriteFCmpSizes>; + avx512_fp_binop_p_sae<0x5D, "vmin", X86fminSAE, SchedWriteFCmpSizes>, SIMD_EXC; defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, HasAVX512, SchedWriteFCmpSizes, 0>, - avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxSAE, SchedWriteFCmpSizes>; + avx512_fp_binop_p_sae<0x5F, "vmax", X86fmaxSAE, SchedWriteFCmpSizes>, SIMD_EXC; let isCodeGenOnly = 1 in { defm VMINC : avx512_fp_binop_p<0x5D, "vmin", X86fminc, HasAVX512, - SchedWriteFCmpSizes, 1>; + SchedWriteFCmpSizes, 1>, SIMD_EXC; defm VMAXC : avx512_fp_binop_p<0x5F, "vmax", X86fmaxc, HasAVX512, - SchedWriteFCmpSizes, 1>; + SchedWriteFCmpSizes, 1>, SIMD_EXC; } defm VAND : avx512_fp_binop_p<0x54, "vand", null_frag, HasDQI, SchedWriteFLogicSizes, 1>; @@ -5581,7 +5581,7 @@ multiclass avx512_fp_scalef_p opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { - let ExeDomain = _.ExeDomain in { + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rr: AVX512_maskable opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { - let ExeDomain = _.ExeDomain in { + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rr: AVX512_maskable_scalar, T8PD, NotEVEX2VEXConvertible; + SchedWriteFAdd>, T8PD, NotEVEX2VEXConvertible, SIMD_EXC; //===----------------------------------------------------------------------===// // AVX-512 VPTESTM instructions @@ -6399,7 +6399,8 @@ multiclass avx512_fma3p_213_rm opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { - let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, + Uses = [MXCSR], mayRaiseFPException = 1 in { defm r: AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { - let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, + Uses = [MXCSR], mayRaiseFPException = 1 in defm rb: AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd > { +let Uses = [MXCSR], mayRaiseFPException = 1 in { defm PS : avx512_fma3p_231_common; defm PD : avx512_fma3p_231_common, VEX_W; } +} defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", X86Fmadd, X86FmaddRnd>; defm VFMSUB231 : avx512_fma3p_231_f<0xBA, "vfmsub231", X86Fmsub, X86FmsubRnd>; @@ -6548,7 +6552,8 @@ multiclass avx512_fma3p_132_rm opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { - let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, + Uses = [MXCSR], mayRaiseFPException = 1 in { defm r: AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Suff> { - let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0 in + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, hasSideEffects = 0, + Uses = [MXCSR], mayRaiseFPException = 1 in defm rb: AVX512_maskable_3src opc, string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd > { defm PS : avx512_fma3p_132_common; + SchedWriteFMA, avx512vl_f32_info, "PS">, SIMD_EXC; defm PD : avx512_fma3p_132_common, - VEX_W; + VEX_W, SIMD_EXC; } defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", X86Fmadd, X86FmaddRnd>; @@ -6701,7 +6707,7 @@ multiclass avx512_fma3s opc213, bits<8> opc231, bits<8> opc132, string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> { - let Predicates = [HasAVX512] in { + let Predicates = [HasAVX512], Uses = [MXCSR], mayRaiseFPException = 1 in { defm NAME : avx512_fma3s_all, EVEX_CD8<32, CD8VT1>, VEX_LIG; @@ -7063,18 +7069,18 @@ defm VCVTSI2SSZ : avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SS, GR32, v4f32x_info, i32mem, loadi32, "cvtsi2ss", "l">, - XS, EVEX_CD8<32, CD8VT1>; + XS, EVEX_CD8<32, CD8VT1>, SIMD_EXC; defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SS, GR64, v4f32x_info, i64mem, loadi64, "cvtsi2ss", "q">, - XS, VEX_W, EVEX_CD8<64, CD8VT1>; + XS, VEX_W, EVEX_CD8<64, CD8VT1>, SIMD_EXC; defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, null_frag, WriteCvtI2SD, GR32, v2f64x_info, i32mem, loadi32, "cvtsi2sd", "l">, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SD, GR64, v2f64x_info, i64mem, loadi64, "cvtsi2sd", "q">, - XD, VEX_W, EVEX_CD8<64, CD8VT1>; + XD, VEX_W, EVEX_CD8<64, CD8VT1>, SIMD_EXC; def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", (VCVTSI2SSZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">; @@ -7102,18 +7108,18 @@ defm VCVTUSI2SSZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SS, GR32, v4f32x_info, i32mem, loadi32, - "cvtusi2ss", "l">, XS, EVEX_CD8<32, CD8VT1>; + "cvtusi2ss", "l">, XS, EVEX_CD8<32, CD8VT1>, SIMD_EXC; defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SS, GR64, v4f32x_info, i64mem, loadi64, "cvtusi2ss", "q">, - XS, VEX_W, EVEX_CD8<64, CD8VT1>; + XS, VEX_W, EVEX_CD8<64, CD8VT1>, SIMD_EXC; defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, null_frag, WriteCvtI2SD, GR32, v2f64x_info, i32mem, loadi32, "cvtusi2sd", "l">, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SD, GR64, v2f64x_info, i64mem, loadi64, "cvtusi2sd", "q">, - XD, VEX_W, EVEX_CD8<64, CD8VT1>; + XD, VEX_W, EVEX_CD8<64, CD8VT1>, SIMD_EXC; def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", (VCVTUSI2SSZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">; @@ -7148,7 +7154,8 @@ SDNode OpNodeRnd, X86FoldableSchedWrite sched, string asm, string aliasStr> { - let Predicates = [HasAVX512], ExeDomain = SrcVT.ExeDomain in { + let Predicates = [HasAVX512], ExeDomain = SrcVT.ExeDomain, + Uses = [MXCSR], mayRaiseFPException = 1 in { def rr_Int : SI, @@ -7289,7 +7296,8 @@ X86VectorVTInfo _DstRC, SDNode OpNode, SDNode OpNodeInt, SDNode OpNodeSAE, X86FoldableSchedWrite sched, string aliasStr>{ -let Predicates = [HasAVX512], ExeDomain = _SrcRC.ExeDomain in { +let Predicates = [HasAVX512], ExeDomain = _SrcRC.ExeDomain, + Uses = [MXCSR], mayRaiseFPException = 1 in { let isCodeGenOnly = 1 in { def rr : AVX512; + f32x_info>, SIMD_EXC; defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd", X86fpexts, X86fpextsSAE, WriteCvtSS2SD, f32x_info, - f64x_info>; + f64x_info>, SIMD_EXC; def : Pat<(f64 (fpextend FR32X:$src)), (VCVTSS2SDZrr (f64 (IMPLICIT_DEF)), FR32X:$src)>, @@ -7623,9 +7631,9 @@ } defm VCVTPD2PS : avx512_cvtpd2ps<0x5A, "vcvtpd2ps", SchedWriteCvtPD2PS>, - VEX_W, PD, EVEX_CD8<64, CD8VF>; + VEX_W, PD, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTPS2PD : avx512_cvtps2pd<0x5A, "vcvtps2pd", SchedWriteCvtPS2PD>, - PS, EVEX_CD8<32, CD8VH>; + PS, EVEX_CD8<32, CD8VH>, SIMD_EXC; let Predicates = [HasAVX512] in { def : Pat<(v8f32 (fpround (v8f64 VR512:$src))), @@ -8083,23 +8091,23 @@ defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp, X86VSintToFpRnd, SchedWriteCvtDQ2PS>, - PS, EVEX_CD8<32, CD8VF>; + PS, EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", X86cvttp2si, X86cvttp2siSAE, SchedWriteCvtPS2DQ>, - XS, EVEX_CD8<32, CD8VF>; + XS, EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", X86cvttp2si, X86cvttp2siSAE, SchedWriteCvtPD2DQ>, - PD, VEX_W, EVEX_CD8<64, CD8VF>; + PD, VEX_W, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", X86cvttp2ui, X86cvttp2uiSAE, SchedWriteCvtPS2DQ>, PS, - EVEX_CD8<32, CD8VF>; + EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", X86cvttp2ui, X86cvttp2uiSAE, SchedWriteCvtPD2DQ>, - PS, VEX_W, EVEX_CD8<64, CD8VF>; + PS, VEX_W, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", uint_to_fp, X86VUintToFP, SchedWriteCvtDQ2PD>, XS, @@ -8107,71 +8115,71 @@ defm VCVTUDQ2PS : avx512_cvtdq2ps<0x7A, "vcvtudq2ps", uint_to_fp, X86VUintToFpRnd, SchedWriteCvtDQ2PS>, XD, - EVEX_CD8<32, CD8VF>; + EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VCVTPS2DQ : avx512_cvtps2dq<0x5B, "vcvtps2dq", X86cvtp2Int, X86cvtp2IntRnd, SchedWriteCvtPS2DQ>, PD, - EVEX_CD8<32, CD8VF>; + EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int, X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, XD, - VEX_W, EVEX_CD8<64, CD8VF>; + VEX_W, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt, X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, - PS, EVEX_CD8<32, CD8VF>; + PS, EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt, X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, - PS, EVEX_CD8<64, CD8VF>; + PS, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int, X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, VEX_W, - PD, EVEX_CD8<64, CD8VF>; + PD, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int, X86cvtp2IntRnd, SchedWriteCvtPS2DQ>, PD, - EVEX_CD8<32, CD8VH>; + EVEX_CD8<32, CD8VH>, SIMD_EXC; defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt, X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, - PD, EVEX_CD8<64, CD8VF>; + PD, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt, X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, PD, - EVEX_CD8<32, CD8VH>; + EVEX_CD8<32, CD8VH>, SIMD_EXC; defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", X86cvttp2si, X86cvttp2siSAE, SchedWriteCvtPD2DQ>, VEX_W, - PD, EVEX_CD8<64, CD8VF>; + PD, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", X86cvttp2si, X86cvttp2siSAE, SchedWriteCvtPS2DQ>, PD, - EVEX_CD8<32, CD8VH>; + EVEX_CD8<32, CD8VH>, SIMD_EXC; defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", X86cvttp2ui, X86cvttp2uiSAE, SchedWriteCvtPD2DQ>, VEX_W, - PD, EVEX_CD8<64, CD8VF>; + PD, EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", X86cvttp2ui, X86cvttp2uiSAE, SchedWriteCvtPS2DQ>, PD, - EVEX_CD8<32, CD8VH>; + EVEX_CD8<32, CD8VH>, SIMD_EXC; defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", sint_to_fp, X86VSintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS, - EVEX_CD8<64, CD8VF>; + EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", uint_to_fp, X86VUintToFpRnd, SchedWriteCvtDQ2PD>, VEX_W, XS, - EVEX_CD8<64, CD8VF>; + EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTQQ2PS : avx512_cvtqq2ps<0x5B, "vcvtqq2ps", sint_to_fp, X86VSintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, PS, - EVEX_CD8<64, CD8VF>; + EVEX_CD8<64, CD8VF>, SIMD_EXC; defm VCVTUQQ2PS : avx512_cvtqq2ps<0x7A, "vcvtuqq2ps", uint_to_fp, X86VUintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, XD, - EVEX_CD8<64, CD8VF>; + EVEX_CD8<64, CD8VF>, SIMD_EXC; let Predicates = [HasVLX] in { // Special patterns to allow use of X86mcvtp2Int for masking. Instruction @@ -8551,15 +8559,15 @@ defm VCVTPH2PSZ : avx512_cvtph2ps, avx512_cvtph2ps_sae, - EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>, SIMD_EXC; let Predicates = [HasVLX] in { defm VCVTPH2PSZ256 : avx512_cvtph2ps, EVEX, EVEX_V256, - EVEX_CD8<32, CD8VH>; + EVEX_CD8<32, CD8VH>, SIMD_EXC; defm VCVTPH2PSZ128 : avx512_cvtph2ps, EVEX, EVEX_V128, - EVEX_CD8<32, CD8VH>; + EVEX_CD8<32, CD8VH>, SIMD_EXC; // Pattern match vcvtph2ps of a scalar i64 load. def : Pat<(v4f32 (X86cvtph2ps (bc_v8i16 (v2i64 (X86vzload64 addr:$src))))), @@ -8620,14 +8628,14 @@ defm VCVTPS2PHZ : avx512_cvtps2ph, avx512_cvtps2ph_sae, - EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>; + EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>, SIMD_EXC; let Predicates = [HasVLX] in { defm VCVTPS2PHZ256 : avx512_cvtps2ph, - EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>; + EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>, SIMD_EXC; defm VCVTPS2PHZ128 : avx512_cvtps2ph, - EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>; + EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>, SIMD_EXC; } def : Pat<(store (f64 (extractelt @@ -8669,7 +8677,7 @@ multiclass avx512_ord_cmp_sae opc, X86VectorVTInfo _, string OpcodeStr, Domain d, X86FoldableSchedWrite sched = WriteFCom> { - let hasSideEffects = 0 in + let hasSideEffects = 0, Uses = [MXCSR], mayRaiseFPException = 1 in def rrb: AVX512, EVEX, EVEX_B, VEX_LIG, EVEX_V128, Sched<[sched]>; @@ -8839,7 +8847,7 @@ } defm VGETEXP : avx512_eri_s<0x43, "vgetexp", X86fgetexps, X86fgetexpSAEs, - SchedWriteFRnd.Scl>, T8PD, EVEX_4V; + SchedWriteFRnd.Scl>, T8PD, EVEX_4V, SIMD_EXC; /// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd multiclass avx512_fp28_p opc, string OpcodeStr, X86VectorVTInfo _, @@ -8914,7 +8922,7 @@ defm VGETEXP : avx512_eri<0x42, "vgetexp", X86fgetexp, X86fgetexpSAE, SchedWriteFRnd>, avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexp, - SchedWriteFRnd>, EVEX; + SchedWriteFRnd>, EVEX, SIMD_EXC; multiclass avx512_sqrt_packed_round opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _>{ @@ -8927,7 +8935,7 @@ multiclass avx512_sqrt_packed opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _>{ - let ExeDomain = _.ExeDomain in { + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm r: AVX512_maskable, EVEX, @@ -8983,7 +8991,7 @@ multiclass avx512_sqrt_scalar opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _, string Name> { - let ExeDomain = _.ExeDomain in { + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm r_Int : AVX512_maskable_scalar, - avx512_sqrt_packed_all_round<0x51, "vsqrt", SchedWriteFSqrtSizes>; + avx512_sqrt_packed_all_round<0x51, "vsqrt", SchedWriteFSqrtSizes>, SIMD_EXC; -defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, VEX_LIG; +defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, VEX_LIG, SIMD_EXC; multiclass avx512_rndscale_scalar opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _> { @@ -9098,12 +9106,12 @@ defm VRNDSCALESSZ : avx512_rndscale_scalar<0x0A, "vrndscaless", SchedWriteFRnd.Scl, f32x_info>, AVX512AIi8Base, EVEX_4V, VEX_LIG, - EVEX_CD8<32, CD8VT1>; + EVEX_CD8<32, CD8VT1>, SIMD_EXC; defm VRNDSCALESDZ : avx512_rndscale_scalar<0x0B, "vrndscalesd", SchedWriteFRnd.Scl, f64x_info>, VEX_W, AVX512AIi8Base, EVEX_4V, VEX_LIG, - EVEX_CD8<64, CD8VT1>; + EVEX_CD8<64, CD8VT1>, SIMD_EXC; multiclass avx512_masked_scalar opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { - let ExeDomain = _.ExeDomain in { + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rri : AVX512_maskable opc, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo _> { - let ExeDomain = _.ExeDomain in + let ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in defm rrib : AVX512_maskable { let Predicates = [prd] in { defm Z : avx512_fp_scalar_imm, - avx512_fp_sae_scalar_imm; + avx512_fp_sae_scalar_imm, SIMD_EXC; } } @@ -10344,10 +10352,10 @@ SDNode OpNodeSAE, X86SchedWriteWidths sched, Predicate prd>{ defm PS : avx512_common_unary_fp_sae_packed_imm, - EVEX_CD8<32, CD8VF>; + EVEX_CD8<32, CD8VF>, SIMD_EXC; defm PD : avx512_common_unary_fp_sae_packed_imm, - EVEX_CD8<64, CD8VF>, VEX_W; + EVEX_CD8<64, CD8VF>, VEX_W, SIMD_EXC; } defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, @@ -10363,11 +10371,11 @@ defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info, 0x50, X86VRange, X86VRangeSAE, SchedWriteFAdd, HasDQI>, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W, SIMD_EXC; defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info, 0x50, X86VRange, X86VRangeSAE, SchedWriteFAdd, HasDQI>, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; + AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>, SIMD_EXC; defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info, 0x51, X86Ranges, X86RangesSAE, SchedWriteFAdd, HasDQI>, @@ -11591,7 +11599,8 @@ multiclass avx512_fixupimm_packed opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _, X86VectorVTInfo TblVT>{ - let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { + let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, + Uses = [MXCSR], mayRaiseFPException = 1 in { defm rri : AVX512_maskable_3src : avx512_fixupimm_packed { -let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in { +let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain, + Uses = [MXCSR], mayRaiseFPException = 1 in { defm rrib : AVX512_maskable_3src { let Constraints = "$src1 = $dst" , Predicates = [HasAVX512], - ExeDomain = _.ExeDomain in { + ExeDomain = _.ExeDomain, Uses = [MXCSR], mayRaiseFPException = 1 in { defm rri : AVX512_maskable_3src_scalar