diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -800,9 +800,9 @@
     Inst = TmpInst;
     break;
   }
-  case PPC::SUBICo: {
+  case PPC::SUBICr: {
     MCInst TmpInst;
-    TmpInst.setOpcode(PPC::ADDICo);
+    TmpInst.setOpcode(PPC::ADDICr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
@@ -810,11 +810,11 @@
     break;
   }
   case PPC::EXTLWI:
-  case PPC::EXTLWIo: {
+  case PPC::EXTLWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B));
@@ -824,11 +824,11 @@
     break;
   }
   case PPC::EXTRWI:
-  case PPC::EXTRWIo: {
+  case PPC::EXTRWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B + N));
@@ -838,11 +838,11 @@
     break;
   }
   case PPC::INSLWI:
-  case PPC::INSLWIo: {
+  case PPC::INSLWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
+    TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
@@ -853,11 +853,11 @@
     break;
   }
   case PPC::INSRWI:
-  case PPC::INSRWIo: {
+  case PPC::INSRWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
+    TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
@@ -868,10 +868,10 @@
     break;
   }
   case PPC::ROTRWI:
-  case PPC::ROTRWIo: {
+  case PPC::ROTRWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(32 - N));
@@ -881,10 +881,10 @@
     break;
   }
   case PPC::SLWI:
-  case PPC::SLWIo: {
+  case PPC::SLWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
@@ -894,10 +894,10 @@
     break;
   }
   case PPC::SRWI:
-  case PPC::SRWIo: {
+  case PPC::SRWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(32 - N));
@@ -907,10 +907,10 @@
     break;
   }
   case PPC::CLRRWI:
-  case PPC::CLRRWIo: {
+  case PPC::CLRRWIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(0));
@@ -920,11 +920,11 @@
     break;
   }
   case PPC::CLRLSLWI:
-  case PPC::CLRLSLWIo: {
+  case PPC::CLRLSLWIr: {
     MCInst TmpInst;
     int64_t B = Inst.getOperand(2).getImm();
     int64_t N = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
@@ -934,11 +934,11 @@
     break;
   }
   case PPC::EXTLDI:
-  case PPC::EXTLDIo: {
+  case PPC::EXTLDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
+    TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B));
@@ -947,11 +947,11 @@
     break;
   }
   case PPC::EXTRDI:
-  case PPC::EXTRDIo: {
+  case PPC::EXTRDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
+    TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(B + N));
@@ -960,11 +960,11 @@
     break;
   }
   case PPC::INSRDI:
-  case PPC::INSRDIo: {
+  case PPC::INSRDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
     int64_t B = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
+    TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
@@ -974,10 +974,10 @@
     break;
   }
   case PPC::ROTRDI:
-  case PPC::ROTRDIo: {
+  case PPC::ROTRDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
+    TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(64 - N));
@@ -986,10 +986,10 @@
     break;
   }
   case PPC::SLDI:
-  case PPC::SLDIo: {
+  case PPC::SLDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
+    TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
@@ -1007,10 +1007,10 @@
     break;
   }
   case PPC::SRDI:
-  case PPC::SRDIo: {
+  case PPC::SRDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
+    TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(64 - N));
@@ -1019,10 +1019,10 @@
     break;
   }
   case PPC::CLRRDI:
-  case PPC::CLRRDIo: {
+  case PPC::CLRRDIr: {
     MCInst TmpInst;
     int64_t N = Inst.getOperand(2).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
+    TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(0));
@@ -1031,11 +1031,11 @@
     break;
   }
   case PPC::CLRLSLDI:
-  case PPC::CLRLSLDIo: {
+  case PPC::CLRLSLDIr: {
     MCInst TmpInst;
     int64_t B = Inst.getOperand(2).getImm();
     int64_t N = Inst.getOperand(3).getImm();
-    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
+    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(N));
@@ -1051,7 +1051,7 @@
       break;
 
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
+    TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(Inst.getOperand(2));
@@ -1068,7 +1068,7 @@
       break;
 
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
+    TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
     TmpInst.addOperand(Inst.getOperand(1));
@@ -1086,7 +1086,7 @@
       break;
 
     MCInst TmpInst;
-    TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
+    TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(Inst.getOperand(2));
@@ -1117,7 +1117,7 @@
   case PPC::CP_PASTE_LAST: {
     MCInst TmpInst;
     TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
-                      PPC::CP_PASTE : PPC::CP_PASTEo);
+                      PPC::CP_PASTE : PPC::CP_PASTEr);
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td
--- a/llvm/lib/Target/PowerPC/P9InstrResources.td
+++ b/llvm/lib/Target/PowerPC/P9InstrResources.td
@@ -107,7 +107,7 @@
     (instregex "XSMAX(C|J)?DP$"),
     (instregex "XSMIN(C|J)?DP$"),
     (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
-    (instregex "CNT(L|T)Z(D|W)(8)?(o)?$"),
+    (instregex "CNT(L|T)Z(D|W)(8)?(r)?$"),
     (instregex "POPCNT(D|W)$"),
     (instregex "CMPB(8)?$"),
     (instregex "SETB(8)?$"),
@@ -130,23 +130,23 @@
     (instregex "CMP(WI|LWI|W|LW)(8)?$"),
     (instregex "CMP(L)?D(I)?$"),
     (instregex "SUBF(I)?C(8)?(O)?$"),
-    (instregex "ANDI(S)?o(8)?$"),
+    (instregex "ANDI(S)?r(8)?$"),
     (instregex "ADDC(8)?(O)?$"),
-    (instregex "ADDIC(8)?(o)?$"),
-    (instregex "ADD(8|4)(O)?(o)?$"),
-    (instregex "ADD(E|ME|ZE)(8)?(O)?(o)?$"),
-    (instregex "SUBF(E|ME|ZE)?(8)?(O)?(o)?$"),
-    (instregex "NEG(8)?(O)?(o)?$"),
+    (instregex "ADDIC(8)?(r)?$"),
+    (instregex "ADD(8|4)(O)?(r)?$"),
+    (instregex "ADD(E|ME|ZE)(8)?(O)?(r)?$"),
+    (instregex "SUBF(E|ME|ZE)?(8)?(O)?(r)?$"),
+    (instregex "NEG(8)?(O)?(r)?$"),
     (instregex "POPCNTB$"),
     (instregex "ADD(I|IS)?(8)?$"),
     (instregex "LI(S)?(8)?$"),
-    (instregex "(X)?OR(I|IS)?(8)?(o)?$"),
-    (instregex "NAND(8)?(o)?$"),
-    (instregex "AND(C)?(8)?(o)?$"),
-    (instregex "NOR(8)?(o)?$"),
-    (instregex "OR(C)?(8)?(o)?$"),
-    (instregex "EQV(8)?(o)?$"),
-    (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(o)?$"),
+    (instregex "(X)?OR(I|IS)?(8)?(r)?$"),
+    (instregex "NAND(8)?(r)?$"),
+    (instregex "AND(C)?(8)?(r)?$"),
+    (instregex "NOR(8)?(r)?$"),
+    (instregex "OR(C)?(8)?(r)?$"),
+    (instregex "EQV(8)?(r)?$"),
+    (instregex "EXTS(B|H|W)(8)?(_32)?(_64)?(r)?$"),
     (instregex "ADD(4|8)(TLS)?(_)?$"),
     (instregex "NEG(8)?(O)?$"),
     (instregex "ADDI(S)?toc(HA|L)(8)?$"),
@@ -211,8 +211,8 @@
     (instregex "VABSDU(B|H|W)$"),
     (instregex "VADDU(B|H|W)S$"),
     (instregex "VAVG(S|U)(B|H|W)$"),
-    (instregex "VCMP(EQ|GE|GT)FP(o)?$"),
-    (instregex "VCMPBFP(o)?$"),
+    (instregex "VCMP(EQ|GE|GT)FP(r)?$"),
+    (instregex "VCMPBFP(r)?$"),
     (instregex "VC(L|T)Z(B|H|W|D)$"),
     (instregex "VADDS(B|H|W)S$"),
     (instregex "V(MIN|MAX)FP$"),
@@ -233,43 +233,43 @@
     VSUBUWS,
     VSUBCUW,
     VCMPGTSB,
-    VCMPGTSBo,
+    VCMPGTSBr,
     VCMPGTSD,
-    VCMPGTSDo,
+    VCMPGTSDr,
     VCMPGTSH,
-    VCMPGTSHo,
+    VCMPGTSHr,
     VCMPGTSW,
-    VCMPGTSWo,
+    VCMPGTSWr,
     VCMPGTUB,
-    VCMPGTUBo,
+    VCMPGTUBr,
     VCMPGTUD,
-    VCMPGTUDo,
+    VCMPGTUDr,
     VCMPGTUH,
-    VCMPGTUHo,
+    VCMPGTUHr,
     VCMPGTUW,
-    VCMPGTUWo,
-    VCMPNEBo,
-    VCMPNEHo,
-    VCMPNEWo,
-    VCMPNEZBo,
-    VCMPNEZHo,
-    VCMPNEZWo,
-    VCMPEQUBo,
-    VCMPEQUDo,
-    VCMPEQUHo,
-    VCMPEQUWo,
+    VCMPGTUWr,
+    VCMPNEBr,
+    VCMPNEHr,
+    VCMPNEWr,
+    VCMPNEZBr,
+    VCMPNEZHr,
+    VCMPNEZWr,
+    VCMPEQUBr,
+    VCMPEQUDr,
+    VCMPEQUHr,
+    VCMPEQUWr,
     XVCMPEQDP,
-    XVCMPEQDPo,
+    XVCMPEQDPr,
     XVCMPEQSP,
-    XVCMPEQSPo,
+    XVCMPEQSPr,
     XVCMPGEDP,
-    XVCMPGEDPo,
+    XVCMPGEDPr,
     XVCMPGESP,
-    XVCMPGESPo,
+    XVCMPGESPr,
     XVCMPGTDP,
-    XVCMPGTDPo,
+    XVCMPGTDPr,
     XVCMPGTSP,
-    XVCMPGTSPo,
+    XVCMPGTSPr,
     XVMAXDP,
     XVMAXSP,
     XVMINDP,
@@ -451,14 +451,14 @@
 def : InstRW<[P9_DP_7C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "FSEL(D|S)o$")
+    (instregex "FSEL(D|S)r$")
 )>;
 
 // 5 Cycle Restricted DP operation and one 2 cycle ALU operation.
 def : InstRW<[P9_DPOpAndALUOp_7C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "MUL(H|L)(D|W)(U)?(O)?o$")
+    (instregex "MUL(H|L)(D|W)(U)?(O)?r$")
 )>;
 
 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
@@ -467,18 +467,18 @@
 def : InstRW<[P9_DPOpAndALU2Op_10C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "FRI(N|P|Z|M)(D|S)o$"),
-    (instregex "FRE(S)?o$"),
-    (instregex "FADD(S)?o$"),
-    (instregex "FSUB(S)?o$"),
-    (instregex "F(N)?MSUB(S)?o$"),
-    (instregex "F(N)?MADD(S)?o$"),
-    (instregex "FCFID(U)?(S)?o$"),
-    (instregex "FCTID(U)?(Z)?o$"),
-    (instregex "FCTIW(U)?(Z)?o$"),
-    (instregex "FMUL(S)?o$"),
-    (instregex "FRSQRTE(S)?o$"),
-    FRSPo
+    (instregex "FRI(N|P|Z|M)(D|S)r$"),
+    (instregex "FRE(S)?r$"),
+    (instregex "FADD(S)?r$"),
+    (instregex "FSUB(S)?r$"),
+    (instregex "F(N)?MSUB(S)?r$"),
+    (instregex "F(N)?MADD(S)?r$"),
+    (instregex "FCFID(U)?(S)?r$"),
+    (instregex "FCTID(U)?(Z)?r$"),
+    (instregex "FCTIW(U)?(Z)?r$"),
+    (instregex "FMUL(S)?r$"),
+    (instregex "FRSQRTE(S)?r$"),
+    FRSPr
 )>;
 
 // 7 cycle DP operation. One DP unit, one EXEC pipeline and 1 dispatch units.
@@ -613,16 +613,16 @@
     XSCMPUQP,
     XSTSTDCQP,
     XSXSIGQP,
-    BCDCFNo,
-    BCDCFZo,
-    BCDCPSGNo,
-    BCDCTNo,
-    BCDCTZo,
-    BCDSETSGNo,
-    BCDSo,
-    BCDTRUNCo,
-    BCDUSo,
-    BCDUTRUNCo
+    BCDCFNr,
+    BCDCFZr,
+    BCDCPSGNr,
+    BCDCTNr,
+    BCDCTZr,
+    BCDSETSGNr,
+    BCDSr,
+    BCDTRUNCr,
+    BCDUSr,
+    BCDUTRUNCr
 )>;
 
 // 12 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
@@ -630,7 +630,7 @@
 // dispatch.
 def : InstRW<[P9_DFU_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
-    BCDSRo,
+    BCDSRr,
     XSADDQP,
     XSADDQPO,
     XSCVDPQP,
@@ -654,7 +654,7 @@
 // dispatch.
 def : InstRW<[P9_DFU_23C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
-    BCDCTSQo
+    BCDCTSQr
 )>;
 
 // 24 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
@@ -679,7 +679,7 @@
 // dispatch.
 def : InstRW<[P9_DFU_37C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C],
       (instrs
-    BCDCFSQo
+    BCDCFSQr
 )>;
 
 // 58 Cycle DFU operation. Only one DFU unit per CPU so we use a whole
@@ -819,7 +819,7 @@
               DISP_1C, DISP_1C],
       (instrs
     (instregex "LHA(X)?(8)?$"),
-    (instregex "CP_PASTE(8)?o$"),
+    (instregex "CP_PASTE(8)?r$"),
     (instregex "LWA(X)?(_32)?$"),
     TCHECK
 )>;
@@ -987,7 +987,7 @@
 def : InstRW<[P9_IntDivAndALUOp_18C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_EVEN_1C, DISP_1C],
       (instrs
-    (instregex "DIVW(U)?(O)?o$")
+    (instregex "DIVW(U)?(O)?r$")
 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
@@ -996,14 +996,14 @@
 def : InstRW<[P9_IntDivAndALUOp_26C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_EVEN_1C, DISP_1C],
       (instrs
-    DIVDo,
-    DIVDOo,
-    DIVDUo,
-    DIVDUOo,
-    DIVWEo,
-    DIVWEOo,
-    DIVWEUo,
-    DIVWEUOo
+    DIVDr,
+    DIVDOr,
+    DIVDUr,
+    DIVDUOr,
+    DIVWEr,
+    DIVWEOr,
+    DIVWEUr,
+    DIVWEUOr
 )>;
 
 // Cracked DIV and ALU operation. Requires one full slice for the ALU operation
@@ -1012,10 +1012,10 @@
 def : InstRW<[P9_IntDivAndALUOp_42C_8, IP_EXECE_1C, IP_EXECO_1C, IP_EXEC_1C,
               DISP_EVEN_1C, DISP_1C],
       (instrs
-    DIVDEo,
-    DIVDEOo,
-    DIVDEUo,
-    DIVDEUOo
+    DIVDEr,
+    DIVDEOr,
+    DIVDEUr,
+    DIVDEUOr
 )>;
 
 // CR access instructions in _BrMCR, IIC_BrMCRX.
@@ -1040,8 +1040,8 @@
 def : InstRW<[P9_ALU_2C, P9_ALU_2C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C],
       (instrs
-    (instregex "ADDC(8)?(O)?o$"),
-    (instregex "SUBFC(8)?(O)?o$")
+    (instregex "ADDC(8)?(O)?r$"),
+    (instregex "SUBFC(8)?(O)?r$")
 )>;
 
 // Cracked ALU operations.
@@ -1052,10 +1052,10 @@
 def : InstRW<[P9_ALU_2C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "F(N)?ABS(D|S)o$"),
-    (instregex "FCPSGN(D|S)o$"),
-    (instregex "FNEG(D|S)o$"),
-    FMRo
+    (instregex "F(N)?ABS(D|S)r$"),
+    (instregex "FCPSGN(D|S)r$"),
+    (instregex "FNEG(D|S)r$"),
+    FMRr
 )>;
 
 // Cracked ALU operations.
@@ -1077,8 +1077,8 @@
 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
-    (instregex "MTFSF(b|o)?$"),
-    (instregex "MTFSFI(o)?$")
+    (instregex "MTFSF(b|r)?$"),
+    (instregex "MTFSFI(r)?$")
 )>;
 
 // Cracked instruction made of two ALU ops.
@@ -1087,13 +1087,13 @@
 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    (instregex "RLD(I)?C(R|L)o$"),
-    (instregex "RLW(IMI|INM|NM)(8)?o$"),
-    (instregex "SLW(8)?o$"),
-    (instregex "SRAW(I)?o$"),
-    (instregex "SRW(8)?o$"),
-    RLDICL_32o,
-    RLDIMIo
+    (instregex "RLD(I)?C(R|L)r$"),
+    (instregex "RLW(IMI|INM|NM)(8)?r$"),
+    (instregex "SLW(8)?r$"),
+    (instregex "SRAW(I)?r$"),
+    (instregex "SRW(8)?r$"),
+    RLDICL_32r,
+    RLDIMIr
 )>;
 
 // Cracked instruction made of two ALU ops.
@@ -1102,7 +1102,7 @@
 def : InstRW<[P9_ALU2OpAndALU2Op_6C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_3SLOTS_1C],
       (instrs
-    (instregex "MFFS(L|CE|o)?$")
+    (instregex "MFFS(L|CE|r)?$")
 )>;
 
 // Cracked ALU instruction composed of three consecutive 2 cycle loads for a
@@ -1118,12 +1118,12 @@
 // The two ops cannot be done in parallel.
 def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
-    (instregex "EXTSWSLI_32_64o$"),
-    (instregex "SRAD(I)?o$"),
-    EXTSWSLIo,
-    SLDo,
-    SRDo,
-    RLDICo
+    (instregex "EXTSWSLI_32_64r$"),
+    (instregex "SRAD(I)?r$"),
+    EXTSWSLIr,
+    SLDr,
+    SRDr,
+    RLDICr
 )>;
 
 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
@@ -1136,7 +1136,7 @@
 def : InstRW<[P9_DPOpAndALU2Op_36C_8, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FDIVo
+    FDIVr
 )>;
 
 // 36 Cycle DP Instruction.
@@ -1170,7 +1170,7 @@
 def : InstRW<[P9_DPOpAndALU2Op_39C_10, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FSQRTo
+    FSQRTr
 )>;
 
 // 26 Cycle DP Instruction.
@@ -1189,7 +1189,7 @@
 def : InstRW<[P9_DPOpAndALU2Op_29C_5, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FSQRTSo
+    FSQRTSr
 )>;
 
 // 33 Cycle DP Instruction. Takes one slice and 1 dispatch.
@@ -1208,7 +1208,7 @@
 def : InstRW<[P9_DPOpAndALU2Op_25C_5, IP_EXEC_1C, IP_EXEC_1C,
               DISP_3SLOTS_1C, DISP_1C],
       (instrs
-    FDIVSo
+    FDIVSr
 )>;
 
 // 22 Cycle DP Instruction. Takes one slice and 1 dispatch.
@@ -1414,7 +1414,7 @@
   MBAR,
   MSYNC,
   SLBSYNC,
-  SLBFEEo,
+  SLBFEEr,
   NAP,
   STOP,
   TRAP,
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -1811,10 +1811,10 @@
 
       SDValue ANDIVal, ANDISVal;
       if (ANDIMask != 0)
-        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
+        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIr, dl, MVT::i32,
                             VRot, getI32Imm(ANDIMask, dl)), 0);
       if (ANDISMask != 0)
-        ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
+        ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISr, dl, MVT::i32,
                              VRot, getI32Imm(ANDISMask, dl)), 0);
 
       SDValue TotalVal;
@@ -1904,10 +1904,10 @@
 
       SDValue ANDIVal, ANDISVal;
       if (ANDIMask != 0)
-        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
+        ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIr, dl, MVT::i32,
                             Res, getI32Imm(ANDIMask, dl)), 0);
       if (ANDISMask != 0)
-        ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
+        ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISr, dl, MVT::i32,
                              Res, getI32Imm(ANDISMask, dl)), 0);
 
       if (!ANDIVal)
@@ -2181,12 +2181,12 @@
 
         SDValue ANDIVal, ANDISVal;
         if (ANDIMask != 0)
-          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
+          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIr8, dl, MVT::i64,
                                                    ExtendToInt64(VRot, dl),
                                                    getI32Imm(ANDIMask, dl)),
                             0);
         if (ANDISMask != 0)
-          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
+          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISr8, dl, MVT::i64,
                                                     ExtendToInt64(VRot, dl),
                                                     getI32Imm(ANDISMask, dl)),
                              0);
@@ -2330,10 +2330,10 @@
 
         SDValue ANDIVal, ANDISVal;
         if (ANDIMask != 0)
-          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
+          ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIr8, dl, MVT::i64,
                               ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0);
         if (ANDISMask != 0)
-          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
+          ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISr8, dl, MVT::i64,
                                ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0);
 
         if (!ANDIVal)
@@ -2623,7 +2623,7 @@
     assert((NewOpc != -1 || !IsBitwiseNegate) &&
            "No record form available for AND8/OR8/XOR8?");
     WideOp =
-      SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl,
+      SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIr8 : NewOpc, dl,
                                      MVT::i64, MVT::Glue, LHS, RHS), 0);
   }
 
@@ -4790,7 +4790,7 @@
     assert((InVT == MVT::i64 || InVT == MVT::i32) &&
            "Invalid input type for ANDIo_1_EQ_BIT");
 
-    unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
+    unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIr8 : PPC::ANDIr;
     SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
                                         N->getOperand(0),
                                         CurDAG->getTargetConstant(1, dl, InVT)),
@@ -6181,8 +6181,8 @@
   // For ANDI and ANDIS, the higher-order bits are zero if either that is true
   // of the first operand, or if the second operand is positive (so that it is
   // not sign extended).
-  if (Op32.getMachineOpcode() == PPC::ANDIo ||
-      Op32.getMachineOpcode() == PPC::ANDISo) {
+  if (Op32.getMachineOpcode() == PPC::ANDIr ||
+      Op32.getMachineOpcode() == PPC::ANDISr) {
     SmallPtrSet<SDNode *, 16> ToPromote1;
     bool Op0OK =
       PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
@@ -6304,8 +6304,8 @@
       case PPC::ORI:       NewOpcode = PPC::ORI8; break;
       case PPC::ORIS:      NewOpcode = PPC::ORIS8; break;
       case PPC::AND:       NewOpcode = PPC::AND8; break;
-      case PPC::ANDIo:     NewOpcode = PPC::ANDIo8; break;
-      case PPC::ANDISo:    NewOpcode = PPC::ANDISo8; break;
+      case PPC::ANDIr:     NewOpcode = PPC::ANDIr8; break;
+      case PPC::ANDISr:    NewOpcode = PPC::ANDISr8; break;
       }
 
       // Note: During the replacement process, the nodes will be in an
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11480,20 +11480,20 @@
 
     // Restore FPSCR value.
     BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
-  } else if (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
-             MI.getOpcode() == PPC::ANDIo_1_GT_BIT ||
-             MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
-             MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) {
-    unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
-                       MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
-                          ? PPC::ANDIo8
-                          : PPC::ANDIo;
-    bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
-                 MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
+  } else if (MI.getOpcode() == PPC::ANDIr_1_EQ_BIT ||
+             MI.getOpcode() == PPC::ANDIr_1_GT_BIT ||
+             MI.getOpcode() == PPC::ANDIr_1_EQ_BIT8 ||
+             MI.getOpcode() == PPC::ANDIr_1_GT_BIT8) {
+    unsigned Opcode = (MI.getOpcode() == PPC::ANDIr_1_EQ_BIT8 ||
+                       MI.getOpcode() == PPC::ANDIr_1_GT_BIT8)
+                          ? PPC::ANDIr8
+                          : PPC::ANDIr;
+    bool isEQ = (MI.getOpcode() == PPC::ANDIr_1_EQ_BIT ||
+                 MI.getOpcode() == PPC::ANDIr_1_EQ_BIT8);
 
     MachineRegisterInfo &RegInfo = F->getRegInfo();
     Register Dest = RegInfo.createVirtualRegister(
-        Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
+        Opcode == PPC::ANDIr ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
 
     DebugLoc dl = MI.getDebugLoc();
     BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -474,11 +474,11 @@
 
 // Logical ops with immediate.
 let Defs = [CR0] in {
-def ANDIo8  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
+def ANDIr8  : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                       "andi. $dst, $src1, $src2", IIC_IntGeneral,
                       [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
                       isDOT;
-def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
+def ANDISr8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
                      "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
                      isDOT;
@@ -1459,7 +1459,7 @@
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_L1_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;
 def CP_PASTE8  : X_L1_RA5_RB5<31, 902, "paste" , g8rc, IIC_LdStPASTE, []>;
-def CP_PASTE8o : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
+def CP_PASTE8r : X_L1_RA5_RB5<31, 902, "paste.", g8rc, IIC_LdStPASTE, []>,isDOT;
 }
 
 // SLB Invalidate Entry Global
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -789,37 +789,37 @@
 
 // f32 element comparisons.0
 def VCMPBFP   : VCMP <966, "vcmpbfp $vD, $vA, $vB"  , v4f32>;
-def VCMPBFPo  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
+def VCMPBFPr  : VCMPo<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>;
 def VCMPEQFP  : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>;
-def VCMPEQFPo : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
+def VCMPEQFPr : VCMPo<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>;
 def VCMPGEFP  : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>;
-def VCMPGEFPo : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
+def VCMPGEFPr : VCMPo<454, "vcmpgefp. $vD, $vA, $vB", v4f32>;
 def VCMPGTFP  : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>;
-def VCMPGTFPo : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
+def VCMPGTFPr : VCMPo<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>;
 
 // i8 element comparisons.
 def VCMPEQUB  : VCMP <  6, "vcmpequb $vD, $vA, $vB" , v16i8>;
-def VCMPEQUBo : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
+def VCMPEQUBr : VCMPo<  6, "vcmpequb. $vD, $vA, $vB", v16i8>;
 def VCMPGTSB  : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>;
-def VCMPGTSBo : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
+def VCMPGTSBr : VCMPo<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>;
 def VCMPGTUB  : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>;
-def VCMPGTUBo : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
+def VCMPGTUBr : VCMPo<518, "vcmpgtub. $vD, $vA, $vB", v16i8>;
 
 // i16 element comparisons.
 def VCMPEQUH  : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>;
-def VCMPEQUHo : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
+def VCMPEQUHr : VCMPo< 70, "vcmpequh. $vD, $vA, $vB", v8i16>;
 def VCMPGTSH  : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>;
-def VCMPGTSHo : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
+def VCMPGTSHr : VCMPo<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>;
 def VCMPGTUH  : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>;
-def VCMPGTUHo : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
+def VCMPGTUHr : VCMPo<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>;
 
 // i32 element comparisons.
 def VCMPEQUW  : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>;
-def VCMPEQUWo : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
+def VCMPEQUWr : VCMPo<134, "vcmpequw. $vD, $vA, $vB", v4i32>;
 def VCMPGTSW  : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>;
-def VCMPGTSWo : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
+def VCMPGTSWr : VCMPo<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>;
 def VCMPGTUW  : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
-def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
+def VCMPGTUWr : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
 
 let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
     isReMaterializable = 1 in {
@@ -1245,11 +1245,11 @@
 
 // i64 element comparisons.
 def VCMPEQUD  : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>;
-def VCMPEQUDo : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
+def VCMPEQUDr : VCMPo<199, "vcmpequd. $vD, $vA, $vB", v2i64>;
 def VCMPGTSD  : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>;
-def VCMPGTSDo : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
+def VCMPGTSDr : VCMPo<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>;
 def VCMPGTUD  : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>;
-def VCMPGTUDo : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
+def VCMPGTUDr : VCMPo<711, "vcmpgtud. $vD, $vA, $vB", v2i64>;
 
 // The cryptography instructions that do not require Category:Vector.Crypto
 def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb",
@@ -1313,21 +1313,21 @@
 
 // i8 element comparisons.
 def VCMPNEB   : VCMP   <  7, "vcmpneb $vD, $vA, $vB"  , v16i8>;
-def VCMPNEBo  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
+def VCMPNEBr  : VCMPo  <  7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
 def VCMPNEZB  : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
-def VCMPNEZBo : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
+def VCMPNEZBr : VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
 
 // i16 element comparisons.
 def VCMPNEH   : VCMP < 71, "vcmpneh $vD, $vA, $vB"  , v8i16>;
-def VCMPNEHo  : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
+def VCMPNEHr  : VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
 def VCMPNEZH  : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
-def VCMPNEZHo : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
+def VCMPNEZHr : VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
 
 // i32 element comparisons.
 def VCMPNEW   : VCMP <135, "vcmpnew $vD, $vA, $vB"  , v4i32>;
-def VCMPNEWo  : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
+def VCMPNEWr  : VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
 def VCMPNEZW  : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
-def VCMPNEZWo : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
+def VCMPNEZWr : VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
 
 // VX-Form: [PO VRT / UIM VRB XO].
 // We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
@@ -1485,7 +1485,7 @@
 // Decimal Integer Format Conversion Instructions
 
 // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set.
-class VX_VT5_EO5_VB5_PS1_XO9_o<bits<5> eo, bits<9> xo, string opc,
+class VX_VT5_EO5_VB5_PS1_XO9_r<bits<5> eo, bits<9> xo, string opc,
                                list<dag> pattern>
   : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB, u1imm:$PS),
                         !strconcat(opc, " $vD, $vB, $PS"), IIC_VecFP, pattern> {
@@ -1493,7 +1493,7 @@
 }
 
 // [PO VRT EO VRB 1 / XO]
-class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
+class VX_VT5_EO5_VB5_XO9_r<bits<5> eo, bits<9> xo, string opc,
                            list<dag> pattern>
   : VX_RD5_EO5_RS5_PS1_XO9<eo, xo, (outs vrrc:$vD), (ins vrrc:$vB),
                            !strconcat(opc, " $vD, $vB"), IIC_VecFP, pattern> {
@@ -1502,21 +1502,21 @@
 }
 
 // Decimal Convert From/to National/Zoned/Signed-QWord
-def BCDCFNo  : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." , []>;
-def BCDCFZo  : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." , []>;
-def BCDCTNo  : VX_VT5_EO5_VB5_XO9_o    <5, 385, "bcdctn." , []>;
-def BCDCTZo  : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." , []>;
-def BCDCFSQo : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
-def BCDCTSQo : VX_VT5_EO5_VB5_XO9_o    <0, 385, "bcdctsq.", []>;
+def BCDCFNr  : VX_VT5_EO5_VB5_PS1_XO9_r<7, 385, "bcdcfn." , []>;
+def BCDCFZr  : VX_VT5_EO5_VB5_PS1_XO9_r<6, 385, "bcdcfz." , []>;
+def BCDCTNr  : VX_VT5_EO5_VB5_XO9_r    <5, 385, "bcdctn." , []>;
+def BCDCTZr  : VX_VT5_EO5_VB5_PS1_XO9_r<4, 385, "bcdctz." , []>;
+def BCDCFSQr : VX_VT5_EO5_VB5_PS1_XO9_r<2, 385, "bcdcfsq.", []>;
+def BCDCTSQr : VX_VT5_EO5_VB5_XO9_r    <0, 385, "bcdctsq.", []>;
 
 // Decimal Copy-Sign/Set-Sign
 let Defs = [CR6] in
-def BCDCPSGNo : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
+def BCDCPSGNr : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>;
 
-def BCDSETSGNo : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>;
+def BCDSETSGNr : VX_VT5_EO5_VB5_PS1_XO9_r<31, 385, "bcdsetsgn.", []>;
 
 // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set.
-class VX_VT5_VA5_VB5_PS1_XO9_o<bits<9> xo, string opc, list<dag> pattern>
+class VX_VT5_VA5_VB5_PS1_XO9_r<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo,
                    (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u1imm:$PS),
                    !strconcat(opc, " $vD, $vA, $vB, $PS"), IIC_VecFP, pattern> {
@@ -1524,7 +1524,7 @@
 }
 
 // [PO VRT VRA VRB 1 / XO]
-class VX_VT5_VA5_VB5_XO9_o<bits<9> xo, string opc, list<dag> pattern>
+class VX_VT5_VA5_VB5_XO9_r<bits<9> xo, string opc, list<dag> pattern>
   : VX_RD5_RSp5_PS1_XO9<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                         !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern> {
   let Defs = [CR6];
@@ -1532,13 +1532,13 @@
 }
 
 // Decimal Shift/Unsigned-Shift/Shift-and-Round
-def BCDSo :  VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
-def BCDUSo : VX_VT5_VA5_VB5_XO9_o    <129, "bcdus.", []>;
-def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
+def BCDSr :  VX_VT5_VA5_VB5_PS1_XO9_r<193, "bcds." , []>;
+def BCDUSr : VX_VT5_VA5_VB5_XO9_r    <129, "bcdus.", []>;
+def BCDSRr : VX_VT5_VA5_VB5_PS1_XO9_r<449, "bcdsr.", []>;
 
 // Decimal (Unsigned) Truncate
-def BCDTRUNCo :  VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
-def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o    <321, "bcdutrunc.", []>;
+def BCDTRUNCr :  VX_VT5_VA5_VB5_PS1_XO9_r<257, "bcdtrunc." , []>;
+def BCDUTRUNCr : VX_VT5_VA5_VB5_XO9_r    <321, "bcdutrunc.", []>;
 
 // Absolute Difference
 def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -371,7 +371,7 @@
   MachineFunction &MF = *MI.getParent()->getParent();
 
   // Normal instructions can be commuted the obvious way.
-  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
+  if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIr)
     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
   // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
@@ -1836,8 +1836,8 @@
 
   int NewOpC = -1;
   int MIOpC = MI->getOpcode();
-  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
-      MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
+  if (MIOpC == PPC::ANDIr || MIOpC == PPC::ANDIr8 ||
+      MIOpC == PPC::ANDISr || MIOpC == PPC::ANDISr8)
     NewOpC = MIOpC;
   else {
     NewOpC = PPC::getRecordFormOpcode(MIOpC);
@@ -1944,8 +1944,8 @@
         // The mask value needs to shift right 16 if we're emitting andis.
         Mask >>= MBInLoHWord ? 0 : 16;
         NewOpC = MIOpC == PPC::RLWINM ?
-          (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
-          (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
+          (MBInLoHWord ? PPC::ANDIr : PPC::ANDISr) :
+          (MBInLoHWord ? PPC::ANDIr8 :PPC::ANDISr8);
       } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
                  (ME - MB + 1 == SH) && (MB >= 16)) {
         // If we are rotating by the exact number of bits as are in the mask
@@ -1953,7 +1953,7 @@
         // that's just an andis. (as long as the GPR result has no uses).
         Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
         Mask >>= 16;
-        NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
+        NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISr :PPC::ANDISr8;
       }
       // If we've set the mask, we can transform.
       if (Mask != ~0LLU) {
@@ -1966,7 +1966,7 @@
       int64_t MB = MI->getOperand(3).getImm();
       if (MB >= 48) {
         uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
-        NewOpC = PPC::ANDIo8;
+        NewOpC = PPC::ANDIr8;
         MI->RemoveOperand(3);
         MI->getOperand(2).setImm(Mask);
         NumRcRotatesConvertedToRcAnd++;
@@ -2306,7 +2306,7 @@
 
   // Replace the instruction.
   if (LII.SetCR) {
-    MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
+    MI.setDesc(get(LII.Is64Bit ? PPC::ANDIr8 : PPC::ANDIr));
     // Set the immediate.
     MachineInstrBuilder(*MI.getParent()->getParent(), MI)
         .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
@@ -2375,10 +2375,10 @@
       Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
       Opc == PPC::ORI || Opc == PPC::ORI8 ||
       Opc == PPC::XORI || Opc == PPC::XORI8 ||
-      Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
+      Opc == PPC::RLDICL || Opc == PPC::RLDICLr ||
       Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
-      Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
-      Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
+      Opc == PPC::RLWINM || Opc == PPC::RLWINMr ||
+      Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8r;
     bool IsVFReg = (MI.getNumOperands() && MI.getOperand(0).isReg())
                        ? isVFRegister(MI.getOperand(0).getReg())
                        : false;
@@ -2879,13 +2879,13 @@
     return false;
   }
   case PPC::RLDICL:
-  case PPC::RLDICLo:
+  case PPC::RLDICLr:
   case PPC::RLDICL_32:
   case PPC::RLDICL_32_64: {
     // Use APInt's rotate function.
     int64_t SH = MI.getOperand(2).getImm();
     int64_t MB = MI.getOperand(3).getImm();
-    APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
+    APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLr) ?
                 64 : 32, SExtImm, true);
     InVal = InVal.rotl(SH);
     uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
@@ -2894,19 +2894,19 @@
     // and not clear the left bits. If we're setting the CR bit, we will use
     // ANDIo which won't sign extend, so that's safe.
     if (isUInt<15>(InVal.getSExtValue()) ||
-        (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
+        (Opc == PPC::RLDICLr && isUInt<16>(InVal.getSExtValue()))) {
       ReplaceWithLI = true;
       Is64BitLI = Opc != PPC::RLDICL_32;
       NewImm = InVal.getSExtValue();
-      SetCR = Opc == PPC::RLDICLo;
+      SetCR = Opc == PPC::RLDICLr;
       break;
     }
     return false;
   }
   case PPC::RLWINM:
   case PPC::RLWINM8:
-  case PPC::RLWINMo:
-  case PPC::RLWINM8o: {
+  case PPC::RLWINMr:
+  case PPC::RLWINM8r: {
     int64_t SH = MI.getOperand(2).getImm();
     int64_t MB = MI.getOperand(3).getImm();
     int64_t ME = MI.getOperand(4).getImm();
@@ -2919,13 +2919,13 @@
     // and not clear the left bits. If we're setting the CR bit, we will use
     // ANDIo which won't sign extend, so that's safe.
     bool ValueFits = isUInt<15>(InVal.getSExtValue());
-    ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
+    ValueFits |= ((Opc == PPC::RLWINMr || Opc == PPC::RLWINM8r) &&
                   isUInt<16>(InVal.getSExtValue()));
     if (ValueFits) {
       ReplaceWithLI = true;
-      Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
+      Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8r;
       NewImm = InVal.getSExtValue();
-      SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
+      SetCR = Opc == PPC::RLWINMr || Opc == PPC::RLWINM8r;
       break;
     }
     return false;
@@ -3038,13 +3038,13 @@
     III.IsSummingOperands = true;
     III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
     break;
-  case PPC::ADDCo:
+  case PPC::ADDCr:
     III.SignedImm = true;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
     III.IsCommutative = true;
     III.IsSummingOperands = true;
-    III.ImmOpcode = PPC::ADDICo;
+    III.ImmOpcode = PPC::ADDICr;
     break;
   case PPC::SUBFC:
   case PPC::SUBFC8:
@@ -3070,8 +3070,8 @@
     III.IsCommutative = false;
     III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
     break;
-  case PPC::ANDo:
-  case PPC::AND8o:
+  case PPC::ANDr:
+  case PPC::AND8r:
   case PPC::OR:
   case PPC::OR8:
   case PPC::XOR:
@@ -3082,8 +3082,8 @@
     III.IsCommutative = true;
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode");
-    case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
-    case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
+    case PPC::ANDr: III.ImmOpcode = PPC::ANDIr; break;
+    case PPC::AND8r: III.ImmOpcode = PPC::ANDIr8; break;
     case PPC::OR: III.ImmOpcode = PPC::ORI; break;
     case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
     case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
@@ -3092,18 +3092,18 @@
     break;
   case PPC::RLWNM:
   case PPC::RLWNM8:
-  case PPC::RLWNMo:
-  case PPC::RLWNM8o:
+  case PPC::RLWNMr:
+  case PPC::RLWNM8r:
   case PPC::SLW:
   case PPC::SLW8:
-  case PPC::SLWo:
-  case PPC::SLW8o:
+  case PPC::SLWr:
+  case PPC::SLW8r:
   case PPC::SRW:
   case PPC::SRW8:
-  case PPC::SRWo:
-  case PPC::SRW8o:
+  case PPC::SRWr:
+  case PPC::SRW8r:
   case PPC::SRAW:
-  case PPC::SRAWo:
+  case PPC::SRAWr:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
@@ -3114,7 +3114,7 @@
     // out of range will produce a -1/0.
     III.ImmWidth = 16;
     if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
-        Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
+        Opc == PPC::RLWNMr || Opc == PPC::RLWNM8r)
       III.TruncateImmTo = 5;
     else
       III.TruncateImmTo = 6;
@@ -3122,38 +3122,38 @@
     default: llvm_unreachable("Unknown opcode");
     case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
     case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
-    case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
-    case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
+    case PPC::RLWNMr: III.ImmOpcode = PPC::RLWINMr; break;
+    case PPC::RLWNM8r: III.ImmOpcode = PPC::RLWINM8r; break;
     case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
     case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
-    case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
-    case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
+    case PPC::SLWr: III.ImmOpcode = PPC::RLWINMr; break;
+    case PPC::SLW8r: III.ImmOpcode = PPC::RLWINM8r; break;
     case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
     case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
-    case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
-    case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
+    case PPC::SRWr: III.ImmOpcode = PPC::RLWINMr; break;
+    case PPC::SRW8r: III.ImmOpcode = PPC::RLWINM8r; break;
     case PPC::SRAW:
       III.ImmWidth = 5;
       III.TruncateImmTo = 0;
       III.ImmOpcode = PPC::SRAWI;
       break;
-    case PPC::SRAWo:
+    case PPC::SRAWr:
       III.ImmWidth = 5;
       III.TruncateImmTo = 0;
-      III.ImmOpcode = PPC::SRAWIo;
+      III.ImmOpcode = PPC::SRAWIr;
       break;
     }
     break;
   case PPC::RLDCL:
-  case PPC::RLDCLo:
+  case PPC::RLDCLr:
   case PPC::RLDCR:
-  case PPC::RLDCRo:
+  case PPC::RLDCRr:
   case PPC::SLD:
-  case PPC::SLDo:
+  case PPC::SLDr:
   case PPC::SRD:
-  case PPC::SRDo:
+  case PPC::SRDr:
   case PPC::SRAD:
-  case PPC::SRADo:
+  case PPC::SRADr:
     III.SignedImm = false;
     III.ZeroIsSpecialOrig = 0;
     III.ZeroIsSpecialNew = 0;
@@ -3163,30 +3163,30 @@
     // This does not apply to shift right algebraic because a value
     // out of range will produce a -1/0.
     III.ImmWidth = 16;
-    if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
-        Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
+    if (Opc == PPC::RLDCL || Opc == PPC::RLDCLr ||
+        Opc == PPC::RLDCR || Opc == PPC::RLDCRr)
       III.TruncateImmTo = 6;
     else
       III.TruncateImmTo = 7;
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode");
     case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
-    case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
+    case PPC::RLDCLr: III.ImmOpcode = PPC::RLDICLr; break;
     case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
-    case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
+    case PPC::RLDCRr: III.ImmOpcode = PPC::RLDICRr; break;
     case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
-    case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
+    case PPC::SLDr: III.ImmOpcode = PPC::RLDICRr; break;
     case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
-    case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
+    case PPC::SRDr: III.ImmOpcode = PPC::RLDICLr; break;
     case PPC::SRAD:
       III.ImmWidth = 6;
       III.TruncateImmTo = 0;
       III.ImmOpcode = PPC::SRADI;
        break;
-    case PPC::SRADo:
+    case PPC::SRADr:
       III.ImmWidth = 6;
       III.TruncateImmTo = 0;
-      III.ImmOpcode = PPC::SRADIo;
+      III.ImmOpcode = PPC::SRADIr;
       break;
     }
     break;
@@ -3758,13 +3758,13 @@
 
   unsigned Opc = MI.getOpcode();
   bool SpecialShift32 =
-    Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
+    Opc == PPC::SLW || Opc == PPC::SLWr || Opc == PPC::SRW || Opc == PPC::SRWr;
   bool SpecialShift64 =
-    Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
-  bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
-    Opc == PPC::SLDo || Opc == PPC::SRDo;
+    Opc == PPC::SLD || Opc == PPC::SLDr || Opc == PPC::SRD || Opc == PPC::SRDr;
+  bool SetCR = Opc == PPC::SLWr || Opc == PPC::SRWr ||
+    Opc == PPC::SLDr || Opc == PPC::SRDr;
   bool RightShift =
-    Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
+    Opc == PPC::SRW || Opc == PPC::SRWr || Opc == PPC::SRD || Opc == PPC::SRDr;
 
   MI.setDesc(get(III.ImmOpcode));
   if (ConstantOpNo == III.OpNoForForwarding) {
@@ -3870,8 +3870,8 @@
   int Opcode = MI.getOpcode();
   if (Opcode == PPC::LI     || Opcode == PPC::LI8     ||
       Opcode == PPC::LIS    || Opcode == PPC::LIS8    ||
-      Opcode == PPC::SRAW   || Opcode == PPC::SRAWo   ||
-      Opcode == PPC::SRAWI  || Opcode == PPC::SRAWIo  ||
+      Opcode == PPC::SRAW   || Opcode == PPC::SRAWr   ||
+      Opcode == PPC::SRAWI  || Opcode == PPC::SRAWIr  ||
       Opcode == PPC::LWA    || Opcode == PPC::LWAX    ||
       Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
       Opcode == PPC::LHA    || Opcode == PPC::LHAX    ||
@@ -3884,10 +3884,10 @@
       Opcode == PPC::LHZ8   || Opcode == PPC::LHZX8   ||
       Opcode == PPC::LHZU   || Opcode == PPC::LHZUX   ||
       Opcode == PPC::LHZU8  || Opcode == PPC::LHZUX8  ||
-      Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBo  ||
-      Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHo  ||
+      Opcode == PPC::EXTSB  || Opcode == PPC::EXTSBr  ||
+      Opcode == PPC::EXTSH  || Opcode == PPC::EXTSHr  ||
       Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8  ||
-      Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWo  ||
+      Opcode == PPC::EXTSW  || Opcode == PPC::EXTSWr  ||
       Opcode == PPC::SETB   || Opcode == PPC::SETB8   ||
       Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
       Opcode == PPC::EXTSB8_32_64)
@@ -3896,8 +3896,8 @@
   if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
     return true;
 
-  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
-       Opcode == PPC::RLWNM  || Opcode == PPC::RLWNMo) &&
+  if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMr ||
+       Opcode == PPC::RLWNM  || Opcode == PPC::RLWNMr) &&
       MI.getOperand(3).getImm() > 0 &&
       MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
     return true;
@@ -3920,35 +3920,35 @@
 
   // We have some variations of rotate-and-mask instructions
   // that clear higher 32-bits.
-  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
-       Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo  ||
+  if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLr ||
+       Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLr  ||
        Opcode == PPC::RLDICL_32_64) &&
       MI.getOperand(3).getImm() >= 32)
     return true;
 
-  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
+  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICr) &&
       MI.getOperand(3).getImm() >= 32 &&
       MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
     return true;
 
-  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
-       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMr ||
+       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMr  ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
       MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
     return true;
 
   // There are other instructions that clear higher 32-bits.
-  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
-      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWr ||
+      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWr ||
       Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
-      Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
-      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo ||
+      Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDr ||
+      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDr ||
       Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
-      Opcode == PPC::SLW     || Opcode == PPC::SLWo    ||
-      Opcode == PPC::SRW     || Opcode == PPC::SRWo    ||
+      Opcode == PPC::SLW     || Opcode == PPC::SLWr    ||
+      Opcode == PPC::SRW     || Opcode == PPC::SRWr    ||
       Opcode == PPC::SLW8    || Opcode == PPC::SRW8    ||
-      Opcode == PPC::SLWI    || Opcode == PPC::SLWIo   ||
-      Opcode == PPC::SRWI    || Opcode == PPC::SRWIo   ||
+      Opcode == PPC::SLWI    || Opcode == PPC::SLWIr   ||
+      Opcode == PPC::SRWI    || Opcode == PPC::SRWIr   ||
       Opcode == PPC::LWZ     || Opcode == PPC::LWZX    ||
       Opcode == PPC::LWZU    || Opcode == PPC::LWZUX   ||
       Opcode == PPC::LWBRX   || Opcode == PPC::LHBRX   ||
@@ -3963,9 +3963,9 @@
       Opcode == PPC::LHZU8   || Opcode == PPC::LHZUX8  ||
       Opcode == PPC::LBZ8    || Opcode == PPC::LBZX8   ||
       Opcode == PPC::LBZU8   || Opcode == PPC::LBZUX8  ||
-      Opcode == PPC::ANDIo   || Opcode == PPC::ANDISo  ||
-      Opcode == PPC::ROTRWI  || Opcode == PPC::ROTRWIo ||
-      Opcode == PPC::EXTLWI  || Opcode == PPC::EXTLWIo ||
+      Opcode == PPC::ANDIr   || Opcode == PPC::ANDISr  ||
+      Opcode == PPC::ROTRWI  || Opcode == PPC::ROTRWIr ||
+      Opcode == PPC::EXTLWI  || Opcode == PPC::EXTLWIr ||
       Opcode == PPC::MFVSRWZ)
     return true;
 
@@ -4059,14 +4059,14 @@
     return false;
   }
 
-  case PPC::ANDIo:
-  case PPC::ANDISo:
+  case PPC::ANDIr:
+  case PPC::ANDISr:
   case PPC::ORI:
   case PPC::ORIS:
   case PPC::XORI:
   case PPC::XORIS:
-  case PPC::ANDIo8:
-  case PPC::ANDISo8:
+  case PPC::ANDIr8:
+  case PPC::ANDISr8:
   case PPC::ORI8:
   case PPC::ORIS8:
   case PPC::XORI8:
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -966,7 +966,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XForm_6<opcode, xo, OOL, IOL,
+    def r    : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -981,7 +981,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XForm_6<opcode, xo, OOL, IOL,
+    def r    : XForm_6<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -996,7 +996,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XForm_10<opcode, xo, OOL, IOL,
+    def r    : XForm_10<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1010,7 +1010,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XForm_11<opcode, xo, OOL, IOL,
+    def r    : XForm_11<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1024,7 +1024,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+    def r    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1040,7 +1040,7 @@
                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                         pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_1<opcode, xo, 0, OOL, IOL,
+    def r    : XOForm_1<opcode, xo, 0, OOL, IOL,
                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                         []>, isDOT, RecFormRel;
   }
@@ -1050,7 +1050,7 @@
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [XER, CR0] in
-    def Oo    : XOForm_1<opcode, xo, 1, OOL, IOL,
+    def Or    : XOForm_1<opcode, xo, 1, OOL, IOL,
                          !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
                          []>, isDOT, RecFormRel;
   }
@@ -1066,7 +1066,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+    def r    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel, PPC970_DGroup_First,
                        PPC970_DGroup_Cracked;
@@ -1077,7 +1077,7 @@
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [XER, CR0] in
-    def Oo   : XOForm_1<opcode, xo, 1, OOL, IOL,
+    def Or   : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
                         []>, isDOT, RecFormRel;
   }
@@ -1092,7 +1092,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+    def r    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1102,7 +1102,7 @@
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [CARRY, XER, CR0] in
-    def Oo   : XOForm_1<opcode, xo, 1, OOL, IOL,
+    def Or   : XOForm_1<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
                         []>, isDOT, RecFormRel;
   }
@@ -1116,7 +1116,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
+    def r    : XOForm_3<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1126,7 +1126,7 @@
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [XER, CR0] in
-    def Oo   : XOForm_3<opcode, xo, 1, OOL, IOL,
+    def Or   : XOForm_3<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
                         []>, isDOT, RecFormRel;
   }
@@ -1141,7 +1141,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XOForm_3<opcode, xo, oe, OOL, IOL,
+    def r    : XOForm_3<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1151,7 +1151,7 @@
                         !strconcat(asmbase, !strconcat("o ", asmstr)), itin,
                         []>, RecFormRel;
     let Defs = [CARRY, XER, CR0] in
-    def Oo   : XOForm_3<opcode, xo, 1, OOL, IOL,
+    def Or   : XOForm_3<opcode, xo, 1, OOL, IOL,
                         !strconcat(asmbase, !strconcat("o. ", asmstr)), itin,
                         []>, isDOT, RecFormRel;
   }
@@ -1165,7 +1165,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : MForm_2<opcode, OOL, IOL,
+    def r    : MForm_2<opcode, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1179,7 +1179,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : MDForm_1<opcode, xo, OOL, IOL,
+    def r    : MDForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1193,7 +1193,7 @@
                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                         pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : MDSForm_1<opcode, xo, OOL, IOL,
+    def r    : MDSForm_1<opcode, xo, OOL, IOL,
                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                         []>, isDOT, RecFormRel;
   }
@@ -1208,7 +1208,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CARRY, CR0] in
-    def o    : XSForm_1<opcode, xo, OOL, IOL,
+    def r    : XSForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1222,7 +1222,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
-    def o    : XSForm_1<opcode, xo, OOL, IOL,
+    def r    : XSForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1236,7 +1236,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : XForm_26<opcode, xo, OOL, IOL,
+    def r    : XForm_26<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1250,7 +1250,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : XForm_28<opcode, xo, OOL, IOL,
+    def r    : XForm_28<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1264,7 +1264,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : AForm_1<opcode, xo, OOL, IOL,
+    def r    : AForm_1<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1278,7 +1278,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : AForm_2<opcode, xo, OOL, IOL,
+    def r    : AForm_2<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -1292,7 +1292,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
     let Defs = [CR1] in
-    def o    : AForm_3<opcode, xo, OOL, IOL,
+    def r    : AForm_3<opcode, xo, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
@@ -2294,7 +2294,7 @@
                      [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>,
                      RecFormRel, PPC970_DGroup_Cracked;
 let Defs = [CARRY, CR0] in
-def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
+def ADDICr : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
                      "addic. $rD, $rA, $imm", IIC_IntGeneral,
                      []>, isDOT, RecFormRel;
 }
@@ -2326,11 +2326,11 @@
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
-def ANDIo : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
+def ANDIr : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andi. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>,
                     isDOT;
-def ANDISo : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
+def ANDISr : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
                     "andis. $dst, $src1, $src2", IIC_IntGeneral,
                     [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>,
                     isDOT;
@@ -2805,7 +2805,7 @@
                PPC970_DGroup_Single, PPC970_Unit_FPU;
 
   let Defs = [CR1] in
-  def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
+  def MFFSr : XForm_42<63, 583, (outs f8rc:$rT), (ins),
                       "mffs. $rT", IIC_IntMFFS, []>, isDOT;
 
   def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
@@ -3047,7 +3047,7 @@
                      "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
                      []>, RecFormRel;
 let Defs = [CR0] in
-def RLWINMo : MForm_2<21,
+def RLWINMr : MForm_2<21,
                       (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
                       "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
                       []>, isDOT, RecFormRel, PPC970_DGroup_Cracked;
@@ -4078,24 +4078,24 @@
 def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)),
           (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>;
 
-def ANDIo_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
-                             "#ANDIo_1_EQ_BIT",
+def ANDIr_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
+                             "#ANDIr_1_EQ_BIT",
                              [(set i1:$dst, (trunc (not i32:$in)))]>;
-def ANDIo_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
-                             "#ANDIo_1_GT_BIT",
+def ANDIr_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in),
+                             "#ANDIr_1_GT_BIT",
                              [(set i1:$dst, (trunc i32:$in))]>;
 
-def ANDIo_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
-                              "#ANDIo_1_EQ_BIT8",
+def ANDIr_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
+                              "#ANDIr_1_EQ_BIT8",
                               [(set i1:$dst, (trunc (not i64:$in)))]>;
-def ANDIo_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
-                              "#ANDIo_1_GT_BIT8",
+def ANDIr_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in),
+                              "#ANDIr_1_GT_BIT8",
                               [(set i1:$dst, (trunc i64:$in))]>;
 
 def : Pat<(i1 (not (trunc i32:$in))),
-           (ANDIo_1_EQ_BIT $in)>;
+           (ANDIr_1_EQ_BIT $in)>;
 def : Pat<(i1 (not (trunc i64:$in))),
-           (ANDIo_1_EQ_BIT8 $in)>;
+           (ANDIr_1_EQ_BIT8 $in)>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Instructions used for assembler/disassembler only
@@ -4179,22 +4179,22 @@
 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                       "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
 
-def MTFSFIo : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
+def MTFSFIr : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                        "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isDOT;
 
 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
-def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIo crrc:$BF, i32imm:$U, 0)>;
+def : InstAlias<"mtfsfi. $BF, $U", (MTFSFIr crrc:$BF, i32imm:$U, 0)>;
 
 let Predicates = [HasFPU] in {
 def MTFSF : XFLForm_1<63, 711, (outs),
                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
                       "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
-def MTFSFo : XFLForm_1<63, 711, (outs),
+def MTFSFr : XFLForm_1<63, 711, (outs),
                        (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
                        "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isDOT;
 
 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
-def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFo i32imm:$FLM, f8rc:$FRB, 0, 0)>;
+def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSFr i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 }
 
 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),
@@ -4212,7 +4212,7 @@
 def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>;
 
 let Defs = [CR0] in
-def SLBFEEo : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB),
+def SLBFEEr : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB),
                          "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isDOT;
 
 def TLBIA : XForm_0<31, 370, (outs), (ins),
@@ -4474,10 +4474,10 @@
 def : InstAlias<"xnop", (XORI R0, R0, 0)>;
 
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
-def : InstAlias<"mr. $rA, $rB", (OR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR8r g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"not $rA, $rB", (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
-def : InstAlias<"not. $rA, $rB", (NOR8o g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
+def : InstAlias<"not. $rA, $rB", (NOR8r g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
 def : InstAlias<"mtcr $rA", (MTCRF8 255, g8rc:$rA)>;
 
@@ -4543,13 +4543,13 @@
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm",
                          (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
-def SUBICo : PPCAsmPseudo<"subic. $rA, $rB, $imm",
+def SUBICr : PPCAsmPseudo<"subic. $rA, $rB, $imm",
                           (ins gprc:$rA, gprc:$rB, s16imm:$imm)>;
 
 def : InstAlias<"sub $rA, $rB, $rC", (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
-def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
+def : InstAlias<"sub. $rA, $rB, $rC", (SUBF8r g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 def : InstAlias<"subc $rA, $rB, $rC", (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
-def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8o g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
+def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC8r g8rc:$rA, g8rc:$rC, g8rc:$rB)>;
 
 def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>;
 def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>;
@@ -4602,96 +4602,96 @@
 
 def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def EXTLWIo : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
+def EXTLWIr : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def EXTRWIo : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
+def EXTRWIr : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def INSLWIo : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
+def INSLWIr : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
-def INSRWIo : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
+def INSRWIr : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>;
 def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def ROTRWIo : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
+def ROTRWIr : PPCAsmPseudo<"rotrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n",
                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def SLWIo : PPCAsmPseudo<"slwi. $rA, $rS, $n",
+def SLWIr : PPCAsmPseudo<"slwi. $rA, $rS, $n",
                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n",
                         (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def SRWIo : PPCAsmPseudo<"srwi. $rA, $rS, $n",
+def SRWIr : PPCAsmPseudo<"srwi. $rA, $rS, $n",
                          (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n",
                           (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
-def CLRRWIo : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
+def CLRRWIr : PPCAsmPseudo<"clrrwi. $rA, $rS, $n",
                            (ins gprc:$rA, gprc:$rS, u5imm:$n)>;
 def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
                             (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
-def CLRLSLWIo : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
+def CLRLSLWIr : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
-def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINMr gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
-def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMo gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
+def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNMr gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
 def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
-def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMo gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
+def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINMr gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>;
 
 def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>;
-def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWo gprc:$rA, gprc:$rS)>;
+def : InstAlias<"cntlzw. $rA, $rS", (CNTLZWr gprc:$rA, gprc:$rS)>;
 // The POWER variant
 def : MnemonicAlias<"cntlz",  "cntlzw">;
 def : MnemonicAlias<"cntlz.", "cntlzw.">;
 
 def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
-def EXTLDIo : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
+def EXTLDIr : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
 def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
-def EXTRDIo : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
+def EXTRDIr : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
 def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
-def INSRDIo : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
+def INSRDIr : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>;
 def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def ROTRDIo : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
+def ROTRDIr : PPCAsmPseudo<"rotrdi. $rA, $rS, $n",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n",
                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def SLDIo : PPCAsmPseudo<"sldi. $rA, $rS, $n",
+def SLDIr : PPCAsmPseudo<"sldi. $rA, $rS, $n",
                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n",
                         (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def SRDIo : PPCAsmPseudo<"srdi. $rA, $rS, $n",
+def SRDIr : PPCAsmPseudo<"srdi. $rA, $rS, $n",
                          (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n",
                           (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
-def CLRRDIo : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
+def CLRRDIr : PPCAsmPseudo<"clrrdi. $rA, $rS, $n",
                            (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>;
 def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n",
                             (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
-def CLRLSLDIo : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
+def CLRLSLDIr : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
                              (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>;
 def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
 
 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
-def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
+def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICLr g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
-def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLo g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
+def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCLr g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"clrldi $rA, $rS, $n",
                 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>;
-def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLo g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
+def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICLr g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>;
 def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>;
 
 def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b",
@@ -4933,7 +4933,7 @@
 def CP_PASTE  : X_L1_RA5_RB5<31, 902, "paste" , gprc, IIC_LdStPASTE, []>;
 
 let mayStore = 1, Defs = [CR0] in
-def CP_PASTEo : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
+def CP_PASTEr : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isDOT;
 
 def CP_COPYx  : PPCAsmPseudo<"copy $rA, $rB" , (ins gprc:$rA, gprc:$rB)>;
 def CP_PASTEx : PPCAsmPseudo<"paste $rA, $rB", (ins gprc:$rA, gprc:$rB)>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -120,7 +120,7 @@
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        [(set OutTy:$XT, (Int InTy:$XA, InTy:$XB))]>;
     let Defs = [CR6] in
-    def o    : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+    def r    : XX3Form_Rc<opcode, xo, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        [(set InTy:$XT,
                                 (InTy (PPCvcmp_o InTy:$XA, InTy:$XB, xo)))]>,
@@ -1961,7 +1961,7 @@
       - The order of elements after the move to GPR is reversed, so we invert
         the bits of the index prior to truncating to the range 0-7
   */
-  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDIo8 $Idx, 8)));
+  dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDIr8 $Idx, 8)));
   dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC));
   dag BE_MV_VBYTE = (MFVSRD
                       (EXTRACT_SUBREG
@@ -1980,7 +1980,7 @@
         the bits of the index prior to truncating to the range 0-3
   */
   dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                       (RLDICR (ANDIo8 $Idx, 4), 1, 62)));
+                                       (RLDICR (ANDIr8 $Idx, 4), 1, 62)));
   dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC));
   dag BE_MV_VHALF = (MFVSRD
                       (EXTRACT_SUBREG
@@ -1998,7 +1998,7 @@
         the bits of the index prior to truncating to the range 0-1
   */
   dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                       (RLDICR (ANDIo8 $Idx, 2), 2, 61)));
+                                       (RLDICR (ANDIr8 $Idx, 2), 2, 61)));
   dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC));
   dag BE_MV_VWORD = (MFVSRD
                       (EXTRACT_SUBREG
@@ -2014,7 +2014,7 @@
       element indices.
   */
   dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8,
-                                        (RLDICR (ANDIo8 $Idx, 1), 3, 60)));
+                                        (RLDICR (ANDIr8 $Idx, 1), 3, 60)));
   dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC));
   dag BE_VARIABLE_DWORD =
         (MFVSRD (EXTRACT_SUBREG
diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -161,33 +161,33 @@
 static unsigned
 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) {
   unsigned Opcode = MI->getOpcode();
-  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
-      Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLo)
+  if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLr ||
+      Opcode == PPC::RLDCL  || Opcode == PPC::RLDCLr)
     return MI->getOperand(3).getImm();
 
-  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
+  if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICr) &&
        MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm())
     return MI->getOperand(3).getImm();
 
-  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMo ||
-       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMo  ||
+  if ((Opcode == PPC::RLWINM  || Opcode == PPC::RLWINMr ||
+       Opcode == PPC::RLWNM   || Opcode == PPC::RLWNMr  ||
        Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
        MI->getOperand(3).getImm() <= MI->getOperand(4).getImm())
     return 32 + MI->getOperand(3).getImm();
 
-  if (Opcode == PPC::ANDIo) {
+  if (Opcode == PPC::ANDIr) {
     uint16_t Imm = MI->getOperand(2).getImm();
     return 48 + countLeadingZeros(Imm);
   }
 
-  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWo ||
-      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWo ||
+  if (Opcode == PPC::CNTLZW  || Opcode == PPC::CNTLZWr ||
+      Opcode == PPC::CNTTZW  || Opcode == PPC::CNTTZWr ||
       Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8)
     // The result ranges from 0 to 32.
     return 58;
 
-  if (Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDo ||
-      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDo)
+  if (Opcode == PPC::CNTLZD  || Opcode == PPC::CNTLZDr ||
+      Opcode == PPC::CNTTZD  || Opcode == PPC::CNTTZDr)
     // The result ranges from 0 to 64.
     return 57;
 
diff --git a/llvm/test/CodeGen/PowerPC/block-placement.mir b/llvm/test/CodeGen/PowerPC/block-placement.mir
--- a/llvm/test/CodeGen/PowerPC/block-placement.mir
+++ b/llvm/test/CodeGen/PowerPC/block-placement.mir
@@ -149,7 +149,7 @@
     successors: %bb.4(0x04000000), %bb.10(0x7c000000)
     liveins: $r8, $x3, $x4, $x5, $x6, $x7
   
-    dead renamable $r8 = ANDIo killed renamable $r8, 65535, implicit-def $cr0
+    dead renamable $r8 = ANDIr killed renamable $r8, 65535, implicit-def $cr0
     BCC 68, killed renamable $cr0, %bb.10
   
   bb.4:
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
@@ -24,7 +24,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testRLWNMo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testRLWNMr(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %and = and i32 %a, 255
     %tobool = icmp eq i32 %and, 0
@@ -33,7 +33,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLWNM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLWNM8r(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %a.tr = trunc i64 %a to i32
     %0 = shl i32 %a.tr, 4
@@ -52,7 +52,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSLWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSLWr(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, %b
     %tobool = icmp eq i32 %shl, 0
@@ -68,7 +68,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSRWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSRWr(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
@@ -84,7 +84,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testSRAWo(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
+  define signext i32 @testSRAWr(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
@@ -104,7 +104,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCLo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCLr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
@@ -128,7 +128,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCRo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCRr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
@@ -147,7 +147,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSLDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSLDr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, %b
     %tobool = icmp eq i64 %shl, 0
@@ -163,7 +163,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRDr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
@@ -179,7 +179,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRADo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRADr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
@@ -311,8 +311,8 @@
 
 ...
 ---
-name:            testRLWNMo
-# CHECK-ALL: name: testRLWNMo
+name:            testRLWNMr
+# CHECK-ALL: name: testRLWNMr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -361,8 +361,8 @@
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
-    %4 = RLWNMo %2, %3, 24, 31, implicit-def $cr0
-    ; CHECK: RLWINMo %2, 10, 24, 31, implicit-def $cr0
+    %4 = RLWNMr %2, %3, 24, 31, implicit-def $cr0
+    ; CHECK: RLWINMr %2, 10, 24, 31, implicit-def $cr0
     ; CHECK-LATE: li 3, -22
     ; CHECK-LATE: rlwinm. 5, 4, 10, 24, 31
     %5 = COPY killed $cr0
@@ -375,8 +375,8 @@
 
 ...
 ---
-name:            testRLWNM8o
-# CHECK-ALL: name: testRLWNM8o
+name:            testRLWNM8r
+# CHECK-ALL: name: testRLWNM8r
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -423,8 +423,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 -18
-    %3 = RLWNM8o %1, %2, 20, 27, implicit-def $cr0
-    ; CHECK: RLWINM8o %1, 14, 20, 27, implicit-def $cr0
+    %3 = RLWNM8r %1, %2, 20, 27, implicit-def $cr0
+    ; CHECK: RLWINM8r %1, 14, 20, 27, implicit-def $cr0
     ; CHECK-LATE: rlwinm. 3, 4, 14, 20, 27
     %7 = COPY killed $cr0
     %6 = RLDICL killed %3, 0, 32
@@ -491,8 +491,8 @@
 
 ...
 ---
-name:            testSLWo
-# CHECK-ALL: name: testSLWo
+name:            testSLWr
+# CHECK-ALL: name: testSLWr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -541,8 +541,8 @@
     %0 = COPY $x3
     %2 = LI 35
     %3 = COPY %0.sub_32
-    %4 = SLWo %3, %2, implicit-def $cr0
-    ; CHECK: ANDIo %3, 0, implicit-def $cr0
+    %4 = SLWr %3, %2, implicit-def $cr0
+    ; CHECK: ANDIr %3, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
@@ -611,8 +611,8 @@
 
 ...
 ---
-name:            testSRWo
-# CHECK-ALL: name: testSRWo
+name:            testSRWr
+# CHECK-ALL: name: testSRWr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -661,8 +661,8 @@
     %0 = COPY $x3
     %2 = LI -7
     %3 = COPY %0.sub_32
-    %4 = SRWo %3, %2, implicit-def $cr0
-    ; CHECK: ANDIo %3, 0, implicit-def $cr0
+    %4 = SRWr %3, %2, implicit-def $cr0
+    ; CHECK: ANDIr %3, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
@@ -730,8 +730,8 @@
 
 ...
 ---
-name:            testSRAWo
-# CHECK-ALL: name: testSRAWo
+name:            testSRAWr
+# CHECK-ALL: name: testSRAWr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -778,8 +778,8 @@
     %0 = COPY $x3
     %2 = LI 80
     %3 = COPY %0.sub_32
-    %4 = SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    %4 = SRAWr killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAWr killed %3, %2, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: sraw. 3, 3, 4
     %5 = COPY killed $cr0
     %6 = ISEL %2, %4, %5.sub_eq
@@ -842,8 +842,8 @@
 
 ...
 ---
-name:            testRLDCLo
-# CHECK-ALL: name: testRLDCLo
+name:            testRLDCLr
+# CHECK-ALL: name: testRLDCLr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -889,8 +889,8 @@
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI -37
-    %4 = RLDCLo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICLo %0, 27, 0, implicit-def $cr0
+    %4 = RLDCLr %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICLr %0, 27, 0, implicit-def $cr0
     ; CHECK-LATE: rldicl. 5, 3, 27, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
@@ -952,8 +952,8 @@
 
 ...
 ---
-name:            testRLDCRo
-# CHECK-ALL: name: testRLDCRo
+name:            testRLDCRr
+# CHECK-ALL: name: testRLDCRr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -999,8 +999,8 @@
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI -18
-    %4 = RLDCRo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICRo %0, 46, 0, implicit-def $cr0
+    %4 = RLDCRr %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICRr %0, 46, 0, implicit-def $cr0
     ; CHECK-LATE: rldicr. 5, 3, 46, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
@@ -1060,8 +1060,8 @@
 
 ...
 ---
-name:            testSLDo
-# CHECK-ALL: name: testSLDo
+name:            testSLDr
+# CHECK-ALL: name: testSLDr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -1105,8 +1105,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 88
-    %3 = SLDo %0, killed %2, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 0, implicit-def $cr0
+    %3 = SLDr %0, killed %2, implicit-def $cr0
+    ; CHECK: ANDIr8 %0, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
@@ -1166,8 +1166,8 @@
 
 ...
 ---
-name:            testSRDo
-# CHECK-ALL: name: testSRDo
+name:            testSRDr
+# CHECK-ALL: name: testSRDr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -1211,8 +1211,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 64
-    %3 = SRDo %0, killed %2, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 0, implicit-def $cr0
+    %3 = SRDr %0, killed %2, implicit-def $cr0
+    ; CHECK: ANDIr8 %0, 0, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 0
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
@@ -1272,8 +1272,8 @@
 
 ...
 ---
-name:            testSRADo
-# CHECK-ALL: name: testSRADo
+name:            testSRADr
+# CHECK-ALL: name: testSRADr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -1317,8 +1317,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 68
-    %3 = SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    %3 = SRADr %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRADr %0, killed %2, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: srad. 3, 3, 5
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq
diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
--- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
+++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
@@ -38,7 +38,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testADDCo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testADDCr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %add = add nsw i64 %b, %a
     %cmp = icmp eq i64 %add, 0
@@ -62,7 +62,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testANDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define signext i32 @testANDr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, %a
     %tobool = icmp eq i64 %and, 0
@@ -72,7 +72,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testAND8o(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testAND8r(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, %a
     %tobool = icmp eq i64 %and, 0
@@ -506,7 +506,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCLo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCLr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
@@ -530,7 +530,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDCRo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDCRr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %and = and i64 %b, 63
     %shl = shl i64 %a, %and
@@ -551,7 +551,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDICLo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDICLr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
@@ -561,7 +561,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDICLo2(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDICLr2(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
@@ -571,7 +571,7 @@
   }
 
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLDICLo3(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLDICLr3(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, 11
     %and = and i64 %shr, 16777215
@@ -613,7 +613,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testRLWINMo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testRLWINMr(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %and = and i32 %a, 255
     %tobool = icmp eq i32 %and, 0
@@ -622,7 +622,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testRLWINMo2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testRLWINMr2(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %and = and i32 %a, 255
     %tobool = icmp eq i32 %and, 0
@@ -631,7 +631,7 @@
   }
 
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testRLWINM8o(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testRLWINM8r(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %a.tr = trunc i64 %a to i32
     %0 = shl i32 %a.tr, 4
@@ -650,7 +650,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSLDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSLDr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i64 %a, %b
     %tobool = icmp eq i64 %shl, 0
@@ -666,7 +666,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRDo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRDr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
@@ -682,7 +682,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSLWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSLWr(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shl = shl i32 %a, %b
     %tobool = icmp eq i32 %shl, 0
@@ -698,7 +698,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define zeroext i32 @testSRWo(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
+  define zeroext i32 @testSRWr(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr #0 {
   entry:
     %shr = lshr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
@@ -714,7 +714,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testSRAWo(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
+  define signext i32 @testSRAWr(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i32 %a, %b
     %tobool = icmp eq i32 %shr, 0
@@ -730,7 +730,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define i64 @testSRADo(i64 %a, i64 %b) local_unnamed_addr #0 {
+  define i64 @testSRADr(i64 %a, i64 %b) local_unnamed_addr #0 {
   entry:
     %shr = ashr i64 %a, %b
     %tobool = icmp eq i64 %shr, 0
@@ -1236,8 +1236,8 @@
 
 ...
 ---
-name:            testADDCo
-# CHECK-ALL: name: testADDCo
+name:            testADDCr
+# CHECK-ALL: name: testADDCr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -1284,8 +1284,8 @@
     %1 = LI 433
     %0 = COPY $x3
     %2 = COPY %0.sub_32
-    %3 = ADDCo %1, %2, implicit-def $cr0, implicit-def $carry
-    ; CHECK: ADDICo %2, 433, implicit-def $cr0, implicit-def $carry
+    %3 = ADDCr %1, %2, implicit-def $cr0, implicit-def $carry
+    ; CHECK: ADDICr %2, 433, implicit-def $cr0, implicit-def $carry
     ; CHECK-LATE: addic. 3, 3, 433
     %4 = COPY killed $cr0
     %5 = COPY %4.sub_eq
@@ -1397,8 +1397,8 @@
 
 ...
 ---
-name:            testANDo
-# CHECK-ALL: name: testANDo
+name:            testANDr
+# CHECK-ALL: name: testANDr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -1443,8 +1443,8 @@
     %1 = LI 78
     %0 = COPY $x3
     %2 = COPY %0.sub_32
-    %3 = ANDo %1, %2, implicit-def $cr0
-    ; CHECK: ANDIo %2, 78, implicit-def $cr0
+    %3 = ANDr %1, %2, implicit-def $cr0
+    ; CHECK: ANDIr %2, 78, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 78
     %4 = COPY killed $cr0
     %5 = ISEL %2, %1, %4.sub_eq
@@ -1454,8 +1454,8 @@
 
 ...
 ---
-name:            testAND8o
-# CHECK-ALL: name: testAND8o
+name:            testAND8r
+# CHECK-ALL: name: testAND8r
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -1497,8 +1497,8 @@
   
     %1 = LI8 321
     %0 = COPY $x3
-    %2 = AND8o %1, %0, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 321, implicit-def $cr0
+    %2 = AND8r %1, %0, implicit-def $cr0
+    ; CHECK: ANDIr8 %0, 321, implicit-def $cr0
     ; CHECK-LATE: andi. 5, 3, 321
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %0, %3.sub_eq
@@ -3671,8 +3671,8 @@
 
 ...
 ---
-name:            testRLDCLo
-# CHECK-ALL: name: testRLDCLo
+name:            testRLDCLr
+# CHECK-ALL: name: testRLDCLr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -3718,8 +3718,8 @@
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI 37
-    %4 = RLDCLo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICLo %0, 37, 0, implicit-def $cr0
+    %4 = RLDCLr %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICLr %0, 37, 0, implicit-def $cr0
     ; CHECK-LATE: rldicl. 5, 3, 37, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
@@ -3781,8 +3781,8 @@
 
 ...
 ---
-name:            testRLDCRo
-# CHECK-ALL: name: testRLDCRo
+name:            testRLDCRr
+# CHECK-ALL: name: testRLDCRr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -3828,8 +3828,8 @@
     %0 = COPY $x3
     %2 = RLDICL %1, 0, 58
     %3 = LI 18
-    %4 = RLDCRo %0, killed %3, 0, implicit-def $cr0
-    ; CHECK: RLDICRo %0, 18, 0, implicit-def $cr0
+    %4 = RLDCRr %0, killed %3, 0, implicit-def $cr0
+    ; CHECK: RLDICRr %0, 18, 0, implicit-def $cr0
     ; CHECK-LATE: rldicr. 5, 3, 18, 0
     %5 = COPY killed $cr0
     %6 = ISEL8 %2, %0, %5.sub_eq
@@ -3884,8 +3884,8 @@
 
 ...
 ---
-name:            testRLDICLo
-# CHECK-ALL: name: testRLDICLo
+name:            testRLDICLr
+# CHECK-ALL: name: testRLDICLr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -3927,8 +3927,8 @@
   
     %1 = COPY $x4
     %0 = LI8 -1
-    %2 = RLDICLo %0, 53, 48, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 65535
+    %2 = RLDICLr %0, 53, 48, implicit-def $cr0
+    ; CHECK: ANDIr8 %0, 65535
     ; CHECK-LATE: li 3, -1
     ; CHECK-LATE: andi. 3, 3, 65535
     %3 = COPY killed $cr0
@@ -3938,8 +3938,8 @@
 
 ...
 ---
-name:            testRLDICLo2
-# CHECK-ALL: name: testRLDICLo2
+name:            testRLDICLr2
+# CHECK-ALL: name: testRLDICLr2
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -3981,9 +3981,9 @@
   
     %1 = COPY $x4
     %0 = LI8 200
-    %2 = RLDICLo %0, 61, 3, implicit-def $cr0
+    %2 = RLDICLr %0, 61, 3, implicit-def $cr0
     ; CHECK: LI8 25
-    ; CHECK: ANDIo8 %0, 25
+    ; CHECK: ANDIr8 %0, 25
     ; CHECK-LATE-NOT: andi.
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
@@ -3992,8 +3992,8 @@
 
 ...
 ---
-name:            testRLDICLo3
-# CHECK-ALL: name: testRLDICLo3
+name:            testRLDICLr3
+# CHECK-ALL: name: testRLDICLr3
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4035,8 +4035,8 @@
   
     %1 = COPY $x4
     %0 = LI8 2
-    %2 = RLDICLo %0, 32, 32, implicit-def $cr0
-    ; CHECK: ANDIo8 %0, 0
+    %2 = RLDICLr %0, 32, 32, implicit-def $cr0
+    ; CHECK: ANDIr8 %0, 0
     ; CHECK-LATE: li 3, 2
     ; CHECK-LATE: andi. 3, 3, 0
     %3 = COPY killed $cr0
@@ -4248,8 +4248,8 @@
 
 ...
 ---
-name:            testRLWINMo
-# CHECK-ALL: name: testRLWINMo
+name:            testRLWINMr
+# CHECK-ALL: name: testRLWINMr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4298,9 +4298,9 @@
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
-    %4 = RLWINMo %3, 0, 24, 31, implicit-def $cr0
+    %4 = RLWINMr %3, 0, 24, 31, implicit-def $cr0
     ; CHECK: LI -22
-    ; CHECK: ANDIo %3, 65514
+    ; CHECK: ANDIr %3, 65514
     ; CHECK-LATE: li 3, -22
     ; CHECK-LATE: andi. 5, 3, 234
     %5 = COPY killed $cr0
@@ -4313,8 +4313,8 @@
 
 ...
 ---
-name:            testRLWINMo2
-# CHECK-ALL: name: testRLWINMo2
+name:            testRLWINMr2
+# CHECK-ALL: name: testRLWINMr2
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4363,9 +4363,9 @@
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -22
-    %4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0
+    %4 = RLWINMr %3, 5, 24, 31, implicit-def $cr0
     ; CHECK: LI -22
-    ; CHECK-NOT: ANDIo8 %3, 65514
+    ; CHECK-NOT: ANDIr8 %3, 65514
     ; CHECK-LATE-NOT: andi.
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
@@ -4377,8 +4377,8 @@
 
 ...
 ---
-name:            testRLWINM8o
-# CHECK-ALL: name: testRLWINM8o
+name:            testRLWINM8r
+# CHECK-ALL: name: testRLWINM8r
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4425,8 +4425,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 -18
-    %3 = RLWINM8o %2, 4, 20, 27, implicit-def $cr0
-    ; CHECK: ANDIo8 %2, 3808
+    %3 = RLWINM8r %2, 4, 20, 27, implicit-def $cr0
+    ; CHECK: ANDIr8 %2, 3808
     ; CHECK-LATE: li 3, -18
     ; CHECK-LATE: andi. 3, 3, 3808
     %7 = COPY killed $cr0
@@ -4488,8 +4488,8 @@
 
 ...
 ---
-name:            testSLDo
-# CHECK-ALL: name: testSLDo
+name:            testSLDr
+# CHECK-ALL: name: testSLDr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4533,8 +4533,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 17
-    %3 = SLDo %0, killed %2, implicit-def $cr0
-    ; CHECK: RLDICRo %0, 17, 46, implicit-def $cr0
+    %3 = SLDr %0, killed %2, implicit-def $cr0
+    ; CHECK: RLDICRr %0, 17, 46, implicit-def $cr0
     ; CHECK-LATE: rldicr. 5, 3, 17, 46
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
@@ -4594,8 +4594,8 @@
 
 ...
 ---
-name:            testSRDo
-# CHECK-ALL: name: testSRDo
+name:            testSRDr
+# CHECK-ALL: name: testSRDr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4639,8 +4639,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 17
-    %3 = SRDo %0, killed %2, implicit-def $cr0
-    ; CHECK: RLDICLo %0, 47, 17, implicit-def $cr0
+    %3 = SRDr %0, killed %2, implicit-def $cr0
+    ; CHECK: RLDICLr %0, 47, 17, implicit-def $cr0
     ; CHECK-LATE: rldicl. 5, 3, 47, 17
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %0, %4.sub_eq
@@ -4706,8 +4706,8 @@
 
 ...
 ---
-name:            testSLWo
-# CHECK-ALL: name: testSLWo
+name:            testSLWr
+# CHECK-ALL: name: testSLWr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4756,8 +4756,8 @@
     %0 = COPY $x3
     %2 = LI 11
     %3 = COPY %0.sub_32
-    %4 = SLWo %3, %2, implicit-def $cr0
-    ; CHECK: RLWINMo %3, 11, 0, 20, implicit-def $cr0
+    %4 = SLWr %3, %2, implicit-def $cr0
+    ; CHECK: RLWINMr %3, 11, 0, 20, implicit-def $cr0
     ; CHECK-LATE: rlwinm. 5, 3, 11, 0, 20
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
@@ -4826,8 +4826,8 @@
 
 ...
 ---
-name:            testSRWo
-# CHECK-ALL: name: testSRWo
+name:            testSRWr
+# CHECK-ALL: name: testSRWr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4876,8 +4876,8 @@
     %0 = COPY $x3
     %2 = LI 7
     %3 = COPY %0.sub_32
-    %4 = SRWo %3, %2, implicit-def $cr0
-    ; CHECK: RLWINMo %3, 25, 7, 31
+    %4 = SRWr %3, %2, implicit-def $cr0
+    ; CHECK: RLWINMr %3, 25, 7, 31
     ; CHECK-LATE: rlwinm. 5, 3, 25, 7, 31
     %5 = COPY killed $cr0
     %6 = ISEL %2, %3, %5.sub_eq
@@ -4944,8 +4944,8 @@
 
 ...
 ---
-name:            testSRAWo
-# CHECK-ALL: name: testSRAWo
+name:            testSRAWr
+# CHECK-ALL: name: testSRAWr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -4992,8 +4992,8 @@
     %0 = COPY $x3
     %2 = LI 8
     %3 = COPY %0.sub_32
-    %4 = SRAWo killed %3, %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAWIo killed %3, 8, implicit-def dead $carry, implicit-def $cr0
+    %4 = SRAWr killed %3, %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAWIr killed %3, 8, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: srawi. 3, 3, 8
     %5 = COPY killed $cr0
     %6 = ISEL %2, %4, %5.sub_eq
@@ -5054,8 +5054,8 @@
 
 ...
 ---
-name:            testSRADo
-# CHECK-ALL: name: testSRADo
+name:            testSRADr
+# CHECK-ALL: name: testSRADr
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -5099,8 +5099,8 @@
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 61
-    %3 = SRADo %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRADIo %0, 61, implicit-def dead $carry, implicit-def $cr0
+    %3 = SRADr %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRADIr %0, 61, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: sradi. 3, 3, 61
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq
diff --git a/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir b/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir
--- a/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir
+++ b/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir
@@ -6,7 +6,7 @@
   liveins: $x0, $x3
   successors: %bb.1(0x40000000), %bb.2(0x40000000)
 
-  dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+  dead renamable $x3 = ANDIr8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
   $cr2lt = CROR $cr0gt, $cr0gt
   BCn killed renamable $cr2lt, %bb.2
   B %bb.1
@@ -26,7 +26,7 @@
 
 # CHECK: body:             |          
 # CHECK:  bb.0:
-# CHECK:    dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
+# CHECK:    dead renamable $x3 = ANDIr8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
 # CHECK:    $cr2lt = CROR $cr0gt, $cr0gt
 # CHECK:    renamable $x3 = LIS8 4096
 # CHECK:    MTLR8 $x0, implicit-def $lr8
diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
--- a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -7,11 +7,11 @@
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead $cr0
+; CHECK: ANDIr8 killed {{[^,]+}}, 65520, implicit-def dead $cr0
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
-; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def $cr0
+; CHECK: ANDIr8 {{[^,]+}}, 65520, implicit-def $cr0
 ; CHECK: COPY $cr0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
@@ -26,7 +26,7 @@
 
 ; CHECK-LABEL: fn2
 define signext i32 @fn2(i64 %a, i64 %b) {
-; CHECK: OR8o {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr0
+; CHECK: OR8r {{[^, ]+}}, {{[^, ]+}}, implicit-def $cr0
 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY killed $cr
 ; CHECK: BCC 12, killed [[CREG]]
   %1 = or i64 %b, %a
@@ -42,7 +42,7 @@
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
+; CHECK: ANDIr killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
 ; CHECK: BCC 76, killed [[CREG]]
   %1 = and i32 %a, 10
@@ -61,7 +61,7 @@
 
 ; CHECK-LABEL: fn4
 define i64 @fn4(i64 %a, i64 %b) {
-; CHECK: ADD8o
+; CHECK: ADD8r
 ; CHECK-NOT: CMP
 ; CHECK: BCC 71
 
@@ -81,11 +81,11 @@
 declare void @exit(i32 signext)
 
 ; Since %v1 and %v2 are zero-extended 32-bit values, %1 is also zero-extended.
-; In this case, we want to use ORo instead of OR + CMPLWI.
+; In this case, we want to use ORr instead of OR + CMPLWI.
 
 ; CHECK-LABEL: fn5
 define zeroext i32 @fn5(i32* %p1, i32* %p2) {
-; CHECK: ORo
+; CHECK: ORr
 ; CHECK-NOT: CMP
 ; CHECK: BCC
   %v1 = load i32, i32* %p1
@@ -107,11 +107,11 @@
 ; CHECK-LABEL: fn6
 define i8* @fn6(i8* readonly %p) {
 ; CHECK: LBZU
-; CHECK: EXTSBo
+; CHECK: EXTSBr
 ; CHECK-NOT: CMP
 ; CHECK: BCC
 ; CHECK: LBZU
-; CHECK: EXTSBo
+; CHECK: EXTSBr
 ; CHECK-NOT: CMP
 ; CHECK: BCC
 
diff --git a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
--- a/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
+++ b/llvm/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@@ -114,7 +114,7 @@
     %24 = CNTLZD killed %20
     %25 = CMPLDI %15, 0
     BCC 76, %25, %bb.2.loop
-    ; CHECK: SUBFC8o %3, %1, implicit-def $carry, implicit-def $cr0
+    ; CHECK: SUBFC8r %3, %1, implicit-def $carry, implicit-def $cr0
     ; CHECK: COPY killed $cr0
     ; CHECK: BCC
 
diff --git a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
--- a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
+++ b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir
@@ -14,14 +14,14 @@
   ; CHECK:   [[COPY1:%[0-9]+]]:g8rc = COPY $x5
   ; CHECK:   [[COPY2:%[0-9]+]]:g8rc = COPY $x4
   ; CHECK:   [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
-  ; CHECK:   [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
+  ; CHECK:   [[ANDIr8_:%[0-9]+]]:g8rc = ANDIr8 [[COPY1]], 1, implicit-def $cr0
   ; CHECK:   [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
   ; CHECK:   BCn killed [[COPY4]], %bb.2
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
   ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
-  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
+  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIr8_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
   ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
   ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
@@ -41,7 +41,7 @@
     %3:g8rc = COPY $x5
     %2:g8rc = COPY $x4
     %1:g8rc_and_g8rc_nox0 = COPY $x3
-    %11:g8rc = ANDIo8 %3, 1, implicit-def $cr0
+    %11:g8rc = ANDIr8 %3, 1, implicit-def $cr0
     %6:crbitrc = COPY $cr0gt
     BCn killed %6, %bb.2
     B %bb.1
diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
--- a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
+++ b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir
@@ -16,7 +16,7 @@
   }
   
   ; Function Attrs: norecurse nounwind readnone
-  define signext i32 @testRLWINMNoGPRUseZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
+  define signext i32 @testRLWINMNrGPRUseZero(i32 signext %a, i32 signext %b) local_unnamed_addr #0 {
   entry:
     %shl.mask = and i32 %a, 1048575
     %tobool = icmp eq i32 %shl.mask, 0
@@ -120,9 +120,9 @@
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc = LI -11
-    %4:gprc_and_gprc_nor0 = RLWINMo %3, 2, 20, 31, implicit-def $cr0
+    %4:gprc_and_gprc_nor0 = RLWINMr %3, 2, 20, 31, implicit-def $cr0
     ; CHECK: LI 4055
-    ; CHECK: ANDIo %3, 4055
+    ; CHECK: ANDIr %3, 4055
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rlwinm.
     %5:crrc = COPY killed $cr0
@@ -133,7 +133,7 @@
 
 ...
 ---
-name:            testRLWINMNoGPRUseZero
+name:            testRLWINMNrGPRUseZero
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
@@ -180,9 +180,9 @@
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc_and_gprc_nor0 = LI 1
-    %4:gprc = RLWINMo %3, 21, 20, 31, implicit-def $cr0
+    %4:gprc = RLWINMr %3, 21, 20, 31, implicit-def $cr0
     ; CHECK: LI 1
-    ; CHECK: ANDIo %3, 0
+    ; CHECK: ANDIr %3, 0
     ; CHECK-LATE: li [[IMM:[0-9]+]], 1
     ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
     %5:crrc = COPY killed $cr0
@@ -240,9 +240,9 @@
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc_and_gprc_nor0 = LI -11
-    %4:gprc = RLWINMo %3, 2, 20, 31, implicit-def $cr0
+    %4:gprc = RLWINMr %3, 2, 20, 31, implicit-def $cr0
     ; CHECK: LI -11
-    ; CHECK: ANDIo %3, 65525
+    ; CHECK: ANDIr %3, 65525
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rlwinm.
     %5:crrc = COPY killed $cr0
@@ -295,9 +295,9 @@
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc = LI8 -11
-    %2:g8rc_and_g8rc_nox0  = RLDICLo %0, 2, 49, implicit-def $cr0
+    %2:g8rc_and_g8rc_nox0  = RLDICLr %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 32727
-    ; CHECK: ANDIo8 %0, 32727
+    ; CHECK: ANDIr8 %0, 32727
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0
@@ -349,9 +349,9 @@
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc_and_g8rc_nox0 = LI8 1
-    %2:g8rc = RLDICLo %0, 32, 33, implicit-def $cr0
+    %2:g8rc = RLDICLr %0, 32, 33, implicit-def $cr0
     ; CHECK: LI8 1
-    ; CHECK: ANDIo8 %0, 0
+    ; CHECK: ANDIr8 %0, 0
     ; CHECK-LATE: li [[IMM:[0-9]+]], 1
     ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0
     %3:crrc = COPY killed $cr0
@@ -403,9 +403,9 @@
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc_and_g8rc_nox0 = LI8 -11
-    %2:g8rc = RLDICLo %0, 2, 49, implicit-def $cr0
+    %2:g8rc = RLDICLr %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 -11
-    ; CHECK: ANDIo8 %0, 65525
+    ; CHECK: ANDIr8 %0, 65525
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0