diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -94,6 +94,13 @@ bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override; + + std::pair + decomposeMachineOperandsTargetFlags(unsigned TF) const override; + + ArrayRef> + getSerializableDirectMachineOperandTargetFlags() const override; + protected: const RISCVSubtarget &STI; }; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -597,3 +597,28 @@ } return false; } + +std::pair +RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const { + const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK; + return std::make_pair(TF & Mask, TF & ~Mask); +} + +ArrayRef> +RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { + using namespace RISCVII; + static const std::pair TargetFlags[] = { + {MO_CALL, "riscv-call"}, + {MO_PLT, "riscv-plt"}, + {MO_LO, "riscv-lo"}, + {MO_HI, "riscv-hi"}, + {MO_PCREL_LO, "riscv-pcrel-lo"}, + {MO_PCREL_HI, "riscv-pcrel-hi"}, + {MO_GOT_HI, "riscv-got-hi"}, + {MO_TPREL_LO, "riscv-tprel-lo"}, + {MO_TPREL_HI, "riscv-tprel-hi"}, + {MO_TPREL_ADD, "riscv-tprel-add"}, + {MO_TLS_GOT_HI, "riscv-tls-got-hi"}, + {MO_TLS_GD_HI, "riscv-tls-gd-hi"}}; + return makeArrayRef(TargetFlags); +} diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h --- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h @@ -48,20 +48,26 @@ InstFormatMask = 31 }; +// RISC-V Specific Machine Operand Flags enum { - MO_None, - MO_CALL, - MO_PLT, - MO_LO, - MO_HI, - MO_PCREL_LO, - MO_PCREL_HI, - MO_GOT_HI, - MO_TPREL_LO, - MO_TPREL_HI, - MO_TPREL_ADD, - MO_TLS_GOT_HI, - MO_TLS_GD_HI, + MO_None = 0, + MO_CALL = 1, + MO_PLT = 2, + MO_LO = 3, + MO_HI = 4, + MO_PCREL_LO = 5, + MO_PCREL_HI = 6, + MO_GOT_HI = 7, + MO_TPREL_LO = 8, + MO_TPREL_HI = 9, + MO_TPREL_ADD = 10, + MO_TLS_GOT_HI = 11, + MO_TLS_GD_HI = 12, + + // Used to differentiate between target-specific "direct" flags and "bitmask" + // flags. A machine operand can only have one "direct" flag, but can have + // multiple "bitmask" flags. + MO_DIRECT_FLAG_MASK = 15 }; } // namespace RISCVII