Index: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -65,35 +65,60 @@ case ISD::EXTRACT_VECTOR_ELT: R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break; case ISD::FABS: R = SoftenFloatRes_FABS(N); break; + case ISD::STRICT_FMINNUM: case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; + case ISD::STRICT_FMAXNUM: case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; + case ISD::STRICT_FADD: case ISD::FADD: R = SoftenFloatRes_FADD(N); break; case ISD::FCBRT: R = SoftenFloatRes_FCBRT(N); break; + case ISD::STRICT_FCEIL: case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; + case ISD::STRICT_FCOS: case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; + case ISD::STRICT_FDIV: case ISD::FDIV: R = SoftenFloatRes_FDIV(N); break; + case ISD::STRICT_FEXP: case ISD::FEXP: R = SoftenFloatRes_FEXP(N); break; + case ISD::STRICT_FEXP2: case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; + case ISD::STRICT_FFLOOR: case ISD::FFLOOR: R = SoftenFloatRes_FFLOOR(N); break; + case ISD::STRICT_FLOG: case ISD::FLOG: R = SoftenFloatRes_FLOG(N); break; + case ISD::STRICT_FLOG2: case ISD::FLOG2: R = SoftenFloatRes_FLOG2(N); break; + case ISD::STRICT_FLOG10: case ISD::FLOG10: R = SoftenFloatRes_FLOG10(N); break; + case ISD::STRICT_FMA: case ISD::FMA: R = SoftenFloatRes_FMA(N); break; + case ISD::STRICT_FMUL: case ISD::FMUL: R = SoftenFloatRes_FMUL(N); break; + case ISD::STRICT_FNEARBYINT: case ISD::FNEARBYINT: R = SoftenFloatRes_FNEARBYINT(N); break; case ISD::FNEG: R = SoftenFloatRes_FNEG(N); break; + case ISD::STRICT_FP_EXTEND: case ISD::FP_EXTEND: R = SoftenFloatRes_FP_EXTEND(N); break; case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; case ISD::FP16_TO_FP: R = SoftenFloatRes_FP16_TO_FP(N); break; + case ISD::STRICT_FPOW: case ISD::FPOW: R = SoftenFloatRes_FPOW(N); break; + case ISD::STRICT_FPOWI: case ISD::FPOWI: R = SoftenFloatRes_FPOWI(N); break; + case ISD::STRICT_FREM: case ISD::FREM: R = SoftenFloatRes_FREM(N); break; + case ISD::STRICT_FRINT: case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; + case ISD::STRICT_FROUND: case ISD::FROUND: R = SoftenFloatRes_FROUND(N); break; + case ISD::STRICT_FSIN: case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; + case ISD::STRICT_FSQRT: case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break; + case ISD::STRICT_FSUB: case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break; + case ISD::STRICT_FTRUNC: case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; case ISD::LOAD: R = SoftenFloatRes_LOAD(N); break; case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break; @@ -113,25 +138,43 @@ } SDValue DAGTypeLegalizer::SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC) { + bool IsStrict = N->isStrictFPOpcode(); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); - assert(N->getNumOperands() == 1 && "Unexpected number of operands!"); - SDValue Op = GetSoftenedFloat(N->getOperand(0)); + unsigned Offset = IsStrict ? 1 : 0; + assert(N->getNumOperands() == (1 + Offset) && + "Unexpected number of operands!"); + SDValue Op = GetSoftenedFloat(N->getOperand(0 + Offset)); + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); TargetLowering::MakeLibCallOptions CallOptions; - EVT OpVT = N->getOperand(0).getValueType(); + EVT OpVT = N->getOperand(0 + Offset).getValueType(); CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true); - return TLI.makeLibCall(DAG, LC, NVT, Op, CallOptions, SDLoc(N)).first; + std::pair Tmp = TLI.makeLibCall(DAG, LC, NVT, Op, + CallOptions, SDLoc(N), + Chain); + if (IsStrict) + ReplaceValueWith(SDValue(N, 1), Tmp.second); + return Tmp.first; } SDValue DAGTypeLegalizer::SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC) { + bool IsStrict = N->isStrictFPOpcode(); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); - assert(N->getNumOperands() == 2 && "Unexpected number of operands!"); - SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), - GetSoftenedFloat(N->getOperand(1)) }; + unsigned Offset = IsStrict ? 1 : 0; + assert(N->getNumOperands() == (2 + Offset) && + "Unexpected number of operands!"); + SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0 + Offset)), + GetSoftenedFloat(N->getOperand(1 + Offset)) }; + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); TargetLowering::MakeLibCallOptions CallOptions; - EVT OpsVT[2] = { N->getOperand(0).getValueType(), - N->getOperand(1).getValueType() }; + EVT OpsVT[2] = { N->getOperand(0 + Offset).getValueType(), + N->getOperand(1 + Offset).getValueType() }; CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true); - return TLI.makeLibCall(DAG, LC, NVT, Ops, CallOptions, SDLoc(N)).first; + std::pair Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops, + CallOptions, SDLoc(N), + Chain); + if (IsStrict) + ReplaceValueWith(SDValue(N, 1), Tmp.second); + return Tmp.first; } SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) { @@ -368,22 +411,29 @@ } SDValue DAGTypeLegalizer::SoftenFloatRes_FMA(SDNode *N) { + bool IsStrict = N->isStrictFPOpcode(); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); - SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0)), - GetSoftenedFloat(N->getOperand(1)), - GetSoftenedFloat(N->getOperand(2)) }; + unsigned Offset = IsStrict ? 1 : 0; + SDValue Ops[3] = { GetSoftenedFloat(N->getOperand(0 + Offset)), + GetSoftenedFloat(N->getOperand(1 + Offset)), + GetSoftenedFloat(N->getOperand(2 + Offset)) }; + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); TargetLowering::MakeLibCallOptions CallOptions; - EVT OpsVT[3] = { N->getOperand(0).getValueType(), - N->getOperand(1).getValueType(), - N->getOperand(2).getValueType() }; + EVT OpsVT[3] = { N->getOperand(0 + Offset).getValueType(), + N->getOperand(1 + Offset).getValueType(), + N->getOperand(2 + Offset).getValueType() }; CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true); - return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0), - RTLIB::FMA_F32, - RTLIB::FMA_F64, - RTLIB::FMA_F80, - RTLIB::FMA_F128, - RTLIB::FMA_PPCF128), - NVT, Ops, CallOptions, SDLoc(N)).first; + std::pair Tmp = TLI.makeLibCall(DAG, + GetFPLibCall(N->getValueType(0), + RTLIB::FMA_F32, + RTLIB::FMA_F64, + RTLIB::FMA_F80, + RTLIB::FMA_F128, + RTLIB::FMA_PPCF128), + NVT, Ops, CallOptions, SDLoc(N), Chain); + if (IsStrict) + ReplaceValueWith(SDValue(N, 1), Tmp.second); + return Tmp.first; } SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { @@ -430,14 +480,24 @@ } SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { + bool IsStrict = N->isStrictFPOpcode(); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); - SDValue Op = N->getOperand(0); + SDValue Op = N->getOperand(IsStrict ? 1 : 0); + + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); // There's only a libcall for f16 -> f32, so proceed in two stages. Also, it's // entirely possible for both f16 and f32 to be legal, so use the fully // hard-float FP_EXTEND rather than FP16_TO_FP. if (Op.getValueType() == MVT::f16 && N->getValueType(0) != MVT::f32) { - Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); + if (IsStrict) { + Op = DAG.getNode(ISD::STRICT_FP_EXTEND, SDLoc(N), + { MVT::f32, MVT::Other }, { Chain, Op }); + Chain = Op.getValue(1); + } else { + Op = DAG.getNode(ISD::FP_EXTEND, SDLoc(N), MVT::f32, Op); + } + if (getTypeAction(MVT::f32) == TargetLowering::TypeSoftenFloat) AddToWorklist(Op.getNode()); } @@ -456,7 +516,12 @@ TargetLowering::MakeLibCallOptions CallOptions; EVT OpsVT[1] = { N->getOperand(0).getValueType() }; CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true); - return TLI.makeLibCall(DAG, LC, NVT, Op, CallOptions, SDLoc(N)).first; + std::pair Tmp = TLI.makeLibCall(DAG, LC, NVT, Op, + CallOptions, SDLoc(N), + Chain); + if (IsStrict) + ReplaceValueWith(SDValue(N, 1), Tmp.second); + return Tmp.first; } // FIXME: Should we just use 'normal' FP_EXTEND / FP_TRUNC instead of special @@ -505,7 +570,9 @@ } SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) { - assert(N->getOperand(1).getValueType() == MVT::i32 && + bool IsStrict = N->isStrictFPOpcode(); + unsigned Offset = IsStrict ? 1 : 0; + assert(N->getOperand(1 + Offset).getValueType() == MVT::i32 && "Unsupported power type!"); RTLIB::Libcall LC = GetFPLibCall(N->getValueType(0), RTLIB::POWI_F32, @@ -521,12 +588,19 @@ } EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); - SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) }; + SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0 + Offset)), + N->getOperand(1 + Offset) }; + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); TargetLowering::MakeLibCallOptions CallOptions; - EVT OpsVT[2] = { N->getOperand(0).getValueType(), - N->getOperand(1).getValueType() }; + EVT OpsVT[2] = { N->getOperand(0 + Offset).getValueType(), + N->getOperand(1 + Offset).getValueType() }; CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true); - return TLI.makeLibCall(DAG, LC, NVT, Ops, CallOptions, SDLoc(N)).first; + std::pair Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops, + CallOptions, SDLoc(N), + Chain); + if (IsStrict) + ReplaceValueWith(SDValue(N, 1), Tmp.second); + return Tmp.first; } SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) { @@ -718,6 +792,7 @@ case ISD::BR_CC: Res = SoftenFloatOp_BR_CC(N); break; case ISD::FP_EXTEND: Res = SoftenFloatOp_FP_EXTEND(N); break; case ISD::FP_TO_FP16: // Same as FP_ROUND for softening purposes + case ISD::STRICT_FP_ROUND: case ISD::FP_ROUND: Res = SoftenFloatOp_FP_ROUND(N); break; case ISD::FP_TO_SINT: case ISD::FP_TO_UINT: Res = SoftenFloatOp_FP_TO_XINT(N); break; @@ -774,20 +849,31 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) { // We actually deal with the partially-softened FP_TO_FP16 node too, which // returns an i16 so doesn't meet the constraints necessary for FP_ROUND. - assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16); + assert(N->getOpcode() == ISD::FP_ROUND || N->getOpcode() == ISD::FP_TO_FP16 || + N->getOpcode() == ISD::STRICT_FP_ROUND); - EVT SVT = N->getOperand(0).getValueType(); + bool IsStrict = N->isStrictFPOpcode(); + SDValue Op = N->getOperand(IsStrict ? 1 : 0); + EVT SVT = Op.getValueType(); EVT RVT = N->getValueType(0); EVT FloatRVT = N->getOpcode() == ISD::FP_TO_FP16 ? MVT::f16 : RVT; RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, FloatRVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall"); - SDValue Op = GetSoftenedFloat(N->getOperand(0)); + SDValue Chain = IsStrict ? N->getOperand(0) : SDValue(); + Op = GetSoftenedFloat(Op); TargetLowering::MakeLibCallOptions CallOptions; - EVT OpsVT[1] = { N->getOperand(0).getValueType() }; - CallOptions.setTypeListBeforeSoften(OpsVT, N->getValueType(0), true); - return TLI.makeLibCall(DAG, LC, RVT, Op, CallOptions, SDLoc(N)).first; + CallOptions.setTypeListBeforeSoften(SVT, RVT, true); + std::pair Tmp = TLI.makeLibCall(DAG, LC, RVT, Op, + CallOptions, SDLoc(N), + Chain); + if (IsStrict) { + ReplaceValueWith(SDValue(N, 1), Tmp.second); + ReplaceValueWith(SDValue(N, 0), Tmp.first); + return SDValue(); + } + return Tmp.first; } SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) { Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h =================================================================== --- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ /dev/null @@ -1,964 +0,0 @@ -//===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file defines the DAGTypeLegalizer class. This is a private interface -// shared between the code that implements the SelectionDAG::LegalizeTypes -// method. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H -#define LLVM_LIB_CODEGEN_SELECTIONDAG_LEGALIZETYPES_H - -#include "llvm/ADT/DenseMap.h" -#include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/CodeGen/TargetLowering.h" -#include "llvm/Support/Compiler.h" -#include "llvm/Support/Debug.h" - -namespace llvm { - -//===----------------------------------------------------------------------===// -/// This takes an arbitrary SelectionDAG as input and hacks on it until only -/// value types the target machine can handle are left. This involves promoting -/// small sizes to large sizes or splitting up large values into small values. -/// -class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer { - const TargetLowering &TLI; - SelectionDAG &DAG; -public: - /// This pass uses the NodeId on the SDNodes to hold information about the - /// state of the node. The enum has all the values. - enum NodeIdFlags { - /// All operands have been processed, so this node is ready to be handled. - ReadyToProcess = 0, - - /// This is a new node, not before seen, that was created in the process of - /// legalizing some other node. - NewNode = -1, - - /// This node's ID needs to be set to the number of its unprocessed - /// operands. - Unanalyzed = -2, - - /// This is a node that has already been processed. - Processed = -3 - - // 1+ - This is a node which has this many unprocessed operands. - }; -private: - - /// This is a bitvector that contains two bits for each simple value type, - /// where the two bits correspond to the LegalizeAction enum from - /// TargetLowering. This can be queried with "getTypeAction(VT)". - TargetLowering::ValueTypeActionImpl ValueTypeActions; - - /// Return how we should legalize values of this type. - TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { - return TLI.getTypeAction(*DAG.getContext(), VT); - } - - /// Return true if this type is legal on this target. - bool isTypeLegal(EVT VT) const { - return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal; - } - - /// Return true if this is a simple legal type. - bool isSimpleLegalType(EVT VT) const { - return VT.isSimple() && TLI.isTypeLegal(VT); - } - - EVT getSetCCResultType(EVT VT) const { - return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); - } - - /// Pretend all of this node's results are legal. - bool IgnoreNodeResults(SDNode *N) const { - return N->getOpcode() == ISD::TargetConstant || - N->getOpcode() == ISD::Register; - } - - // Bijection from SDValue to unique id. As each created node gets a - // new id we do not need to worry about reuse expunging. Should we - // run out of ids, we can do a one time expensive compactifcation. - typedef unsigned TableId; - - TableId NextValueId = 1; - - SmallDenseMap ValueToIdMap; - SmallDenseMap IdToValueMap; - - /// For integer nodes that are below legal width, this map indicates what - /// promoted value to use. - SmallDenseMap PromotedIntegers; - - /// For integer nodes that need to be expanded this map indicates which - /// operands are the expanded version of the input. - SmallDenseMap, 8> ExpandedIntegers; - - /// For floating-point nodes converted to integers of the same size, this map - /// indicates the converted value to use. - SmallDenseMap SoftenedFloats; - - /// For floating-point nodes that have a smaller precision than the smallest - /// supported precision, this map indicates what promoted value to use. - SmallDenseMap PromotedFloats; - - /// For float nodes that need to be expanded this map indicates which operands - /// are the expanded version of the input. - SmallDenseMap, 8> ExpandedFloats; - - /// For nodes that are <1 x ty>, this map indicates the scalar value of type - /// 'ty' to use. - SmallDenseMap ScalarizedVectors; - - /// For nodes that need to be split this map indicates which operands are the - /// expanded version of the input. - SmallDenseMap, 8> SplitVectors; - - /// For vector nodes that need to be widened, indicates the widened value to - /// use. - SmallDenseMap WidenedVectors; - - /// For values that have been replaced with another, indicates the replacement - /// value to use. - SmallDenseMap ReplacedValues; - - /// This defines a worklist of nodes to process. In order to be pushed onto - /// this worklist, all operands of a node must have already been processed. - SmallVector Worklist; - - TableId getTableId(SDValue V) { - assert(V.getNode() && "Getting TableId on SDValue()"); - - auto I = ValueToIdMap.find(V); - if (I != ValueToIdMap.end()) { - // replace if there's been a shift. - RemapId(I->second); - assert(I->second && "All Ids should be nonzero"); - return I->second; - } - // Add if it's not there. - ValueToIdMap.insert(std::make_pair(V, NextValueId)); - IdToValueMap.insert(std::make_pair(NextValueId, V)); - ++NextValueId; - assert(NextValueId != 0 && - "Ran out of Ids. Increase id type size or add compactification"); - return NextValueId - 1; - } - - const SDValue &getSDValue(TableId &Id) { - RemapId(Id); - assert(Id && "TableId should be non-zero"); - return IdToValueMap[Id]; - } - -public: - explicit DAGTypeLegalizer(SelectionDAG &dag) - : TLI(dag.getTargetLoweringInfo()), DAG(dag), - ValueTypeActions(TLI.getValueTypeActions()) { - static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, - "Too many value types for ValueTypeActions to hold!"); - } - - /// This is the main entry point for the type legalizer. This does a - /// top-down traversal of the dag, legalizing types as it goes. Returns - /// "true" if it made any changes. - bool run(); - - void NoteDeletion(SDNode *Old, SDNode *New) { - for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) { - TableId NewId = getTableId(SDValue(New, i)); - TableId OldId = getTableId(SDValue(Old, i)); - - if (OldId != NewId) - ReplacedValues[OldId] = NewId; - - // Delete Node from tables. - ValueToIdMap.erase(SDValue(Old, i)); - IdToValueMap.erase(OldId); - PromotedIntegers.erase(OldId); - ExpandedIntegers.erase(OldId); - SoftenedFloats.erase(OldId); - PromotedFloats.erase(OldId); - ExpandedFloats.erase(OldId); - ScalarizedVectors.erase(OldId); - SplitVectors.erase(OldId); - WidenedVectors.erase(OldId); - } - } - - SelectionDAG &getDAG() const { return DAG; } - -private: - SDNode *AnalyzeNewNode(SDNode *N); - void AnalyzeNewValue(SDValue &Val); - void PerformExpensiveChecks(); - void RemapId(TableId &Id); - void RemapValue(SDValue &V); - - // Common routines. - SDValue BitConvertToInteger(SDValue Op); - SDValue BitConvertVectorToIntegerVector(SDValue Op); - SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT); - bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); - bool CustomWidenLowerNode(SDNode *N, EVT VT); - - /// Replace each result of the given MERGE_VALUES node with the corresponding - /// input operand, except for the result 'ResNo', for which the corresponding - /// input operand is returned. - SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo); - - SDValue JoinIntegers(SDValue Lo, SDValue Hi); - SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); - - std::pair ExpandAtomic(SDNode *Node); - - SDValue PromoteTargetBoolean(SDValue Bool, EVT ValVT); - - void ReplaceValueWith(SDValue From, SDValue To); - void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); - void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, - SDValue &Lo, SDValue &Hi); - - void AddToWorklist(SDNode *N) { - N->setNodeId(ReadyToProcess); - Worklist.push_back(N); - } - - //===--------------------------------------------------------------------===// - // Integer Promotion Support: LegalizeIntegerTypes.cpp - //===--------------------------------------------------------------------===// - - /// Given a processed operand Op which was promoted to a larger integer type, - /// this returns the promoted value. The low bits of the promoted value - /// corresponding to the original type are exactly equal to Op. - /// The extra bits contain rubbish, so the promoted value may need to be zero- - /// or sign-extended from the original type before it is usable (the helpers - /// SExtPromotedInteger and ZExtPromotedInteger can do this for you). - /// For example, if Op is an i16 and was promoted to an i32, then this method - /// returns an i32, the lower 16 bits of which coincide with Op, and the upper - /// 16 bits of which contain rubbish. - SDValue GetPromotedInteger(SDValue Op) { - TableId &PromotedId = PromotedIntegers[getTableId(Op)]; - SDValue PromotedOp = getSDValue(PromotedId); - assert(PromotedOp.getNode() && "Operand wasn't promoted?"); - return PromotedOp; - } - void SetPromotedInteger(SDValue Op, SDValue Result); - - /// Get a promoted operand and sign extend it to the final size. - SDValue SExtPromotedInteger(SDValue Op) { - EVT OldVT = Op.getValueType(); - SDLoc dl(Op); - Op = GetPromotedInteger(Op); - return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, - DAG.getValueType(OldVT)); - } - - /// Get a promoted operand and zero extend it to the final size. - SDValue ZExtPromotedInteger(SDValue Op) { - EVT OldVT = Op.getValueType(); - SDLoc dl(Op); - Op = GetPromotedInteger(Op); - return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType()); - } - - // Get a promoted operand and sign or zero extend it to the final size - // (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given - // subtarget and type, the choice of sign or zero-extension will be - // consistent. - SDValue SExtOrZExtPromotedInteger(SDValue Op) { - EVT OldVT = Op.getValueType(); - SDLoc DL(Op); - Op = GetPromotedInteger(Op); - if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType())) - return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op, - DAG.getValueType(OldVT)); - return DAG.getZeroExtendInReg(Op, DL, OldVT.getScalarType()); - } - - // Integer Result Promotion. - void PromoteIntegerResult(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_AssertSext(SDNode *N); - SDValue PromoteIntRes_AssertZext(SDNode *N); - SDValue PromoteIntRes_Atomic0(AtomicSDNode *N); - SDValue PromoteIntRes_Atomic1(AtomicSDNode *N); - SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo); - SDValue PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N); - SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N); - SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N); - SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N); - SDValue PromoteIntRes_SPLAT_VECTOR(SDNode *N); - SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N); - SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N); - SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N); - SDValue PromoteIntRes_BITCAST(SDNode *N); - SDValue PromoteIntRes_BSWAP(SDNode *N); - SDValue PromoteIntRes_BITREVERSE(SDNode *N); - SDValue PromoteIntRes_BUILD_PAIR(SDNode *N); - SDValue PromoteIntRes_Constant(SDNode *N); - SDValue PromoteIntRes_CTLZ(SDNode *N); - SDValue PromoteIntRes_CTPOP(SDNode *N); - SDValue PromoteIntRes_CTTZ(SDNode *N); - SDValue PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N); - SDValue PromoteIntRes_FP_TO_XINT(SDNode *N); - SDValue PromoteIntRes_FP_TO_FP16(SDNode *N); - SDValue PromoteIntRes_INT_EXTEND(SDNode *N); - SDValue PromoteIntRes_LOAD(LoadSDNode *N); - SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N); - SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N); - SDValue PromoteIntRes_Overflow(SDNode *N); - SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_SELECT(SDNode *N); - SDValue PromoteIntRes_VSELECT(SDNode *N); - SDValue PromoteIntRes_SELECT_CC(SDNode *N); - SDValue PromoteIntRes_SETCC(SDNode *N); - SDValue PromoteIntRes_SHL(SDNode *N); - SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N); - SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N); - SDValue PromoteIntRes_SExtIntBinOp(SDNode *N); - SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N); - SDValue PromoteIntRes_SRA(SDNode *N); - SDValue PromoteIntRes_SRL(SDNode *N); - SDValue PromoteIntRes_TRUNCATE(SDNode *N); - SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_UNDEF(SDNode *N); - SDValue PromoteIntRes_VAARG(SDNode *N); - SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo); - SDValue PromoteIntRes_ADDSUBSAT(SDNode *N); - SDValue PromoteIntRes_MULFIX(SDNode *N); - SDValue PromoteIntRes_FLT_ROUNDS(SDNode *N); - SDValue PromoteIntRes_VECREDUCE(SDNode *N); - SDValue PromoteIntRes_ABS(SDNode *N); - - // Integer Operand Promotion. - bool PromoteIntegerOperand(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_ANY_EXTEND(SDNode *N); - SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N); - SDValue PromoteIntOp_BITCAST(SDNode *N); - SDValue PromoteIntOp_BUILD_PAIR(SDNode *N); - SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N); - SDValue PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N); - SDValue PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N); - SDValue PromoteIntOp_CONCAT_VECTORS(SDNode *N); - SDValue PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N); - SDValue PromoteIntOp_SPLAT_VECTOR(SDNode *N); - SDValue PromoteIntOp_SELECT(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_SETCC(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_Shift(SDNode *N); - SDValue PromoteIntOp_SIGN_EXTEND(SDNode *N); - SDValue PromoteIntOp_SINT_TO_FP(SDNode *N); - SDValue PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo); - SDValue PromoteIntOp_TRUNCATE(SDNode *N); - SDValue PromoteIntOp_UINT_TO_FP(SDNode *N); - SDValue PromoteIntOp_ZERO_EXTEND(SDNode *N); - SDValue PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo); - SDValue PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo); - SDValue PromoteIntOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo); - SDValue PromoteIntOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo); - SDValue PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_FRAMERETURNADDR(SDNode *N); - SDValue PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo); - SDValue PromoteIntOp_MULFIX(SDNode *N); - SDValue PromoteIntOp_FPOWI(SDNode *N); - SDValue PromoteIntOp_VECREDUCE(SDNode *N); - - void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code); - - //===--------------------------------------------------------------------===// - // Integer Expansion Support: LegalizeIntegerTypes.cpp - //===--------------------------------------------------------------------===// - - /// Given a processed operand Op which was expanded into two integers of half - /// the size, this returns the two halves. The low bits of Op are exactly - /// equal to the bits of Lo; the high bits exactly equal Hi. - /// For example, if Op is an i64 which was expanded into two i32's, then this - /// method returns the two i32's, with Lo being equal to the lower 32 bits of - /// Op, and Hi being equal to the upper 32 bits. - void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi); - void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi); - - // Integer Result Expansion. - void ExpandIntegerResult(SDNode *N, unsigned ResNo); - void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ABS (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_CTLZ (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_CTPOP (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_CTTZ (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_LOAD (LoadSDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_READCYCLECOUNTER (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_SIGN_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_SIGN_EXTEND_INREG (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_TRUNCATE (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ZERO_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_FLT_ROUNDS (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_FP_TO_SINT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_FP_TO_UINT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_LLROUND_LLRINT (SDNode *N, SDValue &Lo, SDValue &Hi); - - void ExpandIntRes_Logical (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ADDSUB (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ADDSUBC (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ADDSUBE (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ADDSUBCARRY (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_BITREVERSE (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_BSWAP (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_MUL (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_SDIV (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_SREM (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_UDIV (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_UREM (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_Shift (SDNode *N, SDValue &Lo, SDValue &Hi); - - void ExpandIntRes_MINMAX (SDNode *N, SDValue &Lo, SDValue &Hi); - - void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_ADDSUBSAT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_MULFIX (SDNode *N, SDValue &Lo, SDValue &Hi); - - void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandIntRes_VECREDUCE (SDNode *N, SDValue &Lo, SDValue &Hi); - - void ExpandShiftByConstant(SDNode *N, const APInt &Amt, - SDValue &Lo, SDValue &Hi); - bool ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi); - bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi); - - // Integer Operand Expansion. - bool ExpandIntegerOperand(SDNode *N, unsigned OpNo); - SDValue ExpandIntOp_BR_CC(SDNode *N); - SDValue ExpandIntOp_SELECT_CC(SDNode *N); - SDValue ExpandIntOp_SETCC(SDNode *N); - SDValue ExpandIntOp_SETCCCARRY(SDNode *N); - SDValue ExpandIntOp_Shift(SDNode *N); - SDValue ExpandIntOp_SINT_TO_FP(SDNode *N); - SDValue ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo); - SDValue ExpandIntOp_TRUNCATE(SDNode *N); - SDValue ExpandIntOp_UINT_TO_FP(SDNode *N); - SDValue ExpandIntOp_RETURNADDR(SDNode *N); - SDValue ExpandIntOp_ATOMIC_STORE(SDNode *N); - - void IntegerExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode, const SDLoc &dl); - - //===--------------------------------------------------------------------===// - // Float to Integer Conversion Support: LegalizeFloatTypes.cpp - //===--------------------------------------------------------------------===// - - /// GetSoftenedFloat - Given a processed operand Op which was converted to an - /// integer of the same size, this returns the integer. The integer contains - /// exactly the same bits as Op - only the type changed. For example, if Op - /// is an f32 which was softened to an i32, then this method returns an i32, - /// the bits of which coincide with those of Op - SDValue GetSoftenedFloat(SDValue Op) { - TableId Id = getTableId(Op); - auto Iter = SoftenedFloats.find(Id); - if (Iter == SoftenedFloats.end()) { - assert(isSimpleLegalType(Op.getValueType()) && - "Operand wasn't converted to integer?"); - return Op; - } - SDValue SoftenedOp = getSDValue(Iter->second); - assert(SoftenedOp.getNode() && "Unconverted op in SoftenedFloats?"); - return SoftenedOp; - } - void SetSoftenedFloat(SDValue Op, SDValue Result); - - // Convert Float Results to Integer. - void SoftenFloatResult(SDNode *N, unsigned ResNo); - SDValue SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC); - SDValue SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC); - SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo); - SDValue SoftenFloatRes_BITCAST(SDNode *N); - SDValue SoftenFloatRes_BUILD_PAIR(SDNode *N); - SDValue SoftenFloatRes_ConstantFP(SDNode *N); - SDValue SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo); - SDValue SoftenFloatRes_FABS(SDNode *N); - SDValue SoftenFloatRes_FMINNUM(SDNode *N); - SDValue SoftenFloatRes_FMAXNUM(SDNode *N); - SDValue SoftenFloatRes_FADD(SDNode *N); - SDValue SoftenFloatRes_FCBRT(SDNode *N); - SDValue SoftenFloatRes_FCEIL(SDNode *N); - SDValue SoftenFloatRes_FCOPYSIGN(SDNode *N); - SDValue SoftenFloatRes_FCOS(SDNode *N); - SDValue SoftenFloatRes_FDIV(SDNode *N); - SDValue SoftenFloatRes_FEXP(SDNode *N); - SDValue SoftenFloatRes_FEXP2(SDNode *N); - SDValue SoftenFloatRes_FFLOOR(SDNode *N); - SDValue SoftenFloatRes_FLOG(SDNode *N); - SDValue SoftenFloatRes_FLOG2(SDNode *N); - SDValue SoftenFloatRes_FLOG10(SDNode *N); - SDValue SoftenFloatRes_FMA(SDNode *N); - SDValue SoftenFloatRes_FMUL(SDNode *N); - SDValue SoftenFloatRes_FNEARBYINT(SDNode *N); - SDValue SoftenFloatRes_FNEG(SDNode *N); - SDValue SoftenFloatRes_FP_EXTEND(SDNode *N); - SDValue SoftenFloatRes_FP16_TO_FP(SDNode *N); - SDValue SoftenFloatRes_FP_ROUND(SDNode *N); - SDValue SoftenFloatRes_FPOW(SDNode *N); - SDValue SoftenFloatRes_FPOWI(SDNode *N); - SDValue SoftenFloatRes_FREM(SDNode *N); - SDValue SoftenFloatRes_FRINT(SDNode *N); - SDValue SoftenFloatRes_FROUND(SDNode *N); - SDValue SoftenFloatRes_FSIN(SDNode *N); - SDValue SoftenFloatRes_FSQRT(SDNode *N); - SDValue SoftenFloatRes_FSUB(SDNode *N); - SDValue SoftenFloatRes_FTRUNC(SDNode *N); - SDValue SoftenFloatRes_LOAD(SDNode *N); - SDValue SoftenFloatRes_SELECT(SDNode *N); - SDValue SoftenFloatRes_SELECT_CC(SDNode *N); - SDValue SoftenFloatRes_UNDEF(SDNode *N); - SDValue SoftenFloatRes_VAARG(SDNode *N); - SDValue SoftenFloatRes_XINT_TO_FP(SDNode *N); - - // Convert Float Operand to Integer. - bool SoftenFloatOperand(SDNode *N, unsigned OpNo); - SDValue SoftenFloatOp_BITCAST(SDNode *N); - SDValue SoftenFloatOp_BR_CC(SDNode *N); - SDValue SoftenFloatOp_FP_EXTEND(SDNode *N); - SDValue SoftenFloatOp_FP_ROUND(SDNode *N); - SDValue SoftenFloatOp_FP_TO_XINT(SDNode *N); - SDValue SoftenFloatOp_LROUND(SDNode *N); - SDValue SoftenFloatOp_LLROUND(SDNode *N); - SDValue SoftenFloatOp_LRINT(SDNode *N); - SDValue SoftenFloatOp_LLRINT(SDNode *N); - SDValue SoftenFloatOp_SELECT_CC(SDNode *N); - SDValue SoftenFloatOp_SETCC(SDNode *N); - SDValue SoftenFloatOp_STORE(SDNode *N, unsigned OpNo); - SDValue SoftenFloatOp_FCOPYSIGN(SDNode *N); - - //===--------------------------------------------------------------------===// - // Float Expansion Support: LegalizeFloatTypes.cpp - //===--------------------------------------------------------------------===// - - /// Given a processed operand Op which was expanded into two floating-point - /// values of half the size, this returns the two halves. - /// The low bits of Op are exactly equal to the bits of Lo; the high bits - /// exactly equal Hi. For example, if Op is a ppcf128 which was expanded - /// into two f64's, then this method returns the two f64's, with Lo being - /// equal to the lower 64 bits of Op, and Hi to the upper 64 bits. - void GetExpandedFloat(SDValue Op, SDValue &Lo, SDValue &Hi); - void SetExpandedFloat(SDValue Op, SDValue Lo, SDValue Hi); - - // Float Result Expansion. - void ExpandFloatResult(SDNode *N, unsigned ResNo); - void ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FABS (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FMINNUM (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FMAXNUM (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FADD (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FCBRT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FCEIL (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FCOPYSIGN (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FCOS (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FDIV (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FEXP (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FEXP2 (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FFLOOR (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FLOG (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FLOG2 (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FLOG10 (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FMA (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FMUL (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FNEARBYINT(SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FNEG (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FREM (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FROUND (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FSIN (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FSQRT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FSUB (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_FTRUNC (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi); - - // Float Operand Expansion. - bool ExpandFloatOperand(SDNode *N, unsigned OpNo); - SDValue ExpandFloatOp_BR_CC(SDNode *N); - SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N); - SDValue ExpandFloatOp_FP_ROUND(SDNode *N); - SDValue ExpandFloatOp_FP_TO_SINT(SDNode *N); - SDValue ExpandFloatOp_FP_TO_UINT(SDNode *N); - SDValue ExpandFloatOp_LROUND(SDNode *N); - SDValue ExpandFloatOp_LLROUND(SDNode *N); - SDValue ExpandFloatOp_LRINT(SDNode *N); - SDValue ExpandFloatOp_LLRINT(SDNode *N); - SDValue ExpandFloatOp_SELECT_CC(SDNode *N); - SDValue ExpandFloatOp_SETCC(SDNode *N); - SDValue ExpandFloatOp_STORE(SDNode *N, unsigned OpNo); - - void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, - ISD::CondCode &CCCode, const SDLoc &dl); - - //===--------------------------------------------------------------------===// - // Float promotion support: LegalizeFloatTypes.cpp - //===--------------------------------------------------------------------===// - - SDValue GetPromotedFloat(SDValue Op) { - TableId &PromotedId = PromotedFloats[getTableId(Op)]; - SDValue PromotedOp = getSDValue(PromotedId); - assert(PromotedOp.getNode() && "Operand wasn't promoted?"); - return PromotedOp; - } - void SetPromotedFloat(SDValue Op, SDValue Result); - - void PromoteFloatResult(SDNode *N, unsigned ResNo); - SDValue PromoteFloatRes_BITCAST(SDNode *N); - SDValue PromoteFloatRes_BinOp(SDNode *N); - SDValue PromoteFloatRes_ConstantFP(SDNode *N); - SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N); - SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N); - SDValue PromoteFloatRes_FMAD(SDNode *N); - SDValue PromoteFloatRes_FPOWI(SDNode *N); - SDValue PromoteFloatRes_FP_ROUND(SDNode *N); - SDValue PromoteFloatRes_LOAD(SDNode *N); - SDValue PromoteFloatRes_SELECT(SDNode *N); - SDValue PromoteFloatRes_SELECT_CC(SDNode *N); - SDValue PromoteFloatRes_UnaryOp(SDNode *N); - SDValue PromoteFloatRes_UNDEF(SDNode *N); - SDValue BitcastToInt_ATOMIC_SWAP(SDNode *N); - SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N); - - bool PromoteFloatOperand(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo); - SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo); - - //===--------------------------------------------------------------------===// - // Scalarization Support: LegalizeVectorTypes.cpp - //===--------------------------------------------------------------------===// - - /// Given a processed one-element vector Op which was scalarized to its - /// element type, this returns the element. For example, if Op is a v1i32, - /// Op = < i32 val >, this method returns val, an i32. - SDValue GetScalarizedVector(SDValue Op) { - TableId &ScalarizedId = ScalarizedVectors[getTableId(Op)]; - SDValue ScalarizedOp = getSDValue(ScalarizedId); - assert(ScalarizedOp.getNode() && "Operand wasn't scalarized?"); - return ScalarizedOp; - } - void SetScalarizedVector(SDValue Op, SDValue Result); - - // Vector Result Scalarization: <1 x ty> -> ty. - void ScalarizeVectorResult(SDNode *N, unsigned ResNo); - SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo); - SDValue ScalarizeVecRes_BinOp(SDNode *N); - SDValue ScalarizeVecRes_TernaryOp(SDNode *N); - SDValue ScalarizeVecRes_UnaryOp(SDNode *N); - SDValue ScalarizeVecRes_StrictFPOp(SDNode *N); - SDValue ScalarizeVecRes_OverflowOp(SDNode *N, unsigned ResNo); - SDValue ScalarizeVecRes_InregOp(SDNode *N); - SDValue ScalarizeVecRes_VecInregOp(SDNode *N); - - SDValue ScalarizeVecRes_BITCAST(SDNode *N); - SDValue ScalarizeVecRes_BUILD_VECTOR(SDNode *N); - SDValue ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N); - SDValue ScalarizeVecRes_FP_ROUND(SDNode *N); - SDValue ScalarizeVecRes_STRICT_FP_ROUND(SDNode *N); - SDValue ScalarizeVecRes_FPOWI(SDNode *N); - SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N); - SDValue ScalarizeVecRes_LOAD(LoadSDNode *N); - SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N); - SDValue ScalarizeVecRes_VSELECT(SDNode *N); - SDValue ScalarizeVecRes_SELECT(SDNode *N); - SDValue ScalarizeVecRes_SELECT_CC(SDNode *N); - SDValue ScalarizeVecRes_SETCC(SDNode *N); - SDValue ScalarizeVecRes_UNDEF(SDNode *N); - SDValue ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N); - - SDValue ScalarizeVecRes_MULFIX(SDNode *N); - - // Vector Operand Scalarization: <1 x ty> -> ty. - bool ScalarizeVectorOperand(SDNode *N, unsigned OpNo); - SDValue ScalarizeVecOp_BITCAST(SDNode *N); - SDValue ScalarizeVecOp_UnaryOp(SDNode *N); - SDValue ScalarizeVecOp_UnaryOp_StrictFP(SDNode *N); - SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N); - SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N); - SDValue ScalarizeVecOp_VSELECT(SDNode *N); - SDValue ScalarizeVecOp_VSETCC(SDNode *N); - SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); - SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo); - SDValue ScalarizeVecOp_STRICT_FP_ROUND(SDNode *N, unsigned OpNo); - SDValue ScalarizeVecOp_VECREDUCE(SDNode *N); - - //===--------------------------------------------------------------------===// - // Vector Splitting Support: LegalizeVectorTypes.cpp - //===--------------------------------------------------------------------===// - - /// Given a processed vector Op which was split into vectors of half the size, - /// this method returns the halves. The first elements of Op coincide with the - /// elements of Lo; the remaining elements of Op coincide with the elements of - /// Hi: Op is what you would get by concatenating Lo and Hi. - /// For example, if Op is a v8i32 that was split into two v4i32's, then this - /// method returns the two v4i32's, with Lo corresponding to the first 4 - /// elements of Op, and Hi to the last 4 elements. - void GetSplitVector(SDValue Op, SDValue &Lo, SDValue &Hi); - void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi); - - // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>. - void SplitVectorResult(SDNode *N, unsigned ResNo); - void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_InregOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_OverflowOp(SDNode *N, unsigned ResNo, - SDValue &Lo, SDValue &Hi); - - void SplitVecRes_MULFIX(SDNode *N, SDValue &Lo, SDValue &Hi); - - void SplitVecRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi); - void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi); - void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi); - void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo, - SDValue &Hi); - void SplitVecRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi); - - // Vector Operand Splitting: <128 x ty> -> 2 x <64 x ty>. - bool SplitVectorOperand(SDNode *N, unsigned OpNo); - SDValue SplitVecOp_VSELECT(SDNode *N, unsigned OpNo); - SDValue SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo); - SDValue SplitVecOp_UnaryOp(SDNode *N); - SDValue SplitVecOp_TruncateHelper(SDNode *N); - - SDValue SplitVecOp_BITCAST(SDNode *N); - SDValue SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N); - SDValue SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N); - SDValue SplitVecOp_ExtVecInRegOp(SDNode *N); - SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo); - SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo); - SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo); - SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *MGT, unsigned OpNo); - SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N); - SDValue SplitVecOp_VSETCC(SDNode *N); - SDValue SplitVecOp_FP_ROUND(SDNode *N); - SDValue SplitVecOp_FCOPYSIGN(SDNode *N); - - //===--------------------------------------------------------------------===// - // Vector Widening Support: LegalizeVectorTypes.cpp - //===--------------------------------------------------------------------===// - - /// Given a processed vector Op which was widened into a larger vector, this - /// method returns the larger vector. The elements of the returned vector - /// consist of the elements of Op followed by elements containing rubbish. - /// For example, if Op is a v2i32 that was widened to a v4i32, then this - /// method returns a v4i32 for which the first two elements are the same as - /// those of Op, while the last two elements contain rubbish. - SDValue GetWidenedVector(SDValue Op) { - TableId &WidenedId = WidenedVectors[getTableId(Op)]; - SDValue WidenedOp = getSDValue(WidenedId); - assert(WidenedOp.getNode() && "Operand wasn't widened?"); - return WidenedOp; - } - void SetWidenedVector(SDValue Op, SDValue Result); - - // Widen Vector Result Promotion. - void WidenVectorResult(SDNode *N, unsigned ResNo); - SDValue WidenVecRes_MERGE_VALUES(SDNode* N, unsigned ResNo); - SDValue WidenVecRes_BITCAST(SDNode* N); - SDValue WidenVecRes_BUILD_VECTOR(SDNode* N); - SDValue WidenVecRes_CONCAT_VECTORS(SDNode* N); - SDValue WidenVecRes_EXTEND_VECTOR_INREG(SDNode* N); - SDValue WidenVecRes_EXTRACT_SUBVECTOR(SDNode* N); - SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N); - SDValue WidenVecRes_LOAD(SDNode* N); - SDValue WidenVecRes_MLOAD(MaskedLoadSDNode* N); - SDValue WidenVecRes_MGATHER(MaskedGatherSDNode* N); - SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N); - SDValue WidenVecRes_SELECT(SDNode* N); - SDValue WidenVSELECTAndMask(SDNode *N); - SDValue WidenVecRes_SELECT_CC(SDNode* N); - SDValue WidenVecRes_SETCC(SDNode* N); - SDValue WidenVecRes_UNDEF(SDNode *N); - SDValue WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N); - - SDValue WidenVecRes_Ternary(SDNode *N); - SDValue WidenVecRes_Binary(SDNode *N); - SDValue WidenVecRes_BinaryCanTrap(SDNode *N); - SDValue WidenVecRes_BinaryWithExtraScalarOp(SDNode *N); - SDValue WidenVecRes_StrictFP(SDNode *N); - SDValue WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo); - SDValue WidenVecRes_Convert(SDNode *N); - SDValue WidenVecRes_Convert_StrictFP(SDNode *N); - SDValue WidenVecRes_FCOPYSIGN(SDNode *N); - SDValue WidenVecRes_POWI(SDNode *N); - SDValue WidenVecRes_Shift(SDNode *N); - SDValue WidenVecRes_Unary(SDNode *N); - SDValue WidenVecRes_InregOp(SDNode *N); - - // Widen Vector Operand. - bool WidenVectorOperand(SDNode *N, unsigned OpNo); - SDValue WidenVecOp_BITCAST(SDNode *N); - SDValue WidenVecOp_CONCAT_VECTORS(SDNode *N); - SDValue WidenVecOp_EXTEND(SDNode *N); - SDValue WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N); - SDValue WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N); - SDValue WidenVecOp_STORE(SDNode* N); - SDValue WidenVecOp_MSTORE(SDNode* N, unsigned OpNo); - SDValue WidenVecOp_MGATHER(SDNode* N, unsigned OpNo); - SDValue WidenVecOp_MSCATTER(SDNode* N, unsigned OpNo); - SDValue WidenVecOp_SETCC(SDNode* N); - SDValue WidenVecOp_VSELECT(SDNode *N); - - SDValue WidenVecOp_Convert(SDNode *N); - SDValue WidenVecOp_FCOPYSIGN(SDNode *N); - SDValue WidenVecOp_VECREDUCE(SDNode *N); - - /// Helper function to generate a set of operations to perform - /// a vector operation for a wider type. - /// - SDValue UnrollVectorOp_StrictFP(SDNode *N, unsigned ResNE); - - //===--------------------------------------------------------------------===// - // Vector Widening Utilities Support: LegalizeVectorTypes.cpp - //===--------------------------------------------------------------------===// - - /// Helper function to generate a set of loads to load a vector with a - /// resulting wider type. It takes: - /// LdChain: list of chains for the load to be generated. - /// Ld: load to widen - SDValue GenWidenVectorLoads(SmallVectorImpl &LdChain, - LoadSDNode *LD); - - /// Helper function to generate a set of extension loads to load a vector with - /// a resulting wider type. It takes: - /// LdChain: list of chains for the load to be generated. - /// Ld: load to widen - /// ExtType: extension element type - SDValue GenWidenVectorExtLoads(SmallVectorImpl &LdChain, - LoadSDNode *LD, ISD::LoadExtType ExtType); - - /// Helper function to generate a set of stores to store a widen vector into - /// non-widen memory. - /// StChain: list of chains for the stores we have generated - /// ST: store of a widen value - void GenWidenVectorStores(SmallVectorImpl &StChain, StoreSDNode *ST); - - /// Helper function to generate a set of stores to store a truncate widen - /// vector into non-widen memory. - /// StChain: list of chains for the stores we have generated - /// ST: store of a widen value - void GenWidenVectorTruncStores(SmallVectorImpl &StChain, - StoreSDNode *ST); - - /// Modifies a vector input (widen or narrows) to a vector of NVT. The - /// input vector must have the same element type as NVT. - /// When FillWithZeroes is "on" the vector will be widened with zeroes. - /// By default, the vector will be widened with undefined values. - SDValue ModifyToType(SDValue InOp, EVT NVT, bool FillWithZeroes = false); - - /// Return a mask of vector type MaskVT to replace InMask. Also adjust - /// MaskVT to ToMaskVT if needed with vector extension or truncation. - SDValue convertMask(SDValue InMask, EVT MaskVT, EVT ToMaskVT); - - //===--------------------------------------------------------------------===// - // Generic Splitting: LegalizeTypesGeneric.cpp - //===--------------------------------------------------------------------===// - - // Legalization methods which only use that the illegal type is split into two - // not necessarily identical types. As such they can be used for splitting - // vectors and expanding integers and floats. - - void GetSplitOp(SDValue Op, SDValue &Lo, SDValue &Hi) { - if (Op.getValueType().isVector()) - GetSplitVector(Op, Lo, Hi); - else if (Op.getValueType().isInteger()) - GetExpandedInteger(Op, Lo, Hi); - else - GetExpandedFloat(Op, Lo, Hi); - } - - /// Use ISD::EXTRACT_ELEMENT nodes to extract the low and high parts of the - /// given value. - void GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi); - - // Generic Result Splitting. - void SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, - SDValue &Lo, SDValue &Hi); - void SplitRes_SELECT (SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitRes_SELECT_CC (SDNode *N, SDValue &Lo, SDValue &Hi); - void SplitRes_UNDEF (SDNode *N, SDValue &Lo, SDValue &Hi); - - void SplitVSETCC(const SDNode *N); - - //===--------------------------------------------------------------------===// - // Generic Expansion: LegalizeTypesGeneric.cpp - //===--------------------------------------------------------------------===// - - // Legalization methods which only use that the illegal type is split into two - // identical types of half the size, and that the Lo/Hi part is stored first - // in memory on little/big-endian machines, followed by the Hi/Lo part. As - // such they can be used for expanding integers and floats. - - void GetExpandedOp(SDValue Op, SDValue &Lo, SDValue &Hi) { - if (Op.getValueType().isInteger()) - GetExpandedInteger(Op, Lo, Hi); - else - GetExpandedFloat(Op, Lo, Hi); - } - - - /// This function will split the integer \p Op into \p NumElements - /// operations of type \p EltVT and store them in \p Ops. - void IntegerToVector(SDValue Op, unsigned NumElements, - SmallVectorImpl &Ops, EVT EltVT); - - // Generic Result Expansion. - void ExpandRes_MERGE_VALUES (SDNode *N, unsigned ResNo, - SDValue &Lo, SDValue &Hi); - void ExpandRes_BITCAST (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandRes_BUILD_PAIR (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandRes_EXTRACT_ELEMENT (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandRes_NormalLoad (SDNode *N, SDValue &Lo, SDValue &Hi); - void ExpandRes_VAARG (SDNode *N, SDValue &Lo, SDValue &Hi); - - // Generic Operand Expansion. - SDValue ExpandOp_BITCAST (SDNode *N); - SDValue ExpandOp_BUILD_VECTOR (SDNode *N); - SDValue ExpandOp_EXTRACT_ELEMENT (SDNode *N); - SDValue ExpandOp_INSERT_VECTOR_ELT(SDNode *N); - SDValue ExpandOp_SCALAR_TO_VECTOR (SDNode *N); - SDValue ExpandOp_NormalStore (SDNode *N, unsigned OpNo); -}; - -} // end namespace llvm. - -#endif Index: llvm/test/CodeGen/X86/fp128-libcalls-strict.ll =================================================================== --- llvm/test/CodeGen/X86/fp128-libcalls-strict.ll +++ llvm/test/CodeGen/X86/fp128-libcalls-strict.ll @@ -1,10 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \ +; RUN: llc < %s -O2 -mtriple=x86_64-linux-android \ ; RUN: -enable-legalize-types-checking \ ; RUN: -disable-strictnode-mutation | FileCheck %s -; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \ +; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu \ ; RUN: -enable-legalize-types-checking \ ; RUN: -disable-strictnode-mutation | FileCheck %s +; RUN: llc < %s -O2 -mtriple=i686-linux-gnu -mattr=+sse2 \ +; RUN: -enable-legalize-types-checking \ +; RUN: -disable-strictnode-mutation | FileCheck %s --check-prefix=X86 ; Check all soft floating point library function calls. @@ -15,6 +18,39 @@ ; CHECK-NEXT: callq __addtf3 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: add: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll __addtf3 +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %add = call fp128 @llvm.experimental.constrained.fadd.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %add @@ -27,6 +63,39 @@ ; CHECK-NEXT: callq __subtf3 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: sub: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll __subtf3 +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %sub = call fp128 @llvm.experimental.constrained.fsub.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %sub @@ -39,6 +108,39 @@ ; CHECK-NEXT: callq __multf3 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: mul: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll __multf3 +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %mul = call fp128 @llvm.experimental.constrained.fmul.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %mul @@ -51,6 +153,39 @@ ; CHECK-NEXT: callq __divtf3 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: div: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll __divtf3 +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %div = call fp128 @llvm.experimental.constrained.fdiv.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %div @@ -63,6 +198,43 @@ ; CHECK-NEXT: callq fmal ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: fma: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll fmal +; X86-NEXT: addl $60, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %fma = call fp128 @llvm.experimental.constrained.fma.f128(fp128 %x, fp128 %y, fp128 %z, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %fma @@ -75,6 +247,39 @@ ; CHECK-NEXT: callq fmodl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: frem: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll fmodl +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %div = call fp128 @llvm.experimental.constrained.frem.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %div @@ -87,6 +292,35 @@ ; CHECK-NEXT: callq ceill ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: ceil: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll ceill +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %ceil = call fp128 @llvm.experimental.constrained.ceil.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %ceil @@ -99,6 +333,35 @@ ; CHECK-NEXT: callq cosl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: cos: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll cosl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %cos = call fp128 @llvm.experimental.constrained.cos.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %cos @@ -111,6 +374,35 @@ ; CHECK-NEXT: callq expl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: exp: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll expl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %exp = call fp128 @llvm.experimental.constrained.exp.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %exp @@ -123,6 +415,35 @@ ; CHECK-NEXT: callq exp2l ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: exp2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll exp2l +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %exp2 = call fp128 @llvm.experimental.constrained.exp2.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %exp2 @@ -135,6 +456,35 @@ ; CHECK-NEXT: callq floorl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: floor: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll floorl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %floor = call fp128 @llvm.experimental.constrained.floor.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %floor @@ -147,6 +497,35 @@ ; CHECK-NEXT: callq logl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: log: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll logl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %log = call fp128 @llvm.experimental.constrained.log.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %log @@ -159,6 +538,35 @@ ; CHECK-NEXT: callq log10l ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: log10: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll log10l +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %log10 = call fp128 @llvm.experimental.constrained.log10.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %log10 @@ -171,6 +579,35 @@ ; CHECK-NEXT: callq log2l ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: log2: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll log2l +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %log2 = call fp128 @llvm.experimental.constrained.log2.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %log2 @@ -183,6 +620,39 @@ ; CHECK-NEXT: callq fmaxl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: maxnum: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll fmaxl +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %maxnum = call fp128 @llvm.experimental.constrained.maxnum.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %maxnum @@ -195,6 +665,39 @@ ; CHECK-NEXT: callq fminl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: minnum: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll fminl +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %minnum = call fp128 @llvm.experimental.constrained.minnum.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %minnum @@ -207,6 +710,35 @@ ; CHECK-NEXT: callq nearbyintl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: nearbyint: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll nearbyintl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %nearbyint = call fp128 @llvm.experimental.constrained.nearbyint.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %nearbyint @@ -219,6 +751,39 @@ ; CHECK-NEXT: callq powl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: pow: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll powl +; X86-NEXT: addl $44, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %pow = call fp128 @llvm.experimental.constrained.pow.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %pow @@ -231,6 +796,36 @@ ; CHECK-NEXT: callq __powitf2 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: powi: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $8, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll __powitf2 +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %powi = call fp128 @llvm.experimental.constrained.powi.f128(fp128 %x, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %powi @@ -243,6 +838,35 @@ ; CHECK-NEXT: callq rintl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: rint: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll rintl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %rint = call fp128 @llvm.experimental.constrained.rint.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %rint @@ -255,6 +879,35 @@ ; CHECK-NEXT: callq roundl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: round: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll roundl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %round = call fp128 @llvm.experimental.constrained.round.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %round @@ -267,6 +920,35 @@ ; CHECK-NEXT: callq sinl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: sin: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll sinl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %sin = call fp128 @llvm.experimental.constrained.sin.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %sin @@ -279,6 +961,35 @@ ; CHECK-NEXT: callq sqrtl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: sqrt: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll sqrtl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %sqrt = call fp128 @llvm.experimental.constrained.sqrt.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %sqrt @@ -291,6 +1002,35 @@ ; CHECK-NEXT: callq truncl ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq +; +; X86-LABEL: trunc: +; X86: # %bb.0: # %entry +; X86-NEXT: pushl %edi +; X86-NEXT: pushl %esi +; X86-NEXT: subl $20, %esp +; X86-NEXT: movl {{[0-9]+}}(%esp), %esi +; X86-NEXT: subl $12, %esp +; X86-NEXT: leal {{[0-9]+}}(%esp), %eax +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl {{[0-9]+}}(%esp) +; X86-NEXT: pushl %eax +; X86-NEXT: calll truncl +; X86-NEXT: addl $28, %esp +; X86-NEXT: movl (%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edi, 8(%esi) +; X86-NEXT: movl %edx, 12(%esi) +; X86-NEXT: movl %eax, (%esi) +; X86-NEXT: movl %ecx, 4(%esi) +; X86-NEXT: movl %esi, %eax +; X86-NEXT: addl $20, %esp +; X86-NEXT: popl %esi +; X86-NEXT: popl %edi +; X86-NEXT: retl $4 entry: %trunc = call fp128 @llvm.experimental.constrained.trunc.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 ret fp128 %trunc